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authorDave Jones <davej@redhat.com>2011-03-11 15:33:26 -0500
committerDave Jones <davej@redhat.com>2011-03-11 15:33:26 -0500
commit5fe2a08dea0e35ba4d17e59fc3c778e1acfc95a0 (patch)
tree69e0e92ee6ddaca272a8c3437197d7a40dc82dfd
parent963298eea1b8ee97315b99e2c98163a8b11c283c (diff)
Some more IDA decoding
-rw-r--r--Intel/Intel.h1
-rw-r--r--Intel/MSR-IDA.c19
2 files changed, 18 insertions, 2 deletions
diff --git a/Intel/Intel.h b/Intel/Intel.h
index 838e6a4..d6e86b3 100644
--- a/Intel/Intel.h
+++ b/Intel/Intel.h
@@ -25,5 +25,6 @@ extern void Identify_Intel_family15(struct cpudata *cpu);
#define MSR_IA32_THERM_STATUS 0x19c
#define MSR_PM_THERM2_CTL 0x19d
#define MSR_IA32_MISC_ENABLE 0x1a0
+#define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
#endif /* _INTEL_H */
diff --git a/Intel/MSR-IDA.c b/Intel/MSR-IDA.c
index 235f992..f6072b5 100644
--- a/Intel/MSR-IDA.c
+++ b/Intel/MSR-IDA.c
@@ -22,7 +22,8 @@ void dump_IDA_MSRs(struct cpudata *cpu)
if (cpu->cpuid_level < 6)
return;
- cpuid_count(cpu->number, 6, 0, &eax, &ebx, &ecx, &edx);
+ cpuid(cpu->number, 6, &eax, &ebx, &ecx, &edx);
+
printf("Dynamic Acceleration MSRs:\n");
printf(" Opportunistic performance operation ");
if ((eax & (1 << 1)) == 1)
@@ -38,5 +39,19 @@ void dump_IDA_MSRs(struct cpudata *cpu)
return;
}
- printf("\n");
+ if (read_msr(cpu->number, MSR_IA32_PERF_CTL, &val) != 1)
+ return;
+ printf(" IA32_PERF_CTL: ");
+ if ((val & (1L << 32)) == 1) {
+ printf("IDA/Turbo DISENGAGE=1, ");
+ }
+ printf("EIST Transition target: 0x%x\n", (unsigned int) val & 0xff);
+
+
+ if (ecx & (1 << 3)) { /* SETBH present ? */
+ if (read_msr(cpu->number, MSR_IA32_ENERGY_PERF_BIAS, &val) != 1)
+ return;
+ printf(" IA32_ENERGY_PERF_BIAS: ");
+ printf("hint=%d\n", (unsigned int) val & 0xf);
+ }
}