i965: Fix some downloads of ASTC void-extent blocksjenkins

Use the generic shadow framework and blorp_copy_astc_wa() instead of
modifying the ASTC miptree data on texture upload.

Makes the following piglit test pass on big-core gen9 platforms:
spec@khr_texture_compression_astc@void-extent-dl-bug

5 files changed, 50 insertions, 88 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index c32e3d1f9c0..76a22a6bf57 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -266,6 +266,26 @@ swizzle_to_scs(GLenum swizzle)
    return (enum isl_channel_select)((swizzle + 4) & 7);
 }
 
+void
+brw_blorp_copy_astc_wa(struct brw_context *brw,
+                       struct intel_mipmap_tree *src_mt,
+                       struct intel_mipmap_tree *dst_mt,
+                       unsigned level, unsigned layer)
+{
+   struct blorp_surf src_surf, dst_surf;
+   unsigned src_level = level;
+   unsigned dst_level = level;
+   blorp_surf_for_miptree(brw, &src_surf, src_mt, ISL_AUX_USAGE_NONE, false,
+                          &src_level, layer, 1);
+   blorp_surf_for_miptree(brw, &dst_surf, dst_mt, ISL_AUX_USAGE_NONE, true,
+                          &dst_level, layer, 1);
+
+   struct blorp_batch batch;
+   blorp_batch_init(&brw->blorp, &batch, brw, 0);
+   blorp_copy_astc_wa(&batch, &src_surf, &dst_surf, dst_level, layer);
+   blorp_batch_finish(&batch);
+}
+
 /**
  * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
  * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index 551e1fcdcba..ba0d5679a04 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -35,6 +35,12 @@ extern "C" {
 void brw_blorp_init(struct brw_context *brw);
 
 void
+brw_blorp_copy_astc_wa(struct brw_context *brw,
+                       struct intel_mipmap_tree *src_mt,
+                       struct intel_mipmap_tree *dst_mt,
+                       unsigned level, unsigned layer);
+
+void
 brw_blorp_blit_miptrees(struct brw_context *brw,
                         struct intel_mipmap_tree *src_mt,
                         unsigned src_level, unsigned src_layer,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f7229a45c5b..a3d8350ba13 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3662,6 +3662,14 @@ need_etc_shadow(const struct gen_device_info *devinfo, mesa_format format)
           (_mesa_is_format_etc2(format) || format == MESA_FORMAT_ETC1_RGB8);
 }
 
+static bool
+need_astc_shadow(const struct gen_device_info *devinfo, mesa_format format)
+{
+   return devinfo->gen == 9 && !gen_device_info_is_9lp(devinfo) &&
+          _mesa_get_format_layout(format) == MESA_FORMAT_LAYOUT_ASTC &&
+          _mesa_get_format_color_encoding(format) == GL_LINEAR;
+}
+
 void
 intel_miptree_prepare_shadow_texture(struct brw_context *brw,
                                      struct intel_mipmap_tree *mt,
@@ -3699,6 +3707,17 @@ intel_miptree_prepare_shadow_texture(struct brw_context *brw,
                          mt->surf.logical_level0_px.array_len,
                          mt->surf.samples, ISL_TILING_Y0_BIT,
                          mt_surf_usage(view_format), 0, 0, NULL);
+      } else if (need_astc_shadow(devinfo, view_format)) {
+         mt->shadow_mt =
+            make_surface(brw, mt->target, view_format,
+                         mt->first_level, mt->last_level,
+                         mt->surf.logical_level0_px.width,
+                         mt->surf.logical_level0_px.height,
+                         mt->surf.dim == ISL_SURF_DIM_3D ?
+                         mt->surf.logical_level0_px.depth :
+                         mt->surf.logical_level0_px.array_len,
+                         mt->surf.samples, ISL_TILING_Y0_BIT,
+                         mt_surf_usage(view_format), BO_ALLOC_BUSY, 0, NULL);
       } else {
          assert(!mt->shadow_needs_update);
          return;
@@ -3726,6 +3745,8 @@ intel_miptree_prepare_shadow_texture(struct brw_context *brw,
             } else if (need_etc_shadow(devinfo, view_format)) {
                intel_miptree_update_etc_shadow(brw, mt, level, slice,
                                                width, height);
+            } else if (need_astc_shadow(devinfo, view_format)) {
+               brw_blorp_copy_astc_wa(brw, mt, mt->shadow_mt, level, slice);
             } else {
                unreachable("No shadow update method defined.");
             }
@@ -3757,7 +3778,8 @@ intel_miptree_for_texture(struct brw_context *brw,
    }
 
    if (need_stencil_shadow(devinfo, view_format) ||
-       need_etc_shadow(devinfo, view_format)) {
+       need_etc_shadow(devinfo, view_format) ||
+       need_astc_shadow(devinfo, view_format)) {
       assert(mt->shadow_mt);
       return mt->shadow_mt;
    }
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index c7044f6748c..345ff5bb0f3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -293,6 +293,7 @@ struct intel_mipmap_tree
     * - Stencil texturing (pre-BDW) as required by GL_ARB_stencil_texturing.
     * - To store the decompressed ETC/EAC data in case we emulate the ETC
     *   compression on Gen 7 or earlier GPUs.
+    * - Correctly sampling from ASTC LDR blocks on big-core gen9 platforms.
     */
    struct intel_mipmap_tree *shadow_mt;
    bool shadow_needs_update;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index ccaa9ef7474..691d7fd5fa1 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -839,98 +839,11 @@ intel_get_tex_sub_image(struct gl_context *ctx,
    DBG("%s - DONE\n", __func__);
 }
 
-static void
-flush_astc_denorms(struct gl_context *ctx, GLuint dims,
-                   struct gl_texture_image *texImage,
-                   GLint xoffset, GLint yoffset, GLint zoffset,
-                   GLsizei width, GLsizei height, GLsizei depth)
-{
-   struct compressed_pixelstore store;
-   _mesa_compute_compressed_pixelstore(dims, texImage->TexFormat,
-                                       width, height, depth,
-                                       &ctx->Unpack, &store);
-
-   for (int slice = 0; slice < store.CopySlices; slice++) {
-
-      /* Map dest texture buffer */
-      GLubyte *dstMap;
-      GLint dstRowStride;
-      ctx->Driver.MapTextureImage(ctx, texImage, slice + zoffset,
-                                  xoffset, yoffset, width, height,
-                                  GL_MAP_READ_BIT | GL_MAP_WRITE_BIT,
-                                  &dstMap, &dstRowStride);
-      if (!dstMap)
-         continue;
-
-      for (int i = 0; i < store.CopyRowsPerSlice; i++) {
-
-         /* An ASTC block is stored in little endian mode. The byte that
-          * contains bits 0..7 is stored at the lower address in memory.
-          */
-         struct astc_void_extent {
-            uint16_t header : 12;
-            uint16_t dontcare[3];
-            uint16_t R;
-            uint16_t G;
-            uint16_t B;
-            uint16_t A;
-         } *blocks = (struct astc_void_extent*) dstMap;
-
-         /* Iterate over every copied block in the row */
-         for (int j = 0; j < store.CopyBytesPerRow / 16; j++) {
-
-            /* Check if the header matches that of an LDR void-extent block */
-            if (blocks[j].header == 0xDFC) {
-
-               /* Flush UNORM16 values that would be denormalized */
-               if (blocks[j].A < 4) blocks[j].A = 0;
-               if (blocks[j].B < 4) blocks[j].B = 0;
-               if (blocks[j].G < 4) blocks[j].G = 0;
-               if (blocks[j].R < 4) blocks[j].R = 0;
-            }
-         }
-
-         dstMap += dstRowStride;
-      }
-
-      ctx->Driver.UnmapTextureImage(ctx, texImage, slice + zoffset);
-   }
-}
-
-
-static void
-intelCompressedTexSubImage(struct gl_context *ctx, GLuint dims,
-                        struct gl_texture_image *texImage,
-                        GLint xoffset, GLint yoffset, GLint zoffset,
-                        GLsizei width, GLsizei height, GLsizei depth,
-                        GLenum format,
-                        GLsizei imageSize, const GLvoid *data)
-{
-   /* Upload the compressed data blocks */
-   _mesa_store_compressed_texsubimage(ctx, dims, texImage,
-                                      xoffset, yoffset, zoffset,
-                                      width, height, depth,
-                                      format, imageSize, data);
-
-   /* Fix up copied ASTC blocks if necessary */
-   GLenum gl_format = _mesa_compressed_format_to_glenum(ctx,
-                                                        texImage->TexFormat);
-   bool is_linear_astc = _mesa_is_astc_format(gl_format) &&
-                        !_mesa_is_srgb_format(gl_format);
-   struct brw_context *brw = (struct brw_context*) ctx;
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   if (devinfo->gen == 9 && !gen_device_info_is_9lp(devinfo) && is_linear_astc)
-      flush_astc_denorms(ctx, dims, texImage,
-                         xoffset, yoffset, zoffset,
-                         width, height, depth);
-}
-
 void
 intelInitTextureImageFuncs(struct dd_function_table *functions)
 {
    functions->TexImage = intelTexImage;
    functions->TexSubImage = intelTexSubImage;
-   functions->CompressedTexSubImage = intelCompressedTexSubImage;
    functions->EGLImageTargetTexture2D = intel_image_target_texture_2d;
    functions->BindRenderbufferTexImage = intel_bind_renderbuffer_tex_image;
    functions->GetTexSubImage = intel_get_tex_sub_image;