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Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_blorp.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index c32e3d1f9c0..76a22a6bf57 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -266,6 +266,26 @@ swizzle_to_scs(GLenum swizzle)
return (enum isl_channel_select)((swizzle + 4) & 7);
}
+void
+brw_blorp_copy_astc_wa(struct brw_context *brw,
+ struct intel_mipmap_tree *src_mt,
+ struct intel_mipmap_tree *dst_mt,
+ unsigned level, unsigned layer)
+{
+ struct blorp_surf src_surf, dst_surf;
+ unsigned src_level = level;
+ unsigned dst_level = level;
+ blorp_surf_for_miptree(brw, &src_surf, src_mt, ISL_AUX_USAGE_NONE, false,
+ &src_level, layer, 1);
+ blorp_surf_for_miptree(brw, &dst_surf, dst_mt, ISL_AUX_USAGE_NONE, true,
+ &dst_level, layer, 1);
+
+ struct blorp_batch batch;
+ blorp_batch_init(&brw->blorp, &batch, brw, 0);
+ blorp_copy_astc_wa(&batch, &src_surf, &dst_surf, dst_level, layer);
+ blorp_batch_finish(&batch);
+}
+
/**
* Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
* INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is