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2017-09-21intel: Change a KBL pci id to GT2 from GT1.5Anuj Phogat1-2/+2
See Mesa commit 9c588ff Cc: Matt Turner <mattst88@gmail.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30intel/intel_chipset: Move IS_9XX below IS_GEN10.Rodrigo Vivi1-9/+9
No functional change. Just organizing the code so it gets clear for future platforms. Paulo deserves credits becuase he was the one that just noticed this IS_9XX was in the wrong position after CNL patches got introduced. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30intel: add GEN10 to IS_9XX.Paulo Zanoni1-1/+2
As far as I understand, IS_9XX should return true for it. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30intel/gen10: Add missed gen10 stuffBen Widawsky2-1/+5
This got lost on rebase, I believe Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30intel: Add Cannonlake PCI IDs for Y-skus.Rodrigo Vivi1-1/+15
By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for reference. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-06-30intel: Add Cannonlake PCI IDs for U-skus.Rodrigo Vivi1-0/+13
Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy of merged i915's commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.") v2: Remove PCI IDs for SKU not mentioned in spec. v3: Add kernel commit id for reference. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-06-29intel: PCI Ids for U SKU in CFLAnusha Srivatsa1-1/+11
Add the PCI IDs for U SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29intel: PCI Ids for H SKU in CFLAnusha Srivatsa1-1/+7
Add the PCI IDs for H SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29intel: PCI Ids for S SKU in CFLAnusha Srivatsa1-1/+16
Add the PCI IDs for S SKU IN CFL by following the spec. v2: Update IDs. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-04-10intel: remove dead codeEric Engestrom1-1/+0
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2017-03-08intel: Add handle to hashtable before freeing along an error pathChris Wilson1-4/+4
drm_intel_gem_bo_free() unconditionally attempts to remove the handle from the hashtable. This goes horribly wrong if we haven't already added the bo to the hashtable. Reported-by: Michael Thayer <michael.thayer@oracle.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-02-28intel: avoid null pointer dereferenceThomas Hindoe Paaboel Andersen1-1/+2
Move the dereference after the null check. Fixes: 028715ee707469189505 ("intel: Avoid the need for most overflow checks by using a scratch page.") Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-02-11intel: Move 48b support to bo_gem->kflagsChris Wilson1-16/+5
Another boolean that can be set and used along side the other execobject flags. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-02-11intel: Move is_softpin to obj->kflagsChris Wilson1-18/+11
Use obj->kflags to set EXEC_OBJECT_PINNED when the object is softpinned, and so remember to clear the softpin status when the object is freed (and reused). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-28intel: fix make distcheckDave Airlie1-0/+4
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-27intel: Export a function to re-enable implicit synchronisationChris Wilson2-0/+20
Implicit synchronisation is the default behaviour of the kernel when rendering with an execobject. It may be disabled with drm_intel_gem_bo_disable_implicit_sync(), and then to restore it use drm_intel_gem_bo_enable_implicit_sync(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27intel: Clear execobject flags before preserving object in reuse cacheChris Wilson1-0/+2
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27intel: Support passing of explicit fencing from execbufChris Wilson2-4/+33
Allow the caller to pass in an fd to an array of fences to control serialisation of the execbuf in the kernel and on the GPU, and in return allow creation of a fence fd for signaling the completion (and flushing) of the batch. When the returned fence is signaled, all writes to the buffers inside the batch will be complete and coherent from the cpu, or other consumers. The return fence is a sync_file object and can be passed to other users (such as atomic modesetting, or other drivers). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27intel: Allow the client to control implicit synchronisationChris Wilson2-4/+49
The kernel allows implicit synchronisation to be disabled on individual buffers. Use at your own risk. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27android: introduce Android.common.mk to reduce boilerplateEmil Velikov1-5/+2
... across the makefiles. Currently this isn't much but that will change shortly. As an added bonus this fixes all present and future cases where we've forgotten to strip out the headers from LOCAL_SRC_FILES. In a couple of cases (the tests) we start setting LOCAL_EXPORT_C_INCLUDE_DIRS, which shouldn't be an issue. Cc: Chih-Wei Huang <cwhuang@android-x86.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org>
2017-01-27android: remove LOCAL_MODULE_TAGS := optional tagEmil Velikov1-1/+0
Seems to be the default option since ~2009 with commit 2f31293ba78 "auto import from //branches/cupcake/...@137197". Fleshed out from a larger commit in the AOSP repo/fork. Cc: Dan Willemsen <dwillemsen@google.com> Cc: Chih-Wei Huang <cwhuang@android-x86.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org>
2017-01-15intel: update global_name before HASH_ADDDongwon Kim1-2/+3
bo->global_name should be updated first before a hash value for the entry is calculated with it by HASH_ADD macro. Signed-off-by: Dongwon Kim <dongwon.kim@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-11-22libdrm: random typo fixesGrazvydas Ignotas2-5/+5
Just some trivial boring typo fixes all over the tree. READMEs and comments only. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-11-22intel: Add drm_intel_gem_context_get_id to intel-symbols-checkMichel Dänzer1-0/+1
Fixes make check. Trivial.
2016-11-21intel: Add a getter for the intel_context ctx_idRobert Bragg2-0/+13
Exposing the u32 context ID makes it possible to define new drm kernel interfaces based on the same IDs that e.g. execbuf uses to identify a gem context, that aren't themselves abstracted by libdrm but need to be used by libdrm/drm_intel_context based clients such as (parts of) i-g-t or Mesa. For example this can be used to configure an i915-perf stream to collect metrics for a specific context. v2: s/drm_intel_gem_context_get_context_id/drm_intel_gem_context_get_id/ Signed-off-by: Robert Bragg <robert@sixbynine.org> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
2016-11-18intel: Add Geminilake PCI IDsBen Widawsky1-3/+10
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-11-14intel: Add uthash.h to Makefile.sources.Matt Turner1-1/+2
2016-11-14intel: Allow some codenames in INTEL_DEVID_OVERRIDENeil Roberts1-1/+29
As well as allowing a hexadecimal PCI ID number, the INTEL_DEVID_OVERRIDE environment variable can now contain one of a few short codenames. The codenames are stored in a small table to map them to a corresponding PCI ID. This makes it easier to use without having to look up the PCI IDs manually. The PCI IDs used are the same as those chosen for the -p option of run.c in shader-db but SKL has been added as well. Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-10-24intel: Look prime handle up in handle hash tableChris Wilson1-1/+1
A slightly confused copy'n'paste from the open path where we pass in handle but use it as a global name, in the prime handle-from-fd pass we pass in handle and do mean handle! References: https://bugs.freedesktop.org/show_bug.cgi?id=98416 Fixes: 2f23bf1b7b89 ("intel: Migrate handle/name lookups from linear lists...") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-10-24intel: Add new symbols to intel-symbol-checkMichel Dänzer1-0/+3
Fixes make check. Trivial.
2016-10-22intel: Migrate handle/name lookups from linear lists to hashtablesChris Wilson2-101/+1181
Walking a linear list to find a matching PRIME handle or flinked name does not scale and becomes a major burden with just a few objects. That said, the fixed size hash is not much better, it just buckets the look into a few separate chains rather than one long one. References: https://bugs.freedesktop.org/show_bug.cgi?id=94631 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-10-22intel: Export raw GEM mmap interfacesChris Wilson2-0/+158
Export a set of interfaces to allow the caller to have precise control over mapping the buffer - but still provide caching of the mmaps between callers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-09-08intel: Add new symbols to intel-symbol-checkMichel Dänzer1-0/+2
Fixes make check. Trivial.
2016-09-07intel: Export pooled EU and min no. of eus in a pool.Yang Rong2-0/+33
Update kernel interface with new I915_GETPARAM ioctl entries for pooled EU and min no. of eus in a pool. Add a wrapping function for each parameter. Userspace drivers need these values when decide the thread count. This kernel enabled pooled eu by default for BXT and for fused down 2x6 parts it is advised to turn it off. But there is another HW issue in these parts (fused down 2x6 parts) before C0 that requires Pooled EU to be enabled as a workaround. In this case the pool configuration changes depending upon which subslice is disabled and the no. of eus in a pool is different, So userspace need to know min no. of eus in a pool. V2: use return value as the query results. ret < 0 when error, ret = 0 when not support, and ret > 0 indicate query results.(Chris) V3: Correct V2 errors. Signed-off-by: Yang Rong <rong.r.yang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-07-23automake: Don't include Android Makefiles in the release tarballAndreas Boll1-1/+0
Currently only some Android Makefiles are included in the release tarball. To be more consistent one could either add the remaining files or don't ship Android Makefiles altogether. According to Emil the Android folk doesn't use our release tarballs. Thus it makes sense to remove those files from distribution which also means less work for maintenance in the future. Suggested-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-07-06Android: strip out header files from sources listRob Herring1-1/+1
AOSP master now errors if LOCAL_SRC_FILES contains headers, so filter out header files from the source lists. Signed-off-by: Rob Herring <robh@kernel.org>
2016-06-29intel: Removing PCI IDs that are no longer listed as Kabylake.Rodrigo Vivi1-13/+3
This is unusual. Usually IDs listed on early stages of platform definition are kept there as reserved for later use. However these IDs here are not listed anymore in any of steppings and devices IDs tables for Kabylake on configurations overview section of BSpec. So it is better removing them before they become used in any other future platform. v2: Rebase. Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2016-06-29intel: Add more Kabylake PCI IDs.Rodrigo Vivi1-4/+10
The spec has been updated adding new PCI IDs. v2: Avoid using "H" instead of HALO to keep names uniform - DK. Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2016-04-27intel/skl: Add missing SKL PCI IDsMichał Winiarski1-8/+16
Used by production devices: Intel(R) HD Graphics 510 Intel(R) HD Graphics 535 Intel(R) Iris(TM) Graphics 550 Intel(R) Iris(TM) Graphics P555 Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-07intel: Fix spelling mistakesEric Engestrom5-5/+5
Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-03-02intel: Adding missing Broxton PCI IDs.Rodrigo Vivi1-1/+5
These IDs were already part of the kernel since: kernel commit 985dd4360fdf2533fe48a33a4a2094f2e4718dc0 Author: Imre Deak <imre.deak@intel.com> Date: Thu Jan 28 16:04:12 2016 +0200 drm/i915/bxt: update list of PCIIDs Cc: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
2016-01-20configure.ac: disable annoying warning -Wmissing-field-initializersMarek Olšák1-2/+0
It warns for all "{}" initializers. Reviewed-by: David Herrmann <dh.herrmann@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-06intel/kbl: Add Kabylake PCI idsRodrigo Vivi1-1/+56
Also, following kernel definition Kabylake is skylake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2015-12-22intel: Restore formatting of offsets in debug statementsMichał Winiarski1-9/+14
Using lower_32_bits and upper_32_bits macros was accidentally dropped in: commit 8b4d57e7b75cb0bd01d11ad7f597909034a316aa Author: Michał Winiarski <michal.winiarski@intel.com> Date: Wed Sep 9 16:07:10 2015 +0200 intel: Add support for softpin Let's restore previous, more readable format. Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-14intel: Add drm_intel_bo_set_softpin_offset to intel-symbol-checkKristian Høgsberg Kristensen1-0/+1
Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-12-14intel: Add support for softpinMichał Winiarski4-27/+169
Softpin allows userspace to take greater control of GPU virtual address space and eliminates the need of relocations. It can also be used to mirror addresses between GPU and CPU (shared virtual memory). Calls to drm_intel_bo_emit_reloc are still required to build the list of drm_i915_gem_exec_objects at exec time, but no entries in relocs are created. Self-relocs don't make any sense for softpinned objects and can indicate a programming errors, thus are forbidden. Softpinned objects are marked by asterisk in debug dumps. Cc: Thomas Daniel <thomas.daniel@intel.com> Cc: Kristian Høgsberg <krh@bitplanet.net> Cc: Zou Nanhai <nanhai.zou@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2015-12-14intel: add drm_intel_bo_use_48b_address_range to symbol-check testMichel Thierry1-0/+1
Signed-off-by: Michel Thierry <michel.thierry@intel.com> Reviewed-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com> Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-12-14intel: 48b ppgtt support (EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag)Michel Thierry4-19/+95
Gen8+ supports 48-bit virtual addresses, but some objects must always be allocated inside the 32-bit address range. In specific, any resource used with flat/heapless (0x00000000-0xfffff000) General State Heap (GSH) or Instruction State Heap (ISH) must be in a 32-bit range, because the General State Offset and Instruction State Offset are limited to 32-bits. The i915 driver has been modified to provide a flag to set when the 4GB limit is not necessary in a given bo (EXEC_OBJECT_SUPPORTS_48B_ADDRESS). 48-bit range will only be used when explicitly requested. Callers to the existing drm_intel_bo_emit_reloc function should set the use_48b_address_range flag beforehand, in order to use full ppgtt range. v2: Make set/clear functions nops on pre-gen8 platforms, and use them internally in emit_reloc functions (Ben) s/48BADDRESS/48B_ADDRESS/ (Dave) v3: Keep set/clear functions internal, no-one needs to use them directly. v4: Don't set 48bit-support flag in emit reloc, check for ppgtt type before enabling set/clear function, print full offsets in debug statements, using port of lower_32_bits and upper_32_bits from linux kernel (Michał) References: http://lists.freedesktop.org/archives/intel-gfx/2015-July/072612.html Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Michał Winiarski <michal.winiarski@intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Reviewed-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com> Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-12-01intel: add the missing <strings.h> includeChih-Wei Huang1-0/+1
It defines the prototype of ffs that fixes the building error on Android 6.0 64-bit image. Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-11-03intel: Cleanup SKL PCI ID definitions.Ben Widawsky1-18/+22
This removes ones which aren't used, and adds some new ones. I kept the original names where possible. Cc: Kristian Høgsberg <krh@bitplanet.net> Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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