diff options
| author | Michał Winiarski <michal.winiarski@intel.com> | 2016-02-17 11:40:19 +0100 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2016-04-27 17:45:34 -0700 |
| commit | e3623d34cad0ac3f181b0deee0931df202b8f909 (patch) | |
| tree | cb8f974a2a8fa37139165b7045d257153a3fa8b0 /intel | |
| parent | 739b8886025b31f2f9d09a535c8ff3670bb1d036 (diff) | |
intel/skl: Add missing SKL PCI IDs
Used by production devices:
Intel(R) HD Graphics 510
Intel(R) HD Graphics 535
Intel(R) Iris(TM) Graphics 550
Intel(R) Iris(TM) Graphics P555
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'intel')
| -rw-r--r-- | intel/intel_chipset.h | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 8e42a40d..e2554c3f 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -168,6 +168,7 @@ #define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 #define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ +#define PCI_CHIP_SKYLAKE_H_GT1 0x190B #define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ #define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 #define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */ @@ -179,9 +180,12 @@ #define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D #define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E #define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */ -#define PCI_CHIP_SKYLAKE_GT3 0x1926 -#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ +#define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923 +#define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926 +#define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927 #define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A +#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ +#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D #define PCI_CHIP_SKYLAKE_DT_GT4 0x1932 #define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A #define PCI_CHIP_SKYLAKE_H_GT4 0x193B @@ -375,10 +379,11 @@ #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ IS_CHERRYVIEW(devid)) -#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT1) +#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_H_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_ULX_GT1) #define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ @@ -391,8 +396,11 @@ (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \ (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2) -#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_GT3 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT3) +#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \ + (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \ + (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \ + (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ + (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) #define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \ (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ |