Port TGSI backend to current llvm trunk

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

20 files changed, 178 insertions, 193 deletions

diff --git a/lib/Support/Triple.cpp b/lib/Support/Triple.cpp
index 1abb1fdf22d..1c12b6603b8 100644
--- a/lib/Support/Triple.cpp
+++ b/lib/Support/Triple.cpp
@@ -606,6 +606,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
   case Triple::spir64:
   case Triple::systemz:
   case Triple::tce:
+  case Triple::tgsi:
   case Triple::thumbeb:
   case Triple::wasm32:
   case Triple::wasm64:
@@ -1339,6 +1340,7 @@ Triple Triple::getBigEndianArchVariant() const {
   case Triple::sparcv9:
   case Triple::systemz:
   case Triple::tce:
+  case Triple::tgsi:
   case Triple::thumbeb:
     // Already big endian.
     break;
@@ -1362,6 +1364,7 @@ Triple Triple::getLittleEndianArchVariant() const {
   case Triple::sparcv9:
   case Triple::systemz:
   case Triple::tce:
+  case Triple::tgsi:
 
   // ARM is intentionally unsupported here, changing the architecture would
   // drop any arch suffixes.
diff --git a/lib/Target/TGSI/CMakeLists.txt b/lib/Target/TGSI/CMakeLists.txt
index 4882668a5b5..749f0d3e9d2 100644
--- a/lib/Target/TGSI/CMakeLists.txt
+++ b/lib/Target/TGSI/CMakeLists.txt
@@ -16,7 +16,6 @@ add_llvm_target(TGSICodeGen
   TGSIFrameLowering.cpp
   TGSISubtarget.cpp
   TGSITargetMachine.cpp
-  TGSISelectionDAGInfo.cpp
   TGSIRegisterInfo.cpp
   )
 
diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp b/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp
index ed8dd5eea46..d269c75c3d1 100644
--- a/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp
+++ b/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp
@@ -27,7 +27,7 @@ namespace {
          : MCInstPrinter(mai, mii, mri) {}
 
       virtual void printInst(const MCInst *mi, raw_ostream &os,
-                             StringRef annot);
+                             StringRef annot, const MCSubtargetInfo &STI);
       virtual void printRegName(raw_ostream &os, unsigned reg) const;
 
       // Autogenerated by tblgen.
@@ -42,7 +42,7 @@ namespace {
 #include "TGSIGenAsmWriter.inc"
 
 void TGSIMCInstPrinter::printInst(const MCInst *mi, raw_ostream &os,
-                                  StringRef annot) {
+                                  StringRef annot, const MCSubtargetInfo &STI) {
    printInstruction(mi, os);
    printAnnotation(os, annot);
 }
@@ -67,12 +67,11 @@ void TGSIMCInstPrinter::printOperand(const MCInst *mi, unsigned op_idx,
       assert(0);
 }
 
-MCInstPrinter *llvm::createTGSIMCInstPrinter(const Target &t,
+MCInstPrinter *llvm::createTGSIMCInstPrinter(const Triple &tt,
                                              unsigned SyntaxVariant,
                                              const MCAsmInfo &mai,
                                              const MCInstrInfo &mii,
-                                             const MCRegisterInfo &mri,
-                                             const MCSubtargetInfo &sti) {
+                                             const MCRegisterInfo &mri) {
    return new TGSIMCInstPrinter(mai, mii, mri);
 }
 
diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp b/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp
index c42e9fc68ce..edbb03b7cb4 100644
--- a/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp
+++ b/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp
@@ -33,7 +33,7 @@ using namespace llvm;
 
 namespace {
    struct TGSIMCAsmInfo : public MCAsmInfo {
-      explicit TGSIMCAsmInfo(const Target &T, StringRef TT) {
+      explicit TGSIMCAsmInfo(const Triple &TT) {
          IsLittleEndian = true;
          HasDotTypeDotSizeDirective = false;
       }
@@ -46,17 +46,16 @@ static MCInstrInfo *createTGSIMCInstrInfo() {
    return X;
 }
 
-static MCRegisterInfo *createTGSIMCRegisterInfo(StringRef TT) {
+static MCRegisterInfo *createTGSIMCRegisterInfo(const Triple &TT) {
    MCRegisterInfo *X = new MCRegisterInfo();
    InitTGSIMCRegisterInfo(X, TGSI::ADDR0);
    return X;
 }
 
-static MCSubtargetInfo *createTGSIMCSubtargetInfo(StringRef TT, StringRef CPU,
+static MCSubtargetInfo *createTGSIMCSubtargetInfo(const Triple &TT,
+                                                  StringRef CPU,
                                                   StringRef FS) {
-   MCSubtargetInfo *X = new MCSubtargetInfo();
-   InitTGSIMCSubtargetInfo(X, TT, CPU, FS);
-   return X;
+   return createTGSIMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 extern "C" void LLVMInitializeTGSITargetMC() {
diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.h b/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.h
index cd2e2d25d8c..c9617d9966a 100644
--- a/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.h
+++ b/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.h
@@ -14,6 +14,8 @@
 #ifndef TGSI_MC_TARGET_DESC_H
 #define TGSI_MC_TARGET_DESC_H
 
+#include "llvm/ADT/Triple.h"
+
 namespace llvm {
    class Target;
    class MCStreamer;
@@ -37,12 +39,11 @@ namespace llvm {
                                      bool RelaxAll,
                                      bool NoExecStack);
 
-   MCInstPrinter *createTGSIMCInstPrinter(const Target &t,
+   MCInstPrinter *createTGSIMCInstPrinter(const Triple &tt,
                                           unsigned SyntaxVariant,
                                           const MCAsmInfo &mai,
                                           const MCInstrInfo &mii,
-                                          const MCRegisterInfo &mri,
-                                          const MCSubtargetInfo &sti);
+                                          const MCRegisterInfo &mri);
 }
 
 // Defines symbolic names for TGSI registers.  This defines a mapping from
diff --git a/lib/Target/TGSI/TGSI.h b/lib/Target/TGSI/TGSI.h
index f4d75869711..e394d1050ec 100644
--- a/lib/Target/TGSI/TGSI.h
+++ b/lib/Target/TGSI/TGSI.h
@@ -25,7 +25,6 @@
 namespace llvm {
    class FunctionPass;
    class TGSITargetMachine;
-   class TargetLoweringObjectFile;
 
    FunctionPass *createTGSIISelDag(TGSITargetMachine &tm);
    FunctionPass *createTGSIBranchConvPass(const TGSITargetMachine &tm);
@@ -42,14 +41,20 @@ namespace llvm {
       };
    }
 
+#if 0
    namespace {
       inline bool isKernelFunction(const Function *f) {
          NamedMDNode *md = f->getParent()->getNamedMetadata("opencl.kernels");
 
          if (md) {
+            printf("isKernelFunction found md with %d operands\n");
             for (unsigned i = 0; i < md->getNumOperands(); ++i) {
-               Value *v = md->getOperand(i)->getOperand(0);
+	       auto *metaData = dyn_cast<ConstantAsMetadata>(md->getOperand(i)->getOperand(0));
 
+	       printf("isKernelFunction md %d %p\n", i, metaData);
+	       assert(metaData);
+
+	       Value *v = metaData->getValue();
                assert(v && isa<Function>(v));
 
                if (f == static_cast<Function *>(v))
@@ -60,5 +65,6 @@ namespace llvm {
          return false;
       }
    }
+#endif
 }
 #endif
diff --git a/lib/Target/TGSI/TGSIAsmPrinter.cpp b/lib/Target/TGSI/TGSIAsmPrinter.cpp
index 4c3a9f763b5..8a6f9febed5 100644
--- a/lib/Target/TGSI/TGSIAsmPrinter.cpp
+++ b/lib/Target/TGSI/TGSIAsmPrinter.cpp
@@ -25,7 +25,7 @@
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCExpr.h"
-#include "llvm/Target/Mangler.h"
+#include "llvm/IR/Mangler.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/TargetRegistry.h"
@@ -37,8 +37,9 @@ using namespace llvm;
 namespace {
    class TGSIAsmPrinter : public AsmPrinter {
    public:
-      explicit TGSIAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
-         : AsmPrinter(TM, Streamer) {}
+      explicit TGSIAsmPrinter(TargetMachine &TM,
+                              std::unique_ptr<MCStreamer> Streamer)
+         : AsmPrinter(TM, std::move(Streamer)) {}
 
       virtual const char *getPassName() const {
          return "TGSI Assembly Printer";
@@ -67,26 +68,25 @@ GetSymbolFromOperand(const MachineOperand &mo, AsmPrinter &ap) {
 
    } else {
       assert(mo.isSymbol() && "Isn't a symbol reference");
-      name += ap.MAI->getGlobalPrefix();
-      name += mo.getSymbolName();
+      ap.Mang->getNameWithPrefix(name, mo.getSymbolName(), ap.getDataLayout());
    }
 
-   return ap.OutContext.GetOrCreateSymbol(name.str());
+   return ap.OutContext.getOrCreateSymbol(name);
 }
 
 static MCOperand
 GetSymbolRef(const MachineOperand &mo, const MCSymbol *sym,
              AsmPrinter &printer) {
    MCContext &ctx = printer.OutContext;
-   const MCExpr *Expr = MCSymbolRefExpr::Create(sym, MCSymbolRefExpr::VK_None,
+   const MCExpr *Expr = MCSymbolRefExpr::create(sym, MCSymbolRefExpr::VK_None,
                                                 ctx);
 
    if (mo.getOffset())
-      Expr = MCBinaryExpr::CreateAdd(Expr,
-                                     MCConstantExpr::Create(mo.getOffset(), ctx),
+      Expr = MCBinaryExpr::createAdd(Expr,
+                                     MCConstantExpr::create(mo.getOffset(), ctx),
                                      ctx);
 
-   return MCOperand::CreateExpr(Expr);
+   return MCOperand::createExpr(Expr);
 }
 
 static void LowerMachineInstrToMCInst(const MachineInstr *mi, MCInst &mci,
@@ -99,17 +99,17 @@ static void LowerMachineInstrToMCInst(const MachineInstr *mi, MCInst &mci,
 
       switch (mo.getType()) {
          case MachineOperand::MO_Register:
-            mco = MCOperand::CreateReg(mo.getReg());
+            mco = MCOperand::createReg(mo.getReg());
             break;
          case MachineOperand::MO_Immediate:
-            mco = MCOperand::CreateImm(mo.getImm());
+            mco = MCOperand::createImm(mo.getImm());
             break;
          case MachineOperand::MO_FPImmediate:
-            mco = MCOperand::CreateFPImm(mo.getFPImm()->getValueAPF()
+            mco = MCOperand::createFPImm(mo.getFPImm()->getValueAPF()
                                          .convertToFloat());
             break;
          case MachineOperand::MO_MachineBasicBlock:
-            mco = MCOperand::CreateExpr(MCSymbolRefExpr::Create
+            mco = MCOperand::createExpr(MCSymbolRefExpr::create
                                         (mo.getMBB()->getSymbol(), ap.OutContext));
             break;
          case MachineOperand::MO_GlobalAddress:
@@ -135,20 +135,20 @@ static void LowerMachineInstrToMCInst(const MachineInstr *mi, MCInst &mci,
 void TGSIAsmPrinter::EmitInstruction(const MachineInstr *mi) {
    MCInst mci;
    LowerMachineInstrToMCInst(mi, mci, *this);
-   OutStreamer.EmitInstruction(mci);
+   OutStreamer->EmitInstruction(mci, getSubtargetInfo());
 }
 
 void TGSIAsmPrinter::EmitFunctionBodyStart() {
    MCInst mci;
 
    mci.setOpcode(TGSI::BGNSUB);
-   OutStreamer.EmitInstruction(mci);
+   OutStreamer->EmitInstruction(mci, getSubtargetInfo());
 }
 
 void TGSIAsmPrinter::EmitFunctionBodyEnd() {
    MCInst mci;
    mci.setOpcode(TGSI::ENDSUB);
-   OutStreamer.EmitInstruction(mci);
+   OutStreamer->EmitInstruction(mci, getSubtargetInfo());
 }
 
 extern "C" void LLVMInitializeTGSIAsmPrinter() {
diff --git a/lib/Target/TGSI/TGSIFrameLowering.cpp b/lib/Target/TGSI/TGSIFrameLowering.cpp
index b94bb1cb8d3..783fe052511 100644
--- a/lib/Target/TGSI/TGSIFrameLowering.cpp
+++ b/lib/Target/TGSI/TGSIFrameLowering.cpp
@@ -24,16 +24,18 @@
 
 using namespace llvm;
 
-void TGSIFrameLowering::emitPrologue(MachineFunction &mf) const {
-   MachineBasicBlock &mbb = mf.front();
+void TGSIFrameLowering::emitPrologue(MachineFunction &mf,
+                                     MachineBasicBlock &mbb) const {
    MachineFrameInfo *mfi = mf.getFrameInfo();
    const TGSIInstrInfo &tii =
-      *static_cast<const TGSIInstrInfo*>(mf.getTarget().getInstrInfo());
+      *static_cast<const TGSIInstrInfo*>(mf.getSubtarget().getInstrInfo());
    MachineBasicBlock::iterator mbbi = mbb.begin();
    DebugLoc dl;
 
    // Get the number of bytes to allocate from the FrameInfo
    int frame_sz = mfi->getStackSize();
+   if (frame_sz == 0)
+      return;
 
    BuildMI(mbb, mbbi, dl, tii.get(TGSI::UADDs), TGSI::TEMP0x)
       .addReg(TGSI::TEMP0x).addImm(frame_sz);
@@ -44,11 +46,13 @@ void TGSIFrameLowering::emitEpilogue(MachineFunction &mf,
    MachineBasicBlock::iterator mbbi = mbb.getLastNonDebugInstr();
    MachineFrameInfo *mfi = mf.getFrameInfo();
    const TGSIInstrInfo &tii =
-      *static_cast<const TGSIInstrInfo*>(mf.getTarget().getInstrInfo());
+      *static_cast<const TGSIInstrInfo*>(mf.getSubtarget().getInstrInfo());
    DebugLoc dl;
 
    // Get the number of bytes to allocate from the FrameInfo
    int frame_sz = mfi->getStackSize();
+   if (frame_sz == 0)
+      return;
 
    BuildMI(mbb, mbbi, dl, tii.get(TGSI::UADDs), TGSI::TEMP0x)
       .addReg(TGSI::TEMP0x).addImm(-frame_sz);
diff --git a/lib/Target/TGSI/TGSIFrameLowering.h b/lib/Target/TGSI/TGSIFrameLowering.h
index d376fb1985a..c920eab298c 100644
--- a/lib/Target/TGSI/TGSIFrameLowering.h
+++ b/lib/Target/TGSI/TGSIFrameLowering.h
@@ -15,7 +15,6 @@
 #define TGSI_FRAME_LOWERING_H
 
 #include "TGSI.h"
-#include "TGSISubtarget.h"
 #include "llvm/Target/TargetFrameLowering.h"
 
 namespace llvm {
@@ -28,7 +27,7 @@ namespace llvm {
          : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 16, 0), STI(sti) {
       }
 
-      void emitPrologue(MachineFunction &MF) const;
+      void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const;
       void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 
       bool hasFP(const MachineFunction &MF) const { return false; }
diff --git a/lib/Target/TGSI/TGSIISelDAGToDAG.cpp b/lib/Target/TGSI/TGSIISelDAGToDAG.cpp
index bf9908c5967..ae360e363d1 100644
--- a/lib/Target/TGSI/TGSIISelDAGToDAG.cpp
+++ b/lib/Target/TGSI/TGSIISelDAGToDAG.cpp
@@ -22,16 +22,20 @@ using namespace llvm;
 
 namespace {
    class TGSIDAGToDAGISel : public SelectionDAGISel {
-      const TGSISubtarget &Subtarget;
-      TGSITargetMachine& TM;
+      const TGSISubtarget *Subtarget;
    public:
       explicit TGSIDAGToDAGISel(TGSITargetMachine &tm)
-         : SelectionDAGISel(tm),
-           Subtarget(tm.getSubtarget<TGSISubtarget>()),
-           TM(tm) {
+         : SelectionDAGISel(tm) {
       }
 
-      SDNode *Select(SDNode *N);
+      bool runOnMachineFunction(MachineFunction &MF) override {
+         // Reset the subtarget each time through.
+         Subtarget = &MF.getSubtarget<TGSISubtarget>();
+         SelectionDAGISel::runOnMachineFunction(MF);
+         return true;
+      }
+
+      void Select(SDNode *N);
 
       // Complex Pattern Selectors.
       template<int addr_space>
@@ -49,25 +53,27 @@ namespace {
    };
 }
 
-SDNode *TGSIDAGToDAGISel::Select(SDNode *n) {
-   DebugLoc dl = n->getDebugLoc();
+void TGSIDAGToDAGISel::Select(SDNode *n) {
+   SDLoc dl(n);
 
    switch (n->getOpcode()) {
       case ISD::FrameIndex: {
          int fi = cast<FrameIndexSDNode>(n)->getIndex();
          SDValue tfi = CurDAG->getTargetFrameIndex(fi, MVT::i32);
 
-         return tfi.getNode();
+         ReplaceNode(n, tfi.getNode());
+         return;
       }
       case ISD::GlobalAddress: {
          const GlobalValue *gv = cast<GlobalAddressSDNode>(n)->getGlobal();
          SDValue tga = CurDAG->getTargetGlobalAddress(gv, dl, MVT::i32);
 
-         return tga.getNode();
+         ReplaceNode(n, tga.getNode());
+         return;
       }
    }
 
-   return SelectCode(n);
+   SelectCode(n);
 }
 
 FunctionPass *llvm::createTGSIISelDag(TGSITargetMachine &TM) {
@@ -87,7 +93,7 @@ bool TGSIDAGToDAGISel::SelectPtr(SDNode *p, SDValue &n, SDValue &r) {
       }
 
    } else {
-      if ((v = cast<MemSDNode>(p)->getSrcValue()) &&
+      if ((v = cast<MemSDNode>(p)->getMemOperand()->getValue()) &&
           (ptr = dyn_cast<PointerType>(v->getType())) &&
           ptr->getAddressSpace() == addr_space) {
          r = n;
@@ -101,15 +107,15 @@ bool TGSIDAGToDAGISel::SelectPtr(SDNode *p, SDValue &n, SDValue &r) {
 template<bool any_ok>
 bool TGSIDAGToDAGISel::SelectSrc(SDValue &v, SDValue &r) {
    SDNode *n = v.getNode();
-   DebugLoc dl = n->getDebugLoc();
+   SDLoc dl(n);
 
    if (ConstantSDNode *c = dyn_cast<ConstantSDNode>(n)) {
-      r = CurDAG->getTargetConstant(*c->getConstantIntValue(),
+      r = CurDAG->getTargetConstant(*c->getConstantIntValue(), dl,
                                     n->getValueType(0));
       return true;
 
    } else if (ConstantFPSDNode *c = dyn_cast<ConstantFPSDNode>(n)) {
-      r = CurDAG->getTargetConstantFP(*c->getConstantFPValue(),
+      r = CurDAG->getTargetConstantFP(*c->getConstantFPValue(), dl,
                                       n->getValueType(0));
       return true;
 
diff --git a/lib/Target/TGSI/TGSIISelLowering.cpp b/lib/Target/TGSI/TGSIISelLowering.cpp
index adae48452d5..0311581c3a5 100644
--- a/lib/Target/TGSI/TGSIISelLowering.cpp
+++ b/lib/Target/TGSI/TGSIISelLowering.cpp
@@ -43,7 +43,7 @@ TGSITargetLowering::LowerReturn(SDValue Chain,
                                 CallingConv::ID CallConv, bool isVarArg,
                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
                                 const SmallVectorImpl<SDValue> &OutVals,
-                                DebugLoc dl, SelectionDAG &DAG) const {
+                                const SDLoc &dl, SelectionDAG &DAG) const {
    SDValue Flag;
 
    // CCValAssign - represent the assignment of the return value to locations.
@@ -51,7 +51,7 @@ TGSITargetLowering::LowerReturn(SDValue Chain,
 
    // CCState - Info about the registers and stack slot.
    CCState ccinfo(CallConv, isVarArg, DAG.getMachineFunction(),
-                  getTargetMachine(), RVLocs, *DAG.getContext());
+                  RVLocs, *DAG.getContext());
 
    ccinfo.AnalyzeReturn(Outs, RetCC_TGSI);
 
@@ -78,7 +78,7 @@ SDValue
 TGSITargetLowering::LowerFormalArguments(SDValue Chain,
                                          CallingConv::ID CallConv, bool isVarArg,
                                          const SmallVectorImpl<ISD::InputArg> &Ins,
-                                         DebugLoc dl, SelectionDAG &DAG,
+                                         const SDLoc &dl, SelectionDAG &DAG,
                                          SmallVectorImpl<SDValue> &InVals) const {
    MachineFunction &mf = DAG.getMachineFunction();
    MachineRegisterInfo &reginfo = mf.getRegInfo();
@@ -86,8 +86,9 @@ TGSITargetLowering::LowerFormalArguments(SDValue Chain,
    // Assign locations to all of the incoming arguments.
    SmallVector<CCValAssign, 16> ArgLocs;
    CCState ccinfo(CallConv, isVarArg, DAG.getMachineFunction(),
-                  getTargetMachine(), ArgLocs, *DAG.getContext());
-   CCAssignFn *ccfn = (isKernelFunction(mf.getFunction()) ? KernCC_TGSI : FunCC_TGSI);
+                  ArgLocs, *DAG.getContext());
+   CCAssignFn *ccfn = KernCC_TGSI;
+   // (isKernelFunction(mf.getFunction()) ? KernCC_TGSI : FunCC_TGSI);
 
    ccinfo.AnalyzeFormalArguments(Ins, ccfn);
 
@@ -103,7 +104,7 @@ TGSITargetLowering::LowerFormalArguments(SDValue Chain,
          arg = DAG.getCopyFromReg(Chain, dl, vreg, vt);
 
       } else {
-         SDValue ptr = DAG.getConstant(va.getLocMemOffset(), MVT::i32);
+         SDValue ptr = DAG.getConstant(va.getLocMemOffset(), dl, MVT::i32);
 
          arg = DAG.getNode(TGSIISD::LOAD_INPUT, dl, vt, Chain, ptr);
       }
@@ -115,19 +116,27 @@ TGSITargetLowering::LowerFormalArguments(SDValue Chain,
 }
 
 SDValue
-TGSITargetLowering::LowerCall(SDValue Chain, SDValue Callee,
-                              CallingConv::ID CallConv, bool isVarArg,
-                              bool &isTailCall,
-                              const SmallVectorImpl<ISD::OutputArg> &Outs,
-                              const SmallVectorImpl<SDValue> &OutVals,
-                              const SmallVectorImpl<ISD::InputArg> &Ins,
-                              DebugLoc dl, SelectionDAG &DAG,
+TGSITargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
                               SmallVectorImpl<SDValue> &InVals) const {
+   SelectionDAG &DAG = CLI.DAG;
+   SDLoc dl = CLI.DL;
+   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
+   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
+   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
+   SDValue Chain = CLI.Chain;
+   SDValue Callee = CLI.Callee;
+   bool &isTailCall = CLI.IsTailCall;
+   ArgListTy &Args = CLI.getArgs();
+   Type *retTy = CLI.RetTy;
+   ImmutableCallSite *CS = CLI.CS;
+   CallingConv::ID CallConv = CLI.CallConv;
+   bool isVarArg = CLI.IsVarArg;
+
    SDValue InFlag;
    // Analyze operands of the call, assigning locations to each operand.
    SmallVector<CCValAssign, 16> ArgLocs;
    CCState ccinfo(CallConv, isVarArg, DAG.getMachineFunction(),
-                  DAG.getTarget(), ArgLocs, *DAG.getContext());
+                  ArgLocs, *DAG.getContext());
    ccinfo.AnalyzeCallOperands(Outs, FunCC_TGSI);
 
    // Walk the register assignments, inserting copies.
@@ -155,13 +164,13 @@ TGSITargetLowering::LowerCall(SDValue Chain, SDValue Callee,
    if (InFlag.getNode())
       Ops.push_back(InFlag);
 
-   Chain = DAG.getNode(TGSIISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
+   Chain = DAG.getNode(TGSIISD::CALL, dl, NodeTys, Ops);
    InFlag = Chain.getValue(1);
 
    // Assign locations to each value returned by this call.
    SmallVector<CCValAssign, 16> RVLocs;
    CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
-                  DAG.getTarget(), RVLocs, *DAG.getContext());
+                  RVLocs, *DAG.getContext());
 
    RVInfo.AnalyzeCallResult(Ins, RetCC_TGSI);
 
@@ -183,8 +192,9 @@ TGSITargetLowering::LowerCall(SDValue Chain, SDValue Callee,
 // TargetLowering Implementation
 //===----------------------------------------------------------------------===//
 
-TGSITargetLowering::TGSITargetLowering(TargetMachine &TM)
-   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
+TGSITargetLowering::TGSITargetLowering(TargetMachine &TM,
+                                       const TGSISubtarget &STI)
+   : TargetLowering(TM), Subtarget(&STI) {
 
    // Set up the register classes.
    addRegisterClass(MVT::i32, &TGSI::IRegsRegClass);
@@ -193,7 +203,7 @@ TGSITargetLowering::TGSITargetLowering(TargetMachine &TM)
    addRegisterClass(MVT::v4f32, &TGSI::FVRegsRegClass);
 
    setStackPointerRegisterToSaveRestore(TGSI::TEMP0);
-   computeRegisterProperties();
+   computeRegisterProperties(Subtarget->getRegisterInfo());
 
    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
diff --git a/lib/Target/TGSI/TGSIISelLowering.h b/lib/Target/TGSI/TGSIISelLowering.h
index 588125c5f5e..1aa96ebc091 100644
--- a/lib/Target/TGSI/TGSIISelLowering.h
+++ b/lib/Target/TGSI/TGSIISelLowering.h
@@ -19,6 +19,8 @@
 #include "TGSI.h"
 
 namespace llvm {
+   class TGSISubtarget;
+
    namespace TGSIISD {
       enum {
          FIRST_NUMBER = ISD::BUILTIN_OP_END,
@@ -29,36 +31,32 @@ namespace llvm {
    }
 
    class TGSITargetLowering : public TargetLowering {
+      const TGSISubtarget *Subtarget;
    public:
-      TGSITargetLowering(TargetMachine &TM);
-      virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+      TGSITargetLowering(TargetMachine &TM,
+                         const TGSISubtarget &STI);
+      SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
-      virtual const char *getTargetNodeName(unsigned Opcode) const;
+      const char *getTargetNodeName(unsigned Opcode) const override;
 
-      virtual SDValue
+      SDValue
       LowerFormalArguments(SDValue Chain,
                            CallingConv::ID CallConv,
                            bool isVarArg,
                            const SmallVectorImpl<ISD::InputArg> &Ins,
-                           DebugLoc dl, SelectionDAG &DAG,
-                           SmallVectorImpl<SDValue> &InVals) const;
+                           const SDLoc &dl, SelectionDAG &DAG,
+                           SmallVectorImpl<SDValue> &InVals) const override;
 
-      virtual SDValue
-      LowerCall(SDValue Chain, SDValue Callee,
-                CallingConv::ID CallConv, bool isVarArg,
-                bool &isTailCall,
-                const SmallVectorImpl<ISD::OutputArg> &Outs,
-                const SmallVectorImpl<SDValue> &OutVals,
-                const SmallVectorImpl<ISD::InputArg> &Ins,
-                DebugLoc dl, SelectionDAG &DAG,
-                SmallVectorImpl<SDValue> &InVals) const;
+      SDValue
+      LowerCall(TargetLowering::CallLoweringInfo &CLI,
+                SmallVectorImpl<SDValue> &InVals) const override;
 
-      virtual SDValue
+      SDValue
       LowerReturn(SDValue Chain,
                   CallingConv::ID CallConv, bool isVarArg,
                   const SmallVectorImpl<ISD::OutputArg> &Outs,
                   const SmallVectorImpl<SDValue> &OutVals,
-                  DebugLoc dl, SelectionDAG &DAG) const;
+                  const SDLoc &dl, SelectionDAG &DAG) const override;
    };
 }
 
diff --git a/lib/Target/TGSI/TGSIInstrInfo.cpp b/lib/Target/TGSI/TGSIInstrInfo.cpp
index 525a760b414..732adab916d 100644
--- a/lib/Target/TGSI/TGSIInstrInfo.cpp
+++ b/lib/Target/TGSI/TGSIInstrInfo.cpp
@@ -21,7 +21,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "TGSIGenInstrInfo.inc"
 
 using namespace llvm;
diff --git a/lib/Target/TGSI/TGSIRegisterInfo.td b/lib/Target/TGSI/TGSIRegisterInfo.td
index 43b9fd1af48..bc7703040c8 100644
--- a/lib/Target/TGSI/TGSIRegisterInfo.td
+++ b/lib/Target/TGSI/TGSIRegisterInfo.td
@@ -12,10 +12,10 @@
 //===----------------------------------------------------------------------===//
 
 let Namespace = "TGSI" in {
-    def sub_x  : SubRegIndex;
-    def sub_y  : SubRegIndex;
-    def sub_z  : SubRegIndex;
-    def sub_w  : SubRegIndex;
+    def sub_x  : SubRegIndex<32>;
+    def sub_y  : SubRegIndex<32>;
+    def sub_z  : SubRegIndex<32>;
+    def sub_w  : SubRegIndex<32>;
 
     class TGSIReg<string n, int id, int c> : Register<n> {
         let HWEncoding{11-0} = id;
diff --git a/lib/Target/TGSI/TGSISelectionDAGInfo.cpp b/lib/Target/TGSI/TGSISelectionDAGInfo.cpp
deleted file mode 100644
index 6faa560dc35..00000000000
--- a/lib/Target/TGSI/TGSISelectionDAGInfo.cpp
+++ /dev/null
@@ -1,23 +0,0 @@
-//===-- TGSISelectionDAGInfo.cpp - TGSI SelectionDAG Info ---------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the TGSISelectionDAGInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "tgsi-selectiondag-info"
-#include "TGSITargetMachine.h"
-using namespace llvm;
-
-TGSISelectionDAGInfo::TGSISelectionDAGInfo(const TGSITargetMachine &TM)
-   : TargetSelectionDAGInfo(TM) {
-}
-
-TGSISelectionDAGInfo::~TGSISelectionDAGInfo() {
-}
diff --git a/lib/Target/TGSI/TGSISelectionDAGInfo.h b/lib/Target/TGSI/TGSISelectionDAGInfo.h
deleted file mode 100644
index 799a841efc7..00000000000
--- a/lib/Target/TGSI/TGSISelectionDAGInfo.h
+++ /dev/null
@@ -1,30 +0,0 @@
-//===-- TGSISelectionDAGInfo.h - TGSI SelectionDAG Info -------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the TGSI subclass for TargetSelectionDAGInfo.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef TGSI_SELECTION_DAG_INFO_H
-#define TGSI_SELECTION_DAG_INFO_H
-
-#include "llvm/Target/TargetSelectionDAGInfo.h"
-
-namespace llvm {
-   class TGSITargetMachine;
-
-   class TGSISelectionDAGInfo : public TargetSelectionDAGInfo {
-   public:
-      explicit TGSISelectionDAGInfo(const TGSITargetMachine &TM);
-      ~TGSISelectionDAGInfo();
-   };
-
-}
-
-#endif
diff --git a/lib/Target/TGSI/TGSISubtarget.cpp b/lib/Target/TGSI/TGSISubtarget.cpp
index c6add741f80..4f7565cc514 100644
--- a/lib/Target/TGSI/TGSISubtarget.cpp
+++ b/lib/Target/TGSI/TGSISubtarget.cpp
@@ -11,6 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#define DEBUG_TYPE "tgsi-subtarget"
 #include "TGSISubtarget.h"
 #include "TGSI.h"
 #include "llvm/Support/TargetRegistry.h"
@@ -21,9 +22,12 @@
 
 using namespace llvm;
 
-TGSISubtarget::TGSISubtarget(const std::string &TT, const std::string &CPU,
-			     const std::string &FS) :
-   TGSIGenSubtargetInfo(TT, CPU, FS) {
+TGSISubtarget::TGSISubtarget(const Triple &TT, const std::string &CPU,
+			     const std::string &FS, TargetMachine &TM) :
+   TGSIGenSubtargetInfo(TT, CPU, FS),
+   InstrInfo(*this),
+   TLInfo(TM, *this),
+   FrameLowering(*this) {
 
    // Determine default and user specified characteristics
    std::string CPUName = CPU.empty() ? "TGSI" : CPU;
diff --git a/lib/Target/TGSI/TGSISubtarget.h b/lib/Target/TGSI/TGSISubtarget.h
index 6f434408cf9..7cffba4b6d4 100644
--- a/lib/Target/TGSI/TGSISubtarget.h
+++ b/lib/Target/TGSI/TGSISubtarget.h
@@ -14,6 +14,10 @@
 #ifndef TGSI_SUBTARGET_H
 #define TGSI_SUBTARGET_H
 
+#include "TGSIInstrInfo.h"
+#include "TGSIISelLowering.h"
+#include "TGSIFrameLowering.h"
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 #include <string>
 
@@ -24,14 +28,28 @@ namespace llvm {
    class StringRef;
 
    class TGSISubtarget : public TGSIGenSubtargetInfo {
+      TGSIInstrInfo InstrInfo;
+      TGSITargetLowering TLInfo;
+      SelectionDAGTargetInfo TSInfo;
+      TGSIFrameLowering FrameLowering;
    public:
-      TGSISubtarget(const std::string &TT, const std::string &CPU,
-                    const std::string &FS);
+      TGSISubtarget(const Triple &TT, const std::string &CPU,
+                    const std::string &FS, TargetMachine &TM);
 
       void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
-      std::string getDataLayout() const {
-         return std::string("E-p:32:32-i64:64:64-f64:64:64-f128:128:128-n32");
+      const TGSIInstrInfo *getInstrInfo() const override { return &InstrInfo; }
+      const TargetFrameLowering *getFrameLowering() const override {
+         return &FrameLowering;
+      }
+      const TGSIRegisterInfo *getRegisterInfo() const override {
+         return &InstrInfo.getRegisterInfo();
+      }
+      const TGSITargetLowering *getTargetLowering() const override {
+         return &TLInfo;
+      }
+      const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
+         return &TSInfo;
       }
    };
 
diff --git a/lib/Target/TGSI/TGSITargetMachine.cpp b/lib/Target/TGSI/TGSITargetMachine.cpp
index 0f562ff7946..40e5c0e34d0 100644
--- a/lib/Target/TGSI/TGSITargetMachine.cpp
+++ b/lib/Target/TGSI/TGSITargetMachine.cpp
@@ -14,7 +14,9 @@
 #include "TGSI.h"
 #include "TGSITargetMachine.h"
 #include "llvm/CodeGen/Passes.h"
-#include "llvm/PassManager.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/PassManager.h"
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
@@ -36,18 +38,25 @@ extern "C" void LLVMInitializeTGSITarget() {
    RegisterTargetMachine<TGSITargetMachine> X(TheTGSITarget);
 }
 
-TGSITargetMachine::TGSITargetMachine(const Target &T, StringRef TT,
+static std::string computeDataLayout(const Triple &TT, StringRef CPU,
+                                     const TargetOptions &Options) {
+   return std::string("E-p:32:32-i64:64:64-f32:32:32-n32");
+}
+
+TGSITargetMachine::TGSITargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      const TargetOptions &Options,
-                                     Reloc::Model RM, CodeModel::Model CM,
+                                     Optional<llvm::Reloc::Model> RM,
+                                     CodeModel::Model CM,
                                      CodeGenOpt::Level OL)
-   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
-     Subtarget(TT, CPU, FS),
-     dl(Subtarget.getDataLayout()),
-     InstrInfo(Subtarget),
-     TLInfo(*this), TSInfo(*this),
-     FrameLowering(Subtarget) {
-     }
+   // TGSI does not support linking (only supports building a single file)
+   // So we always use Reloc::Static
+   : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options),
+                       TT, CPU, FS, Options, Reloc::Static, CM, OL),
+     TLOF(make_unique<TargetLoweringObjectFileELF>()),
+     Subtarget(TT, CPU, FS, *this) {
+   initAsmInfo();
+}
 
 TargetPassConfig *TGSITargetMachine::createPassConfig(PassManagerBase &PM) {
    return new TGSIPassConfig(this, PM);
diff --git a/lib/Target/TGSI/TGSITargetMachine.h b/lib/Target/TGSI/TGSITargetMachine.h
index 3c56cc29645..e9ab038f82c 100644
--- a/lib/Target/TGSI/TGSITargetMachine.h
+++ b/lib/Target/TGSI/TGSITargetMachine.h
@@ -14,47 +14,30 @@
 #ifndef TGSI_TARGET_MACHINE_H
 #define TGSI_TARGET_MACHINE_H
 
-#include "TGSIInstrInfo.h"
-#include "TGSIISelLowering.h"
-#include "TGSIFrameLowering.h"
-#include "TGSISelectionDAGInfo.h"
 #include "TGSISubtarget.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetFrameLowering.h"
 
 namespace llvm {
    class TGSITargetMachine : public LLVMTargetMachine {
+      std::unique_ptr<TargetLoweringObjectFile> TLOF;
       TGSISubtarget Subtarget;
-      const DataLayout dl;       // Calculates type size & alignment
-      TGSIInstrInfo InstrInfo;
-      TGSITargetLowering TLInfo;
-      TGSISelectionDAGInfo TSInfo;
-      TGSIFrameLowering FrameLowering;
    public:
-      TGSITargetMachine(const Target &T, StringRef TT,
+      TGSITargetMachine(const Target &T, const Triple &TT,
                         StringRef CPU, StringRef FS,
                         const TargetOptions &Options,
-                        Reloc::Model RM, CodeModel::Model CM,
+                        Optional<llvm::Reloc::Model> RM,
+                        CodeModel::Model CM,
                         CodeGenOpt::Level OL);
 
-      virtual const TGSIInstrInfo *getInstrInfo() const { return &InstrInfo; }
-      virtual const TargetFrameLowering  *getFrameLowering() const {
-         return &FrameLowering;
+      const TGSISubtarget *getSubtargetImpl(const Function &) const override {
+         return &Subtarget;
       }
-      virtual const TGSISubtarget   *getSubtargetImpl() const{ return &Subtarget; }
-      virtual const TargetRegisterInfo *getRegisterInfo() const {
-         return &InstrInfo.getRegisterInfo();
-      }
-      virtual const TGSITargetLowering* getTargetLowering() const {
-         return &TLInfo;
-      }
-      virtual const TGSISelectionDAGInfo* getSelectionDAGInfo() const {
-         return &TSInfo;
-      }
-      virtual const DataLayout *getDataLayout() const { return &dl; }
 
-      virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
+      TargetPassConfig *createPassConfig(PassManagerBase &PM);
+      TargetLoweringObjectFile *getObjFileLowering() const override {
+         return TLOF.get();
+      }
    };
 
 }