diff options
| author | Francisco Jerez <currojerez@riseup.net> | 2013-04-22 00:13:12 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2016-06-27 08:33:30 +0200 |
| commit | a269b42a3afc9ba1d655e799b1d2ef88b0285d75 (patch) | |
| tree | ce590ff35a4b520b620962368ae17e2d188cd8ec | |
| parent | 00fd9cb07c2bd0b892fd51c1707bbcf0e03c4db8 (diff) | |
TGSI back-end: Initial import.
39 files changed, 2587 insertions, 1 deletions
diff --git a/CMakeLists.txt b/CMakeLists.txt index a83d47761a4..0641aed82ad 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -230,6 +230,7 @@ set(LLVM_ALL_TARGETS PowerPC Sparc SystemZ + TGSI X86 XCore ) diff --git a/include/llvm/ADT/Triple.h b/include/llvm/ADT/Triple.h index 9154abd6eb3..bbb8e2be358 100644 --- a/include/llvm/ADT/Triple.h +++ b/include/llvm/ADT/Triple.h @@ -89,7 +89,8 @@ public: lanai, // Lanai: Lanai 32-bit wasm32, // WebAssembly with 32-bit pointers wasm64, // WebAssembly with 64-bit pointers - LastArchType = wasm64 + tgsi, // TGSI: Mesa-3D IR + LastArchType = tgsi }; enum SubArchType { NoSubArch, diff --git a/lib/Support/Triple.cpp b/lib/Support/Triple.cpp index 86c548f5612..1abb1fdf22d 100644 --- a/lib/Support/Triple.cpp +++ b/lib/Support/Triple.cpp @@ -62,6 +62,7 @@ const char *Triple::getArchTypeName(ArchType Kind) { case kalimba: return "kalimba"; case lanai: return "lanai"; case shave: return "shave"; + case tgsi: return "tgsi"; case wasm32: return "wasm32"; case wasm64: return "wasm64"; } @@ -129,6 +130,7 @@ const char *Triple::getArchTypePrefix(ArchType Kind) { case kalimba: return "kalimba"; case lanai: return "lanai"; case shave: return "shave"; + case tgsi: return "tgsi"; case wasm32: case wasm64: return "wasm"; } @@ -278,6 +280,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) { .Case("kalimba", kalimba) .Case("lanai", lanai) .Case("shave", shave) + .Case("tgsi", tgsi) .Case("wasm32", wasm32) .Case("wasm64", wasm64) .Default(UnknownArch); @@ -387,6 +390,7 @@ static Triple::ArchType parseArch(StringRef ArchName) { .StartsWith("kalimba", Triple::kalimba) .Case("lanai", Triple::lanai) .Case("shave", Triple::shave) + .Case("tgsi", Triple::tgsi) .Case("wasm32", Triple::wasm32) .Case("wasm64", Triple::wasm64) .Default(Triple::UnknownArch); @@ -1134,6 +1138,7 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) { case llvm::Triple::kalimba: case llvm::Triple::lanai: case llvm::Triple::shave: + case llvm::Triple::tgsi: case llvm::Triple::wasm32: return 32; @@ -1208,6 +1213,7 @@ Triple Triple::get32BitArchVariant() const { case Triple::xcore: case Triple::lanai: case Triple::shave: + case Triple::tgsi: case Triple::wasm32: // Already 32-bit. break; @@ -1243,6 +1249,7 @@ Triple Triple::get64BitArchVariant() const { case Triple::xcore: case Triple::sparcel: case Triple::shave: + case Triple::tgsi: T.setArch(UnknownArch); break; diff --git a/lib/Target/LLVMBuild.txt b/lib/Target/LLVMBuild.txt index 43621629dd2..c8111fa19f1 100644 --- a/lib/Target/LLVMBuild.txt +++ b/lib/Target/LLVMBuild.txt @@ -32,6 +32,7 @@ subdirectories = PowerPC Sparc SystemZ + TGSI WebAssembly X86 XCore diff --git a/lib/Target/TGSI/CMakeLists.txt b/lib/Target/TGSI/CMakeLists.txt new file mode 100644 index 00000000000..4882668a5b5 --- /dev/null +++ b/lib/Target/TGSI/CMakeLists.txt @@ -0,0 +1,26 @@ +set(LLVM_TARGET_DEFINITIONS TGSI.td) + +tablegen(LLVM TGSIGenRegisterInfo.inc -gen-register-info) +tablegen(LLVM TGSIGenInstrInfo.inc -gen-instr-info) +tablegen(LLVM TGSIGenAsmWriter.inc -gen-asm-writer) +tablegen(LLVM TGSIGenDAGISel.inc -gen-dag-isel) +tablegen(LLVM TGSIGenSubtargetInfo.inc -gen-subtarget) +tablegen(LLVM TGSIGenCallingConv.inc -gen-callingconv) +add_public_tablegen_target(TGSICommonTableGen) + +add_llvm_target(TGSICodeGen + TGSIAsmPrinter.cpp + TGSIInstrInfo.cpp + TGSIISelDAGToDAG.cpp + TGSIISelLowering.cpp + TGSIFrameLowering.cpp + TGSISubtarget.cpp + TGSITargetMachine.cpp + TGSISelectionDAGInfo.cpp + TGSIRegisterInfo.cpp + ) + +add_dependencies(LLVMTGSICodeGen intrinsics_gen) + +add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/lib/Target/TGSI/LLVMBuild.txt b/lib/Target/TGSI/LLVMBuild.txt new file mode 100644 index 00000000000..63a56132437 --- /dev/null +++ b/lib/Target/TGSI/LLVMBuild.txt @@ -0,0 +1,31 @@ +;===- ./lib/Target/TGSI/LLVMBuild.txt -------------------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[common] +subdirectories = MCTargetDesc TargetInfo + +[component_0] +type = TargetGroup +name = TGSI +parent = Target + +[component_1] +type = Library +name = TGSICodeGen +parent = TGSI +required_libraries = AsmPrinter CodeGen Core MC SelectionDAG Support Target TGSIDesc TGSIInfo +add_to_library_groups = TGSI diff --git a/lib/Target/TGSI/MCTargetDesc/CMakeLists.txt b/lib/Target/TGSI/MCTargetDesc/CMakeLists.txt new file mode 100644 index 00000000000..5ec827effe1 --- /dev/null +++ b/lib/Target/TGSI/MCTargetDesc/CMakeLists.txt @@ -0,0 +1,8 @@ +add_llvm_library(LLVMTGSIDesc + TGSIMCTargetDesc.cpp + TGSIMCInstPrinter.cpp + ) + +add_dependencies(LLVMTGSIDesc LLVMTGSIInfo) + +add_dependencies(LLVMTGSIDesc TGSICommonTableGen) diff --git a/lib/Target/TGSI/MCTargetDesc/LLVMBuild.txt b/lib/Target/TGSI/MCTargetDesc/LLVMBuild.txt new file mode 100644 index 00000000000..daf800ec781 --- /dev/null +++ b/lib/Target/TGSI/MCTargetDesc/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/TGSI/MCTargetDesc/LLVMBuild.txt ------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = TGSIDesc +parent = TGSI +required_libraries = MC TGSIInfo +add_to_library_groups = TGSI diff --git a/lib/Target/TGSI/MCTargetDesc/Makefile b/lib/Target/TGSI/MCTargetDesc/Makefile new file mode 100644 index 00000000000..df54382ac3a --- /dev/null +++ b/lib/Target/TGSI/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/TGSI/TargetDesc/Makefile ----------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMTGSIDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp b/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp new file mode 100644 index 00000000000..ed8dd5eea46 --- /dev/null +++ b/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp @@ -0,0 +1,78 @@ +//===-- TGSIMCInstPrinter.cpp - Convert TGSI MCInst to assembly syntax ----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an TGSI MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/TGSIMCTargetDesc.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +namespace { + class TGSIMCInstPrinter : public MCInstPrinter { + public: + TGSIMCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii, + const MCRegisterInfo &mri) + : MCInstPrinter(mai, mii, mri) {} + + virtual void printInst(const MCInst *mi, raw_ostream &os, + StringRef annot); + virtual void printRegName(raw_ostream &os, unsigned reg) const; + + // Autogenerated by tblgen. + void printInstruction(const MCInst *MI, raw_ostream &O); + static const char *getInstructionName(unsigned Opcode); + static const char *getRegisterName(unsigned RegNo); + + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + }; +} + +#include "TGSIGenAsmWriter.inc" + +void TGSIMCInstPrinter::printInst(const MCInst *mi, raw_ostream &os, + StringRef annot) { + printInstruction(mi, os); + printAnnotation(os, annot); +} + +void TGSIMCInstPrinter::printRegName(raw_ostream &os, unsigned reg) const { + os << getRegisterName(reg); +} + +void TGSIMCInstPrinter::printOperand(const MCInst *mi, unsigned op_idx, + raw_ostream &os) { + const MCOperand &op = mi->getOperand(op_idx); + + if (op.isReg()) + os << getRegisterName(op.getReg()); + else if (op.isImm()) + os << op.getImm(); + else if (op.isFPImm()) + os << op.getFPImm(); + else if (op.isExpr()) + os << *op.getExpr(); + else + assert(0); +} + +MCInstPrinter *llvm::createTGSIMCInstPrinter(const Target &t, + unsigned SyntaxVariant, + const MCAsmInfo &mai, + const MCInstrInfo &mii, + const MCRegisterInfo &mri, + const MCSubtargetInfo &sti) { + return new TGSIMCInstPrinter(mai, mii, mri); +} + diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp b/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp new file mode 100644 index 00000000000..c42e9fc68ce --- /dev/null +++ b/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp @@ -0,0 +1,71 @@ +//===-- TGSIMCTargetDesc.cpp - TGSI Target Descriptions --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides TGSI specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "TGSIMCTargetDesc.h" +#include "llvm/MC/MCCodeGenInfo.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/Support/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "TGSIGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "TGSIGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "TGSIGenRegisterInfo.inc" + +using namespace llvm; + +namespace { + struct TGSIMCAsmInfo : public MCAsmInfo { + explicit TGSIMCAsmInfo(const Target &T, StringRef TT) { + IsLittleEndian = true; + HasDotTypeDotSizeDirective = false; + } + }; +} + +static MCInstrInfo *createTGSIMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitTGSIMCInstrInfo(X); + return X; +} + +static MCRegisterInfo *createTGSIMCRegisterInfo(StringRef TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitTGSIMCRegisterInfo(X, TGSI::ADDR0); + return X; +} + +static MCSubtargetInfo *createTGSIMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitTGSIMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeTGSITargetMC() { + RegisterMCAsmInfo<TGSIMCAsmInfo> regMCAsmInfo(TheTGSITarget); + + TargetRegistry::RegisterMCInstrInfo(TheTGSITarget, createTGSIMCInstrInfo); + TargetRegistry::RegisterMCRegInfo(TheTGSITarget, createTGSIMCRegisterInfo); + TargetRegistry::RegisterMCSubtargetInfo(TheTGSITarget, + createTGSIMCSubtargetInfo); + TargetRegistry::RegisterMCInstPrinter(TheTGSITarget, + createTGSIMCInstPrinter); +} diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.h b/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.h new file mode 100644 index 00000000000..cd2e2d25d8c --- /dev/null +++ b/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.h @@ -0,0 +1,62 @@ +//===-- TGSIMCTargetDesc.h - TGSI Target Descriptions ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides TGSI specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef TGSI_MC_TARGET_DESC_H +#define TGSI_MC_TARGET_DESC_H + +namespace llvm { + class Target; + class MCStreamer; + class StringRef; + class MCContext; + class MCAsmBackend; + class raw_ostream; + class MCCodeEmitter; + class MCInstPrinter; + class MCAsmInfo; + class MCInstrInfo; + class MCRegisterInfo; + class MCSubtargetInfo; + + extern Target TheTGSITarget; + + MCStreamer *createTGSIObjStreamer(const Target &T, StringRef TT, + MCContext &Ctx, MCAsmBackend &MAB, + raw_ostream &OS, + MCCodeEmitter *Emitter, + bool RelaxAll, + bool NoExecStack); + + MCInstPrinter *createTGSIMCInstPrinter(const Target &t, + unsigned SyntaxVariant, + const MCAsmInfo &mai, + const MCInstrInfo &mii, + const MCRegisterInfo &mri, + const MCSubtargetInfo &sti); +} + +// Defines symbolic names for TGSI registers. This defines a mapping from +// register name to register number. +// +#define GET_REGINFO_ENUM +#include "TGSIGenRegisterInfo.inc" + +// Defines symbolic names for the TGSI instructions. +// +#define GET_INSTRINFO_ENUM +#include "TGSIGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "TGSIGenSubtargetInfo.inc" + +#endif diff --git a/lib/Target/TGSI/Makefile b/lib/Target/TGSI/Makefile new file mode 100644 index 00000000000..da1e08cd3db --- /dev/null +++ b/lib/Target/TGSI/Makefile @@ -0,0 +1,22 @@ +##===- lib/Target/TGSI/Makefile ---------------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../.. +LIBRARYNAME = LLVMTGSICodeGen +TARGET = TGSI + +# Make sure that tblgen is run, first thing. +BUILT_SOURCES = TGSIGenRegisterInfo.inc TGSIGenInstrInfo.inc \ + TGSIGenAsmWriter.inc TGSIGenDAGISel.inc \ + TGSIGenSubtargetInfo.inc TGSIGenCallingConv.inc + +DIRS = TargetInfo MCTargetDesc + +include $(LEVEL)/Makefile.common + diff --git a/lib/Target/TGSI/TGSI.h b/lib/Target/TGSI/TGSI.h new file mode 100644 index 00000000000..f4d75869711 --- /dev/null +++ b/lib/Target/TGSI/TGSI.h @@ -0,0 +1,64 @@ +//===-- TGSI.h - Top-level interface for TGSI representation --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the entry points for global functions defined in the LLVM +// TGSI back-end. +// +//===----------------------------------------------------------------------===// + +#ifndef TGSI_H +#define TGSI_H + +#include "MCTargetDesc/TGSIMCTargetDesc.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/Module.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetMachine.h" +#include <cassert> + +namespace llvm { + class FunctionPass; + class TGSITargetMachine; + class TargetLoweringObjectFile; + + FunctionPass *createTGSIISelDag(TGSITargetMachine &tm); + FunctionPass *createTGSIBranchConvPass(const TGSITargetMachine &tm); + + namespace tgsi { + enum AddressSpace { + // Enums corresponding to OpenCL address spaces + PRIVATE = 0, + GLOBAL = 1, + LOCAL = 2, + CONSTANT = 3, + // Special address space the arguments of a __kernel function are stored in + INPUT = 4 + }; + } + + namespace { + inline bool isKernelFunction(const Function *f) { + NamedMDNode *md = f->getParent()->getNamedMetadata("opencl.kernels"); + + if (md) { + for (unsigned i = 0; i < md->getNumOperands(); ++i) { + Value *v = md->getOperand(i)->getOperand(0); + + assert(v && isa<Function>(v)); + + if (f == static_cast<Function *>(v)) + return true; + } + } + + return false; + } + } +} +#endif diff --git a/lib/Target/TGSI/TGSI.td b/lib/Target/TGSI/TGSI.td new file mode 100644 index 00000000000..2b6493c9ed5 --- /dev/null +++ b/lib/Target/TGSI/TGSI.td @@ -0,0 +1,44 @@ +//===- TGSI.td - Describe the TGSI Target Machine --------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Target-independent interfaces which we are implementing +//===----------------------------------------------------------------------===// + +include "llvm/Target/Target.td" + +//===----------------------------------------------------------------------===// +// Register File, Calling Conv, Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "TGSIRegisterInfo.td" +include "TGSICallingConv.td" +include "TGSIInstrInfo.td" + +def TGSIInstrInfo : InstrInfo; + +//===----------------------------------------------------------------------===// +// TGSI processors supported. +//===----------------------------------------------------------------------===// + +def : Processor<"generic", NoItineraries, []>; + +//===----------------------------------------------------------------------===// +// Declare the target which we are implementing +//===----------------------------------------------------------------------===// + +def TGSIAsmWriter : AsmWriter { + string AsmWriterClassName = "MCInstPrinter"; + bit isMCAsmWriter = 1; +} + +def TGSI : Target { + let InstructionSet = TGSIInstrInfo; + let AssemblyWriters = [TGSIAsmWriter]; +} diff --git a/lib/Target/TGSI/TGSIAsmPrinter.cpp b/lib/Target/TGSI/TGSIAsmPrinter.cpp new file mode 100644 index 00000000000..4c3a9f763b5 --- /dev/null +++ b/lib/Target/TGSI/TGSIAsmPrinter.cpp @@ -0,0 +1,156 @@ +//===-- TGSIAsmPrinter.cpp - TGSI LLVM assembly writer ------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains a printer that converts from our internal representation +// of machine-dependent LLVM code to GAS-format TGSI assembly language. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "asm-printer" +#include "TGSI.h" +#include "TGSIInstrInfo.h" +#include "TGSITargetMachine.h" + +#include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/Target/Mangler.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +namespace { + class TGSIAsmPrinter : public AsmPrinter { + public: + explicit TGSIAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) {} + + virtual const char *getPassName() const { + return "TGSI Assembly Printer"; + } + + virtual void EmitInstruction(const MachineInstr *mi); + virtual void EmitFunctionBodyStart(); + virtual void EmitFunctionBodyEnd(); + + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); + void printInstruction(const MachineInstr *MI, raw_ostream &OS); + static const char *getRegisterName(unsigned RegNo); + + + }; +} + +static MCSymbol * +GetSymbolFromOperand(const MachineOperand &mo, AsmPrinter &ap) { + SmallString<128> name; + + if (mo.isGlobal()) { + const GlobalValue *gv = mo.getGlobal(); + + ap.Mang->getNameWithPrefix(name, gv, false); + + } else { + assert(mo.isSymbol() && "Isn't a symbol reference"); + name += ap.MAI->getGlobalPrefix(); + name += mo.getSymbolName(); + } + + return ap.OutContext.GetOrCreateSymbol(name.str()); +} + +static MCOperand +GetSymbolRef(const MachineOperand &mo, const MCSymbol *sym, + AsmPrinter &printer) { + MCContext &ctx = printer.OutContext; + const MCExpr *Expr = MCSymbolRefExpr::Create(sym, MCSymbolRefExpr::VK_None, + ctx); + + if (mo.getOffset()) + Expr = MCBinaryExpr::CreateAdd(Expr, + MCConstantExpr::Create(mo.getOffset(), ctx), + ctx); + + return MCOperand::CreateExpr(Expr); +} + +static void LowerMachineInstrToMCInst(const MachineInstr *mi, MCInst &mci, + AsmPrinter &ap) { + mci.setOpcode(mi->getOpcode()); + + for (unsigned i = 0; i != mi->getNumOperands(); ++i) { + const MachineOperand &mo = mi->getOperand(i); + MCOperand mco; + + switch (mo.getType()) { + case MachineOperand::MO_Register: + mco = MCOperand::CreateReg(mo.getReg()); + break; + case MachineOperand::MO_Immediate: + mco = MCOperand::CreateImm(mo.getImm()); + break; + case MachineOperand::MO_FPImmediate: + mco = MCOperand::CreateFPImm(mo.getFPImm()->getValueAPF() + .convertToFloat()); + break; + case MachineOperand::MO_MachineBasicBlock: + mco = MCOperand::CreateExpr(MCSymbolRefExpr::Create + (mo.getMBB()->getSymbol(), ap.OutContext)); + break; + case MachineOperand::MO_GlobalAddress: + case MachineOperand::MO_ExternalSymbol: + mco = GetSymbolRef(mo, GetSymbolFromOperand(mo, ap), ap); + break; + case MachineOperand::MO_ConstantPoolIndex: + mco = GetSymbolRef(mo, ap.GetCPISymbol(mo.getIndex()), ap); + break; + case MachineOperand::MO_BlockAddress: + mco = GetSymbolRef(mo, ap.GetBlockAddressSymbol(mo.getBlockAddress()), + ap); + break; + default: + assert(0); + break; + } + + mci.addOperand(mco); + } +} + +void TGSIAsmPrinter::EmitInstruction(const MachineInstr *mi) { + MCInst mci; + LowerMachineInstrToMCInst(mi, mci, *this); + OutStreamer.EmitInstruction(mci); +} + +void TGSIAsmPrinter::EmitFunctionBodyStart() { + MCInst mci; + + mci.setOpcode(TGSI::BGNSUB); + OutStreamer.EmitInstruction(mci); +} + +void TGSIAsmPrinter::EmitFunctionBodyEnd() { + MCInst mci; + mci.setOpcode(TGSI::ENDSUB); + OutStreamer.EmitInstruction(mci); +} + +extern "C" void LLVMInitializeTGSIAsmPrinter() { + RegisterAsmPrinter<TGSIAsmPrinter> X(TheTGSITarget); +} diff --git a/lib/Target/TGSI/TGSICallingConv.td b/lib/Target/TGSI/TGSICallingConv.td new file mode 100644 index 00000000000..0af9d8e1bc1 --- /dev/null +++ b/lib/Target/TGSI/TGSICallingConv.td @@ -0,0 +1,54 @@ +//===- TGSICallingConv.td - Calling Conventions TGSI -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This describes the calling conventions for the TGSI architectures. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Return Value Calling Conventions +//===----------------------------------------------------------------------===// + +// TGSI 32-bit C return-value convention. +def RetCC_TGSI : CallingConv<[ + CCIfType<[i32,f32], CCAssignToReg<[TEMP1x]>>, + CCIfType<[v4i32,v4f32], CCAssignToReg<[TEMP1]>> +]>; + +// TGSI 32-bit C Calling convention. +def FunCC_TGSI : CallingConv<[ + // i32 f32 arguments get passed in integer registers if there is space. + CCIfType<[i32, f32], CCAssignToReg<[TEMP1x, TEMP1y, TEMP1z, TEMP1w, + TEMP2x, TEMP2y, TEMP2z, TEMP2w, TEMP3x, TEMP3y, TEMP3z, TEMP3w, + TEMP4x, TEMP4y, TEMP4z, TEMP4w, TEMP5x, TEMP5y, TEMP5z, TEMP5w, + TEMP6x, TEMP6y, TEMP6z, TEMP6w, TEMP7x, TEMP7y, TEMP7z, TEMP7w, + TEMP8x, TEMP8y, TEMP8z, TEMP8w, TEMP9x, TEMP9y, TEMP9z, TEMP9w, + TEMP10x, TEMP10y, TEMP10z, TEMP10w, TEMP11x, TEMP11y, TEMP11z, TEMP11w, + TEMP12x, TEMP12y, TEMP12z, TEMP12w, TEMP13x, TEMP13y, TEMP13z, TEMP13w, + TEMP14x, TEMP14y, TEMP14z, TEMP14w, TEMP15x, TEMP15y, TEMP15z, TEMP15w, + TEMP16x, TEMP16y, TEMP16z, TEMP16w, TEMP17x, TEMP17y, TEMP17z, TEMP17w, + TEMP18x, TEMP18y, TEMP18z, TEMP18w, TEMP19x, TEMP19y, TEMP19z, TEMP19w, + TEMP20x, TEMP20y, TEMP20z, TEMP20w, TEMP21x, TEMP21y, TEMP21z, TEMP21w, + TEMP22x, TEMP22y, TEMP22z, TEMP22w, TEMP23x, TEMP23y, TEMP23z, TEMP23w, + TEMP24x, TEMP24y, TEMP24z, TEMP24w, TEMP25x, TEMP25y, TEMP25z, TEMP25w, + TEMP26x, TEMP26y, TEMP26z, TEMP26w, TEMP27x, TEMP27y, TEMP27z, TEMP27w, + TEMP28x, TEMP28y, TEMP28z, TEMP28w, TEMP29x, TEMP29y, TEMP29z, TEMP29w, + TEMP30x, TEMP30y, TEMP30z, TEMP30w, TEMP31x, TEMP31y, TEMP31z, TEMP31w]>>, + + CCIfType<[v4i32, v4f32], CCAssignToReg<[TEMP1, TEMP2, TEMP3, TEMP4, TEMP5, + TEMP6, TEMP7, TEMP8, TEMP9, TEMP10, TEMP11, TEMP12, TEMP13, TEMP14, + TEMP15, TEMP16, TEMP17, TEMP18, TEMP19, TEMP20, TEMP21, TEMP22, TEMP23, + TEMP24, TEMP25, TEMP26, TEMP27, TEMP28, TEMP29, TEMP30, TEMP31]>> +]>; + +def KernCC_TGSI : CallingConv<[ + // i32 f32 arguments get passed through the input space. + CCIfType<[i32, f32], CCAssignToStack<4, 4>>, + CCIfType<[v4i32, v4f32], CCAssignToStack<16, 16>> +]>; diff --git a/lib/Target/TGSI/TGSIFrameLowering.cpp b/lib/Target/TGSI/TGSIFrameLowering.cpp new file mode 100644 index 00000000000..b94bb1cb8d3 --- /dev/null +++ b/lib/Target/TGSI/TGSIFrameLowering.cpp @@ -0,0 +1,55 @@ +//====- TGSIFrameLowering.cpp - TGSI Frame Information -------*- C++ -*-====// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the TGSI implementation of TargetFrameLowering class. +// +//===----------------------------------------------------------------------===// + +#include "TGSIFrameLowering.h" +#include "TGSIInstrInfo.h" +#include "llvm/IR/Function.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Target/TargetOptions.h" +#include "llvm/Support/CommandLine.h" + +using namespace llvm; + +void TGSIFrameLowering::emitPrologue(MachineFunction &mf) const { + MachineBasicBlock &mbb = mf.front(); + MachineFrameInfo *mfi = mf.getFrameInfo(); + const TGSIInstrInfo &tii = + *static_cast<const TGSIInstrInfo*>(mf.getTarget().getInstrInfo()); + MachineBasicBlock::iterator mbbi = mbb.begin(); + DebugLoc dl; + + // Get the number of bytes to allocate from the FrameInfo + int frame_sz = mfi->getStackSize(); + + BuildMI(mbb, mbbi, dl, tii.get(TGSI::UADDs), TGSI::TEMP0x) + .addReg(TGSI::TEMP0x).addImm(frame_sz); +} + +void TGSIFrameLowering::emitEpilogue(MachineFunction &mf, + MachineBasicBlock &mbb) const { + MachineBasicBlock::iterator mbbi = mbb.getLastNonDebugInstr(); + MachineFrameInfo *mfi = mf.getFrameInfo(); + const TGSIInstrInfo &tii = + *static_cast<const TGSIInstrInfo*>(mf.getTarget().getInstrInfo()); + DebugLoc dl; + + // Get the number of bytes to allocate from the FrameInfo + int frame_sz = mfi->getStackSize(); + + BuildMI(mbb, mbbi, dl, tii.get(TGSI::UADDs), TGSI::TEMP0x) + .addReg(TGSI::TEMP0x).addImm(-frame_sz); +} diff --git a/lib/Target/TGSI/TGSIFrameLowering.h b/lib/Target/TGSI/TGSIFrameLowering.h new file mode 100644 index 00000000000..d376fb1985a --- /dev/null +++ b/lib/Target/TGSI/TGSIFrameLowering.h @@ -0,0 +1,38 @@ +//===- TGSIFrameLowering.h - Define frame lowering for TGSI --*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the TGSI implementation of TargetFrameLowering class. +// +//===----------------------------------------------------------------------===// + +#ifndef TGSI_FRAME_LOWERING_H +#define TGSI_FRAME_LOWERING_H + +#include "TGSI.h" +#include "TGSISubtarget.h" +#include "llvm/Target/TargetFrameLowering.h" + +namespace llvm { + class TGSISubtarget; + + class TGSIFrameLowering : public TargetFrameLowering { + const TGSISubtarget &STI; + public: + explicit TGSIFrameLowering(const TGSISubtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 16, 0), STI(sti) { + } + + void emitPrologue(MachineFunction &MF) const; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; + + bool hasFP(const MachineFunction &MF) const { return false; } + }; +} + +#endif diff --git a/lib/Target/TGSI/TGSIISelDAGToDAG.cpp b/lib/Target/TGSI/TGSIISelDAGToDAG.cpp new file mode 100644 index 00000000000..bf9908c5967 --- /dev/null +++ b/lib/Target/TGSI/TGSIISelDAGToDAG.cpp @@ -0,0 +1,126 @@ +//===-- TGSIISelDAGToDAG.cpp - A dag to dag inst selector for TGSI ------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines an instruction selector for the TGSI target. +// +//===----------------------------------------------------------------------===// + +#include "TGSITargetMachine.h" +#include "llvm/IR/Intrinsics.h" +#include "llvm/CodeGen/SelectionDAGISel.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +namespace { + class TGSIDAGToDAGISel : public SelectionDAGISel { + const TGSISubtarget &Subtarget; + TGSITargetMachine& TM; + public: + explicit TGSIDAGToDAGISel(TGSITargetMachine &tm) + : SelectionDAGISel(tm), + Subtarget(tm.getSubtarget<TGSISubtarget>()), + TM(tm) { + } + + SDNode *Select(SDNode *N); + + // Complex Pattern Selectors. + template<int addr_space> + bool SelectPtr(SDNode *p, SDValue &n, SDValue &v); + + template<bool any_ok> + bool SelectSrc(SDValue &n, SDValue &v); + + virtual const char *getPassName() const { + return "TGSI DAG->DAG Pattern Instruction Selection"; + } + + // Include the pieces autogenerated from the target description. +#include "TGSIGenDAGISel.inc" + }; +} + +SDNode *TGSIDAGToDAGISel::Select(SDNode *n) { + DebugLoc dl = n->getDebugLoc(); + + switch (n->getOpcode()) { + case ISD::FrameIndex: { + int fi = cast<FrameIndexSDNode>(n)->getIndex(); + SDValue tfi = CurDAG->getTargetFrameIndex(fi, MVT::i32); + + return tfi.getNode(); + } + case ISD::GlobalAddress: { + const GlobalValue *gv = cast<GlobalAddressSDNode>(n)->getGlobal(); + SDValue tga = CurDAG->getTargetGlobalAddress(gv, dl, MVT::i32); + + return tga.getNode(); + } + } + + return SelectCode(n); +} + +FunctionPass *llvm::createTGSIISelDag(TGSITargetMachine &TM) { + return new TGSIDAGToDAGISel(TM); +} + +template<int addr_space> +bool TGSIDAGToDAGISel::SelectPtr(SDNode *p, SDValue &n, SDValue &r) { + const Value *v; + const PointerType *ptr; + + if (ConstantPoolSDNode *c = dyn_cast<ConstantPoolSDNode>(n)) { + if (addr_space == tgsi::CONSTANT) { + r = CurDAG->getTargetConstantPool(c->getConstVal(), MVT::i32, + c->getAlignment()); + return true; + } + + } else { + if ((v = cast<MemSDNode>(p)->getSrcValue()) && + (ptr = dyn_cast<PointerType>(v->getType())) && + ptr->getAddressSpace() == addr_space) { + r = n; + return true; + } + } + + return false; +} + +template<bool any_ok> +bool TGSIDAGToDAGISel::SelectSrc(SDValue &v, SDValue &r) { + SDNode *n = v.getNode(); + DebugLoc dl = n->getDebugLoc(); + + if (ConstantSDNode *c = dyn_cast<ConstantSDNode>(n)) { + r = CurDAG->getTargetConstant(*c->getConstantIntValue(), + n->getValueType(0)); + return true; + + } else if (ConstantFPSDNode *c = dyn_cast<ConstantFPSDNode>(n)) { + r = CurDAG->getTargetConstantFP(*c->getConstantFPValue(), + n->getValueType(0)); + return true; + + } else if (GlobalAddressSDNode *ga = dyn_cast<GlobalAddressSDNode>(n)) { + r = CurDAG->getTargetGlobalAddress(ga->getGlobal(), dl, MVT::i32); + return true; + + } else if (any_ok) { + r = v; + return true; + } + + return false; +} diff --git a/lib/Target/TGSI/TGSIISelLowering.cpp b/lib/Target/TGSI/TGSIISelLowering.cpp new file mode 100644 index 00000000000..adae48452d5 --- /dev/null +++ b/lib/Target/TGSI/TGSIISelLowering.cpp @@ -0,0 +1,244 @@ +//===-- TGSIISelLowering.cpp - TGSI DAG Lowering Implementation ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the interfaces that TGSI uses to lower LLVM code into a +// selection DAG. +// +//===----------------------------------------------------------------------===// + +#include "TGSIISelLowering.h" +#include "TGSITargetMachine.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/Module.h" +#include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/Support/ManagedStatic.h" +using namespace llvm; + + +//===----------------------------------------------------------------------===// +// Calling Convention Implementation +//===----------------------------------------------------------------------===// + +#include "TGSIGenCallingConv.inc" + +SDValue +TGSITargetLowering::LowerReturn(SDValue Chain, + CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + DebugLoc dl, SelectionDAG &DAG) const { + SDValue Flag; + + // CCValAssign - represent the assignment of the return value to locations. + SmallVector<CCValAssign, 16> RVLocs; + + // CCState - Info about the registers and stack slot. + CCState ccinfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); + + ccinfo.AnalyzeReturn(Outs, RetCC_TGSI); + + for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { + CCValAssign& VA = RVLocs[i]; + + assert(VA.isRegLoc() && "CCValAssign must be RegLoc"); + + unsigned Reg = VA.getLocReg(); + + Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag); + + // Guarantee that all emitted copies are stuck together. + Flag = Chain.getValue(1); + } + + if (Flag.getNode()) + return DAG.getNode(TGSIISD::RET, dl, MVT::Other, Chain, Flag); + else + return DAG.getNode(TGSIISD::RET, dl, MVT::Other, Chain); +} + +SDValue +TGSITargetLowering::LowerFormalArguments(SDValue Chain, + CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, + DebugLoc dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) const { + MachineFunction &mf = DAG.getMachineFunction(); + MachineRegisterInfo ®info = mf.getRegInfo(); + + // Assign locations to all of the incoming arguments. + SmallVector<CCValAssign, 16> ArgLocs; + CCState ccinfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); + CCAssignFn *ccfn = (isKernelFunction(mf.getFunction()) ? KernCC_TGSI : FunCC_TGSI); + + ccinfo.AnalyzeFormalArguments(Ins, ccfn); + + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &va = ArgLocs[i]; + MVT vt = va.getValVT(); + SDValue arg; + + if (va.isRegLoc()) { + unsigned vreg = reginfo.createVirtualRegister(getRegClassFor(vt)); + + reginfo.addLiveIn(va.getLocReg(), vreg); + arg = DAG.getCopyFromReg(Chain, dl, vreg, vt); + + } else { + SDValue ptr = DAG.getConstant(va.getLocMemOffset(), MVT::i32); + + arg = DAG.getNode(TGSIISD::LOAD_INPUT, dl, vt, Chain, ptr); + } + + InVals.push_back(arg); + } + + return Chain; +} + +SDValue +TGSITargetLowering::LowerCall(SDValue Chain, SDValue Callee, + CallingConv::ID CallConv, bool isVarArg, + bool &isTailCall, + const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + const SmallVectorImpl<ISD::InputArg> &Ins, + DebugLoc dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) const { + SDValue InFlag; + // Analyze operands of the call, assigning locations to each operand. + SmallVector<CCValAssign, 16> ArgLocs; + CCState ccinfo(CallConv, isVarArg, DAG.getMachineFunction(), + DAG.getTarget(), ArgLocs, *DAG.getContext()); + ccinfo.AnalyzeCallOperands(Outs, FunCC_TGSI); + + // Walk the register assignments, inserting copies. + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + SDValue Arg = OutVals[i]; + + if (VA.getLocVT() == MVT::f32) + Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); + + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, InFlag); + InFlag = Chain.getValue(1); + } + + // Returns a chain & a flag for retval copy to use + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + SmallVector<SDValue, 8> Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + unsigned Reg = ArgLocs[i].getLocReg(); + + Ops.push_back(DAG.getRegister(Reg, ArgLocs[i].getLocVT())); + } + if (InFlag.getNode()) + Ops.push_back(InFlag); + + Chain = DAG.getNode(TGSIISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); + InFlag = Chain.getValue(1); + + // Assign locations to each value returned by this call. + SmallVector<CCValAssign, 16> RVLocs; + CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), + DAG.getTarget(), RVLocs, *DAG.getContext()); + + RVInfo.AnalyzeCallResult(Ins, RetCC_TGSI); + + // Copy all of the result registers out of their specified physreg. + for (unsigned i = 0; i != RVLocs.size(); ++i) { + unsigned Reg = RVLocs[i].getLocReg(); + + Chain = DAG.getCopyFromReg(Chain, dl, Reg, + RVLocs[i].getValVT(), InFlag).getValue(1); + InFlag = Chain.getValue(2); + InVals.push_back(Chain.getValue(0)); + } + + isTailCall = false; + return Chain; +} + +//===----------------------------------------------------------------------===// +// TargetLowering Implementation +//===----------------------------------------------------------------------===// + +TGSITargetLowering::TGSITargetLowering(TargetMachine &TM) + : TargetLowering(TM, new TargetLoweringObjectFileELF()) { + + // Set up the register classes. + addRegisterClass(MVT::i32, &TGSI::IRegsRegClass); + addRegisterClass(MVT::v4i32, &TGSI::IVRegsRegClass); + addRegisterClass(MVT::f32, &TGSI::FRegsRegClass); + addRegisterClass(MVT::v4f32, &TGSI::FVRegsRegClass); + + setStackPointerRegisterToSaveRestore(TGSI::TEMP0); + computeRegisterProperties(); + + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + setOperationAction(ISD::SDIVREM, MVT::i32, Expand); + setOperationAction(ISD::UDIVREM, MVT::i32, Expand); + setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + setOperationAction(ISD::BR_CC, MVT::i32, Expand); + setOperationAction(ISD::BR_CC, MVT::f32, Expand); + setOperationAction(ISD::BR_CC, MVT::f64, Expand); + setOperationAction(ISD::BR_CC, MVT::Other, Expand); + setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); + setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); + + setOperationAction(ISD::ConstantFP, MVT::f32, Legal); + setOperationAction(ISD::FGETSIGN, MVT::f32, Legal); + setOperationAction(ISD::FLOG2, MVT::f32, Legal); + setOperationAction(ISD::FEXP2, MVT::f32, Legal); + + setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Expand); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Expand); +} + +const char *TGSITargetLowering::getTargetNodeName(unsigned Opcode) const { + switch (Opcode) { + case TGSIISD::LOAD_INPUT: + return "TGSIISD::LOAD_INPUT"; + case TGSIISD::CALL: + return "TGSIISD::CALL"; + case TGSIISD::RET: + return "TGSIISD::RET"; + default: + llvm_unreachable("Invalid opcode"); + } +} + +SDValue TGSITargetLowering:: +LowerOperation(SDValue op, SelectionDAG &dag) const { + switch (op.getOpcode()) { + default: + llvm_unreachable("Should not custom lower this!"); + }; +} diff --git a/lib/Target/TGSI/TGSIISelLowering.h b/lib/Target/TGSI/TGSIISelLowering.h new file mode 100644 index 00000000000..588125c5f5e --- /dev/null +++ b/lib/Target/TGSI/TGSIISelLowering.h @@ -0,0 +1,65 @@ +//===-- TGSIISelLowering.h - TGSI DAG Lowering Interface ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the interfaces that TGSI uses to lower LLVM code into a +// selection DAG. +// +//===----------------------------------------------------------------------===// + +#ifndef TGSI_ISEL_LOWERING_H +#define TGSI_ISEL_LOWERING_H + +#include "llvm/Target/TargetLowering.h" +#include "TGSI.h" + +namespace llvm { + namespace TGSIISD { + enum { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + LOAD_INPUT, + CALL, + RET + }; + } + + class TGSITargetLowering : public TargetLowering { + public: + TGSITargetLowering(TargetMachine &TM); + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; + + virtual const char *getTargetNodeName(unsigned Opcode) const; + + virtual SDValue + LowerFormalArguments(SDValue Chain, + CallingConv::ID CallConv, + bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, + DebugLoc dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) const; + + virtual SDValue + LowerCall(SDValue Chain, SDValue Callee, + CallingConv::ID CallConv, bool isVarArg, + bool &isTailCall, + const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + const SmallVectorImpl<ISD::InputArg> &Ins, + DebugLoc dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) const; + + virtual SDValue + LowerReturn(SDValue Chain, + CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + DebugLoc dl, SelectionDAG &DAG) const; + }; +} + +#endif diff --git a/lib/Target/TGSI/TGSIInstrFormats.td b/lib/Target/TGSI/TGSIInstrFormats.td new file mode 100644 index 00000000000..b842a3a38e8 --- /dev/null +++ b/lib/Target/TGSI/TGSIInstrFormats.td @@ -0,0 +1,67 @@ +//===- TGSIInstrFormats.td - TGSI Instruction Formats ----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +class tgsi_class<bits<8> instr, dag outs, dag ins, + string asmstr, list<dag> pattern> : Instruction { + let Namespace = "TGSI"; + let OutOperandList = outs; + let InOperandList = ins; + let AsmString = asmstr; + let Pattern = pattern; + + bits<1> vector = 0; + bits<1> negate_op0 = 0; + bits<1> negate_op1 = 0; + bits<1> dst_resource = 0; + bits<1> src_resource = 0; + bits<3> addr_space = 0; + + let TSFlags{7-0} = instr; + let TSFlags{8} = negate_op0; + let TSFlags{9} = negate_op1; + let TSFlags{10} = dst_resource; + let TSFlags{11} = src_resource; + let TSFlags{14-12} = addr_space; +} + +class tgsi_negate_op0_class { + bits<1> negate_op0 = 1; +} + +class tgsi_negate_op1_class { + bits<1> negate_op1 = 1; +} + +class tgsi_dst_resource_class { + bits<1> dst_resource = 1; +} + +class tgsi_src_resource_class { + bits<1> src_resource = 1; +} + +class tgsi_addr_space_private_class { + bits<3> addr_space = 0; +} + +class tgsi_addr_space_global_class { + bits<3> addr_space = 1; +} + +class tgsi_addr_space_local_class { + bits<3> addr_space = 2; +} + +class tgsi_addr_space_constant_class { + bits<3> addr_space = 3; +} + +class tgsi_addr_space_input_class { + bits<3> addr_space = 4; +} diff --git a/lib/Target/TGSI/TGSIInstrInfo.cpp b/lib/Target/TGSI/TGSIInstrInfo.cpp new file mode 100644 index 00000000000..525a760b414 --- /dev/null +++ b/lib/Target/TGSI/TGSIInstrInfo.cpp @@ -0,0 +1,177 @@ +//===- TGSIInstrInfo.cpp - TGSI Instruction Information -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the TGSI implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#include "TGSIInstrInfo.h" +#include "TGSI.h" +#include "TGSISubtarget.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" + +#define GET_INSTRINFO_CTOR +#include "TGSIGenInstrInfo.inc" + +using namespace llvm; + +TGSIInstrInfo::TGSIInstrInfo(TGSISubtarget &ST) + : RI(ST, *this), Subtarget(ST) { +} + +unsigned TGSIInstrInfo::isLoadFromStackSlot(const MachineInstr *mi, + int &fi) const { + if ((mi->getOpcode() == TGSI::LDpis || mi->getOpcode() == TGSI::LDpfs || + mi->getOpcode() == TGSI::LDpiv || mi->getOpcode() == TGSI::LDpfv) && + mi->getOperand(1).isFI()) { + fi = mi->getOperand(1).getIndex(); + return mi->getOperand(0).getReg(); + } + + return 0; +} + +unsigned TGSIInstrInfo::isStoreToStackSlot(const MachineInstr *mi, + int &fi) const { + if ((mi->getOpcode() == TGSI::STpis || mi->getOpcode() == TGSI::STpfs || + mi->getOpcode() == TGSI::STpiv || mi->getOpcode() == TGSI::STpfv) && + mi->getOperand(0).isFI()) { + assert(0); + fi = mi->getOperand(0).getIndex(); + return mi->getOperand(1).getReg(); + } + + return 0; +} + +bool TGSIInstrInfo::AnalyzeBranch(MachineBasicBlock &bb, + MachineBasicBlock *&tbb, + MachineBasicBlock *&fbb, + SmallVectorImpl<MachineOperand> &cond, + bool AllowModify) const { + for (MachineBasicBlock::iterator i = bb.getFirstTerminator(); + i != bb.end(); ++i) { + if (i->getOpcode() == TGSI::P_BRCOND) { + tbb = i->getOperand(1).getMBB(); + cond.clear(); + cond.push_back(i->getOperand(0)); + + } else if (i->getOpcode() == TGSI::BRA) { + MachineBasicBlock **pbb = tbb ? &fbb : &tbb; + + *pbb = i->getOperand(0).getMBB(); + return false; + + } else { + return true; + } + } + + return false; +} + +unsigned +TGSIInstrInfo::InsertBranch(MachineBasicBlock &bb, MachineBasicBlock *tbb, + MachineBasicBlock *fbb, + const SmallVectorImpl<MachineOperand> &cond, + DebugLoc dl) const { + int n = 0; + + if (cond.empty()) { + BuildMI(&bb, dl, get(TGSI::BRA)).addMBB(tbb); + n++; + + } else { + BuildMI(&bb, dl, get(TGSI::P_BRCOND)).addOperand(cond[0]).addMBB(tbb); + n++; + + if (fbb) { + BuildMI(&bb, dl, get(TGSI::BRA)).addMBB(fbb); + n++; + } + } + + return n; +} + +unsigned TGSIInstrInfo::RemoveBranch(MachineBasicBlock &bb) const { + int n = 0; + + while (!bb.empty()) { + MachineInstr& i = bb.back(); + + if (i.getOpcode() == TGSI::BRA || + i.getOpcode() == TGSI::P_BRCOND) { + i.eraseFromParent(); + n++; + + } else { + break; + } + } + + return n; +} + +void TGSIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, DebugLoc DL, + unsigned DestReg, unsigned SrcReg, + bool KillSrc) const { + if (TGSI::IRegsRegClass.contains(DestReg, SrcReg)) + BuildMI(MBB, I, DL, get(TGSI::MOVis), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + else if (TGSI::IVRegsRegClass.contains(DestReg, SrcReg)) + BuildMI(MBB, I, DL, get(TGSI::MOViv), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + else + assert(0); +} + +void TGSIInstrInfo:: +storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned SrcReg, bool isKill, int fi, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const { + DebugLoc dl = I->getDebugLoc(); + + if (RC == &TGSI::IRegsRegClass) + BuildMI(MBB, I, dl, get(TGSI::STpis)).addFrameIndex(fi).addReg(SrcReg); + else if (RC == &TGSI::IVRegsRegClass) + BuildMI(MBB, I, dl, get(TGSI::STpiv)).addFrameIndex(fi).addReg(SrcReg); + else if (RC == &TGSI::FRegsRegClass) + BuildMI(MBB, I, dl, get(TGSI::STpfs)).addFrameIndex(fi).addReg(SrcReg); + else if (RC == &TGSI::FVRegsRegClass) + BuildMI(MBB, I, dl, get(TGSI::STpfv)).addFrameIndex(fi).addReg(SrcReg); + else + llvm_unreachable("Can't store this register to stack slot"); +} + +void TGSIInstrInfo:: +loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned DestReg, int fi, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const { + DebugLoc dl = I->getDebugLoc(); + + if (RC == &TGSI::IRegsRegClass) + BuildMI(MBB, I, dl, get(TGSI::LDpis), DestReg).addFrameIndex(fi); + else if (RC == &TGSI::IVRegsRegClass) + BuildMI(MBB, I, dl, get(TGSI::LDpiv), DestReg).addFrameIndex(fi); + else if (RC == &TGSI::FRegsRegClass) + BuildMI(MBB, I, dl, get(TGSI::LDpfs), DestReg).addFrameIndex(fi); + else if (RC == &TGSI::FVRegsRegClass) + BuildMI(MBB, I, dl, get(TGSI::LDpfv), DestReg).addFrameIndex(fi); + else + llvm_unreachable("Can't load this register from stack slot"); +} diff --git a/lib/Target/TGSI/TGSIInstrInfo.h b/lib/Target/TGSI/TGSIInstrInfo.h new file mode 100644 index 00000000000..b7381b3c62e --- /dev/null +++ b/lib/Target/TGSI/TGSIInstrInfo.h @@ -0,0 +1,92 @@ +//===- TGSIInstrInfo.h - TGSI Instruction Information ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the TGSI implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef TGSI_INSTRUCTION_INFO_H +#define TGSI_INSTRUCTION_INFO_H + +#include "TGSI.h" +#include "TGSIRegisterInfo.h" +#include "llvm/Target/TargetInstrInfo.h" + +#define GET_INSTRINFO_HEADER +#include "TGSIGenInstrInfo.inc" + +namespace llvm { + namespace TGSIIF { + enum { + OPCODE = 0xff, + NEGATE_OP0 = 0x100, + NEGATE_OP1 = 0x200, + DST_RESOURCE = 0x400, + SRC_RESOURCE = 0x800, + ADDR_SPACE = 0x7000, + ADDR_SPACE_PRIVATE = tgsi::PRIVATE << 12, + ADDR_SPACE_GLOBAL = tgsi::GLOBAL << 12, + ADDR_SPACE_LOCAL = tgsi::LOCAL << 12, + ADDR_SPACE_CONSTANT = tgsi::CONSTANT << 12, + ADDR_SPACE_INPUT = tgsi::INPUT << 12 + }; + } + + class TGSIInstrInfo : public TGSIGenInstrInfo { + const TGSIRegisterInfo RI; + const TGSISubtarget& Subtarget; + public: + explicit TGSIInstrInfo(TGSISubtarget &ST); + + virtual const TGSIRegisterInfo &getRegisterInfo() const { + return RI; + } + + virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const; + + virtual unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const; + + + virtual bool AnalyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl<MachineOperand> &Cond, + bool AllowModify = false) const ; + + virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; + + virtual unsigned InsertBranch(MachineBasicBlock &MBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + const SmallVectorImpl<MachineOperand> &Cond, + DebugLoc DL) const; + + virtual void copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, DebugLoc DL, + unsigned DestReg, unsigned SrcReg, + bool KillSrc) const; + + virtual void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, bool isKill, + int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const; + + virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const; + }; +} + +#endif diff --git a/lib/Target/TGSI/TGSIInstrInfo.td b/lib/Target/TGSI/TGSIInstrInfo.td new file mode 100644 index 00000000000..685d9630554 --- /dev/null +++ b/lib/Target/TGSI/TGSIInstrInfo.td @@ -0,0 +1,367 @@ +//===- TGSIInstrInfo.td - Target Description for TGSI Target ------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the TGSI instructions in TableGen format. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction format superclass +//===----------------------------------------------------------------------===// + +include "TGSIInstrFormats.td" + +//===----------------------------------------------------------------------===// +// Instruction Pattern Stuff +//===----------------------------------------------------------------------===// + + +def load_input : SDNode<"TGSIISD::LOAD_INPUT", + SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>, + [SDNPHasChain]>; + +def call : SDNode<"TGSIISD::CALL", + SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, + SDNPVariadic]>; + +def ret : SDNode<"TGSIISD::RET", SDTNone, + [SDNPHasChain, SDNPOptInGlue]>; + +class pat_ptr<string space> : ComplexPattern<i32, 1, + !strconcat("SelectPtr<tgsi::", + !strconcat(space, ">")), + [imm], [SDNPWantParent]>; + +def private_ptr : pat_ptr<"PRIVATE">; +def global_ptr : pat_ptr<"GLOBAL">; +def local_ptr : pat_ptr<"LOCAL">; +def const_ptr : pat_ptr<"CONSTANT">; +def input_ptr : pat_ptr<"INPUT">; + +def i32_imm : ComplexPattern<i32, 1, "SelectSrc<false>", + [imm, globaladdr, tglobaladdr], []>; +def vi32_imm : ComplexPattern<v4i32, 1, "SelectSrc<false>", [imm], []>; +def f32_imm : ComplexPattern<f32, 1, "SelectSrc<false>", [fpimm], []>; +def vf32_imm : ComplexPattern<v4f32, 1, "SelectSrc<false>", [fpimm], []>; + +def i32_src : ComplexPattern<i32, 1, "SelectSrc<true>", + [imm, globaladdr, tglobaladdr], []>; +def vi32_src : ComplexPattern<v4i32, 1, "SelectSrc<true>", [imm], []>; +def f32_src : ComplexPattern<f32, 1, "SelectSrc<true>", [fpimm], []>; +def vf32_src : ComplexPattern<v4f32, 1, "SelectSrc<true>", [fpimm], []>; + +def brtarget : Operand<OtherVT>; +def calltarget : Operand<iPTR>; + +//===----------------------------------------------------------------------===// +// Instruction multiclass Templates +//===----------------------------------------------------------------------===// + +multiclass tgsi1p_i32_class<bits<8> instr, PatFrag op, string asmstr> { + def s: tgsi_class<instr, (outs IRegs:$d), (ins IRegs:$a), + !strconcat(asmstr, "s $d, $a"), + [(set IRegs:$d, (op i32_src:$a))]>; + + def v: tgsi_class<instr, (outs IVRegs:$d), (ins IVRegs:$a), + !strconcat(asmstr, "v $d, $a"), + [(set IVRegs:$d, (op vi32_src:$a))]>; +} + +multiclass tgsi1np_i32_class<bits<8> instr, string asmstr> { + def s: tgsi_class<instr, (outs IRegs:$d), (ins IRegs:$a), + !strconcat(asmstr, "s $d, $a"), []>; + + def v: tgsi_class<instr, (outs IVRegs:$d), (ins IVRegs:$a), + !strconcat(asmstr, "v $d, $a"), []>; +} + +multiclass tgsi2_i32_class<bits<8> instr, SDNode op, string asmstr> { + def s: tgsi_class<instr, (outs IRegs:$d), (ins IRegs:$a, IRegs:$b), + !strconcat(asmstr, "s $d, $a, $b"), + [(set IRegs:$d, (op i32_src:$a, i32_src:$b))]>; + + def v: tgsi_class<instr, (outs IVRegs:$d), (ins IVRegs:$a, IVRegs:$b), + !strconcat(asmstr, "v $d, $a, $b"), + [(set IVRegs:$d, (op vi32_src:$a, vi32_src:$b))]>; +} + +multiclass tgsi2p_i32_class<bits<8> instr, PatFrag op, string asmstr> { + def s: tgsi_class<instr, (outs IRegs:$d), (ins IRegs:$a, IRegs:$b), + !strconcat(asmstr, "s $d, $a, $b"), + [(set IRegs:$d, (op i32_src:$a, i32_src:$b))]>; + + def v: tgsi_class<instr, (outs IVRegs:$d), (ins IVRegs:$a, IVRegs:$b), + !strconcat(asmstr, "v $d, $a, $b"), + [(set IVRegs:$d, (op vi32_src:$a, vi32_src:$b))]>; +} + +multiclass tgsi3_i32_class<bits<8> instr, SDNode op, string asmstr> { + def s: tgsi_class<instr, (outs IRegs:$d), (ins IRegs:$a, IRegs:$b, IRegs:$c), + !strconcat(asmstr, "s $d, $a, $b, $c"), + [(set IRegs:$d, (op i32_src:$a, i32_src:$b, i32_src:$c))]>; + + def v: tgsi_class<instr, (outs IVRegs:$d), (ins IVRegs:$a, IVRegs:$b, IVRegs:$c), + !strconcat(asmstr, "v $d, $a, $b, $c"), + [(set IVRegs:$d, (op vi32_src:$a, vi32_src:$b, vi32_src:$c))]>; +} + +multiclass tgsi1_f32_class<bits<8> instr, SDNode op, string asmstr> { + def s: tgsi_class<instr, (outs FRegs:$d), (ins FRegs:$a), + !strconcat(asmstr, "s $d, $a"), + [(set FRegs:$d, (op f32_src:$a))]>; + + def v: tgsi_class<instr, (outs FVRegs:$d), (ins FVRegs:$a), + !strconcat(asmstr, "v $d, $a"), + [(set FVRegs:$d, (op vf32_src:$a))]>; +} + +class tgsi1_sf32_class<bits<8> instr, SDNode op, string asmstr> : + tgsi_class<instr, (outs FRegs:$d), (ins FRegs:$a), + !strconcat(asmstr, "s $d, $a"), + [(set FRegs:$d, (op f32_src:$a))]>; + +multiclass tgsi1np_f32_class<bits<8> instr, string asmstr> { + def s: tgsi_class<instr, (outs FRegs:$d), (ins FRegs:$a), + !strconcat(asmstr, "s $d, $a"), []>; + + def v: tgsi_class<instr, (outs FVRegs:$d), (ins FVRegs:$a), + !strconcat(asmstr, "v $d, $a"), []>; +} + +multiclass tgsi2_f32_class<bits<8> instr, SDNode op, string asmstr> { + def s: tgsi_class<instr, (outs FRegs:$d), (ins FRegs:$a, FRegs:$b), + !strconcat(asmstr, "s $d, $a, $b"), + [(set FRegs:$d, (op f32_src:$a, f32_src:$b))]>; + + def v: tgsi_class<instr, (outs FVRegs:$d), (ins FVRegs:$a, FVRegs:$b), + !strconcat(asmstr, "v $d, $a, $b"), + [(set FVRegs:$d, (op vf32_src:$a, vf32_src:$b))]>; +} + +multiclass tgsi2p_iff32_class<bits<8> instr, PatFrag op, string asmstr> { + def s: tgsi_class<instr, (outs IRegs:$d), (ins FRegs:$a, FRegs:$b), + !strconcat(asmstr, "s $d, $a, $b"), + [(set IRegs:$d, (op f32_src:$a, f32_src:$b))]>; + + def v: tgsi_class<instr, (outs IVRegs:$d), (ins FVRegs:$a, FVRegs:$b), + !strconcat(asmstr, "v $d, $a, $b"), + [(set IVRegs:$d, (op vf32_src:$a, vf32_src:$b))]>; +} + +multiclass tgsi3_f32_class<bits<8> instr, SDNode op, string asmstr> { + def s: tgsi_class<instr, (outs FRegs:$d), (ins FRegs:$a, FRegs:$b, FRegs:$c), + !strconcat(asmstr, "s $d, $a, $b, $c"), + [(set FRegs:$d, (op f32_src:$a, f32_src:$b, f32_src:$c))]>; + + def v: tgsi_class<instr, (outs FVRegs:$d), (ins FVRegs:$a, FVRegs:$b, FVRegs:$c), + !strconcat(asmstr, "v $d, $a, $b, $c"), + [(set FVRegs:$d, (op vf32_src:$a, vf32_src:$b, vf32_src:$c))]>; +} + +multiclass tgsi3_fiff32_class<bits<8> instr, SDNode op, string asmstr> { + def s: tgsi_class<instr, (outs FRegs:$d), (ins IRegs:$a, FRegs:$b, FRegs:$c), + !strconcat(asmstr, "s $d, $a, $b, $c"), + [(set FRegs:$d, (op i32_src:$a, f32_src:$b, f32_src:$c))]>; + + def v: tgsi_class<instr, (outs FVRegs:$d), (ins IVRegs:$a, FVRegs:$b, FVRegs:$c), + !strconcat(asmstr, "v $d, $a, $b, $c"), + [(set FVRegs:$d, (op vi32_src:$a, vf32_src:$b, vf32_src:$c))]>; +} + +multiclass tgsi1_if32_class<bits<8> instr, SDNode op, string asmstr> { + def s: tgsi_class<instr, (outs IRegs:$d), (ins FRegs:$a), + !strconcat(asmstr, "s $d, $a"), + [(set IRegs:$d, (op f32_src:$a))]>; + + def v: tgsi_class<instr, (outs IVRegs:$d), (ins FVRegs:$a), + !strconcat(asmstr, "v $d, $a"), + [(set IVRegs:$d, (op vf32_src:$a))]>; +} + +multiclass tgsi1_fi32_class<bits<8> instr, SDNode op, string asmstr> { + def s: tgsi_class<instr, (outs FRegs:$d), (ins IRegs:$a), + !strconcat(asmstr, "s $d, $a"), + [(set FRegs:$d, (op i32_src:$a))]>; + + def v: tgsi_class<instr, (outs FVRegs:$d), (ins IVRegs:$a), + !strconcat(asmstr, "v $d, $a"), + [(set FVRegs:$d, (op vi32_src:$a))]>; +} + +multiclass ld_class<bits<8> instr, ComplexPattern pat_ptr, string asmstr> { + def is: tgsi_class<instr, (outs IRegs:$d), (ins IRegs:$a), + !strconcat(asmstr, "is $d, [$a]"), + [(set IRegs:$d, (load pat_ptr:$a))]>, tgsi_src_resource_class; + + def fs: tgsi_class<instr, (outs FRegs:$d), (ins IRegs:$a), + !strconcat(asmstr, "fs $d, [$a]"), + [(set FRegs:$d, (load pat_ptr:$a))]>, tgsi_src_resource_class; + + def iv: tgsi_class<instr, (outs IVRegs:$d), (ins IRegs:$a), + !strconcat(asmstr, "iv $d, [$a]"), + [(set IVRegs:$d, (load pat_ptr:$a))]>, tgsi_src_resource_class; + + def fv: tgsi_class<instr, (outs FVRegs:$d), (ins IRegs:$a), + !strconcat(asmstr, "fv $d, [$a]"), + [(set FVRegs:$d, (load pat_ptr:$a))]>, tgsi_src_resource_class; +} + +multiclass st_class<bits<8> instr, ComplexPattern pat_ptr, string asmstr> { + def is: tgsi_class<instr, (outs), (ins IRegs:$d, IRegs:$a), + !strconcat(asmstr, "is [$d], $a"), + [(store i32_src:$a, pat_ptr:$d)]>, tgsi_dst_resource_class; + + def fs: tgsi_class<instr, (outs), (ins IRegs:$d, FRegs:$a), + !strconcat(asmstr, "fs [$d], $a"), + [(store f32_src:$a, pat_ptr:$d)]>, tgsi_dst_resource_class; + + def iv: tgsi_class<instr, (outs), (ins IRegs:$d, IVRegs:$a), + !strconcat(asmstr, "iv [$d], $a"), + [(store vi32_src:$a, pat_ptr:$d)]>, tgsi_dst_resource_class; + + def fv: tgsi_class<instr, (outs), (ins IRegs:$d, FVRegs:$a), + !strconcat(asmstr, "fv [$d], $a"), + [(store vf32_src:$a, pat_ptr:$d)]>, tgsi_dst_resource_class; +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// +defm LDp : ld_class<145, private_ptr, "LOADp">, tgsi_addr_space_private_class; +defm LDg : ld_class<145, global_ptr, "LOADg">, tgsi_addr_space_global_class; +defm LDl : ld_class<145, local_ptr, "LOADl">, tgsi_addr_space_local_class; +defm LDc : ld_class<145, const_ptr, "LOADc">, tgsi_addr_space_constant_class; +defm LDi : ld_class<145, input_ptr, "LOADi">, tgsi_addr_space_input_class; +defm STp : st_class<159, private_ptr, "STOREp">, tgsi_addr_space_private_class; +defm STg : st_class<159, global_ptr, "STOREg">, tgsi_addr_space_global_class; +defm STl : st_class<159, local_ptr, "STOREl">, tgsi_addr_space_local_class; + +defm MOVi : tgsi1np_i32_class<1, "MOVi">; +defm INEG : tgsi1np_i32_class<123, "INEG">; +defm NOT : tgsi1p_i32_class<85, not, "NOT">; +defm UADD : tgsi2_i32_class<129, add, "UADD">; +defm UMUL : tgsi2_i32_class<135, mul, "UMUL">; +defm UDIV : tgsi2_i32_class<130, udiv, "UDIV">; +defm IDIV : tgsi2_i32_class<120, sdiv, "IDIV">; +defm UMOD : tgsi2_i32_class<134, urem, "UMOD">; +defm MOD : tgsi2_i32_class<91, srem, "MOD">; +defm SHL : tgsi2_i32_class<87, shl, "SHL">; +defm USHR : tgsi2_i32_class<138, srl, "USHR">; +defm ISHR : tgsi2_i32_class<125, sra, "ISHR">; +defm AND : tgsi2_i32_class<89, and, "AND">; +defm OR : tgsi2_i32_class<90, or, "OR">; +defm XOR : tgsi2_i32_class<92, xor, "XOR">; + +defm USEQ : tgsi2p_i32_class<136, seteq, "USEQ">; +defm USNE : tgsi2p_i32_class<140, setne, "USNE">; +defm USLT : tgsi2p_i32_class<139, setult, "USLT">; +defm USGTnn : tgsi2p_i32_class<139, setugt, "USGTnn">, + tgsi_negate_op0_class, tgsi_negate_op1_class; +defm USGE : tgsi2p_i32_class<137, setuge, "USGE">; +defm USGEnn : tgsi2p_i32_class<137, setule, "USGEnn">, + tgsi_negate_op0_class, tgsi_negate_op1_class; +defm ISGE : tgsi2p_i32_class<124, setge, "ISGE">; +defm ISGEnn : tgsi2p_i32_class<124, setle, "ISGEnn">, + tgsi_negate_op0_class, tgsi_negate_op1_class; +defm ISLT : tgsi2p_i32_class<126, setlt, "ISLT">; +defm ISGT : tgsi2p_i32_class<126, setgt, "ISGT">, + tgsi_negate_op0_class, tgsi_negate_op1_class; +defm UCMPi : tgsi3_i32_class<158, select, "UCMPi">; + +defm MOVf : tgsi1np_f32_class<1, "MOVf">; +defm SSG : tgsi1np_f32_class<65, "SSG">; +defm MOVfn : tgsi1_f32_class<1, fneg, "MOVfn">, tgsi_negate_op0_class; +defm ABS : tgsi1_f32_class<33, fabs, "ABS">; +def SIN : tgsi1_sf32_class<48, fsin, "SIN">; +def COS : tgsi1_sf32_class<36, fcos, "COS">; +def LG2 : tgsi1_sf32_class<29, flog2, "LG2">; +def EX2 : tgsi1_sf32_class<28, fexp2, "EX2">; +defm CEIL : tgsi1_f32_class<83, fceil, "CEIL">; +defm TRUNC : tgsi1_f32_class<86, ftrunc, "TRUNC">; +defm ROUND : tgsi1_f32_class<27, fnearbyint, "ROUND">; +defm FLR : tgsi1_f32_class<26, ffloor, "FLR">; +defm ADD : tgsi2_f32_class<8, fadd, "ADD">; +defm SUB : tgsi2_f32_class<17, fsub, "SUB">; +defm MUL : tgsi2_f32_class<7, fmul, "MUL">; +defm DIV : tgsi2_f32_class<70, fdiv, "DIV">; +defm MAD : tgsi3_f32_class<16, fma, "MAD">; + +defm SEQ : tgsi2p_iff32_class<45, setoeq, "SEQ">; +defm SNE : tgsi2p_iff32_class<50, setone, "SNE">; +defm SLT : tgsi2p_iff32_class<14, setolt, "SLT">; +defm SLE : tgsi2p_iff32_class<49, setole, "SLE">; +defm SGT : tgsi2p_iff32_class<47, setogt, "SGT">; +defm SGE : tgsi2p_iff32_class<15, setoge, "SGE">; +defm UCMPf : tgsi3_fiff32_class<158, select, "UCMPf">; + +defm I2F : tgsi1_fi32_class<84, sint_to_fp, "I2F">; +defm U2F : tgsi1_fi32_class<128, uint_to_fp, "U2F">; +defm F2I : tgsi1_if32_class<119, fp_to_sint, "F2I">; +defm F2U : tgsi1_if32_class<127, fp_to_uint, "F2U">; + +let isBranch = 1, isTerminator = 1, isBarrier = 1 in { + def IF : tgsi_class<74, (outs), (ins IRegs:$s), "IF $s", []>; + def ELSE : tgsi_class<77, (outs), (ins), "ELSE", []>; + def ENDIF : tgsi_class<78, (outs), (ins), "ENDIF", []>; + def ENDLOOP : tgsi_class<101, (outs), (ins), "ENDLOOP", []>; + def CONT : tgsi_class<96, (outs), (ins), "CONT", []>; + def BRK : tgsi_class<73, (outs), (ins), "BRK", []>; +} + +let isBarrier = 1 in + def BGNLOOP : tgsi_class<99, (outs), (ins), "BGNLOOP", []>; + +let isBranch = 1, isTerminator = 1, isBarrier = 1 in + def BRA : tgsi_class<62, (outs), (ins brtarget:$d), "BRA $d", [(br bb:$d)]>; + +let isReturn = 1, isTerminator = 1, isBarrier = 1 in + def RET : tgsi_class<64, (outs), (ins), "RET", [(ret)]>; + +let isCall = 1, Defs = [TEMP1] in + def CALL : tgsi_class<63, (outs), (ins calltarget:$d, variable_ops), + "CAL $d", [(call i32_imm:$d)]>; + +def BGNSUB : tgsi_class<100, (outs), (ins), "BGNSUB", []>; +def ENDSUB : tgsi_class<102, (outs), (ins), "ENDSUB", []>; + +//===----------------------------------------------------------------------===// +// Pseudo-Instructions +//===----------------------------------------------------------------------===// + +let isBranch = 1, isTerminator = 1, isBarrier = 1 in +def P_BRCOND : tgsi_class<-1, (outs), (ins IRegs:$c, brtarget:$d), + "P_BRCOND $c, $d", [(brcond IRegs:$c, bb:$d)]>; + +//===----------------------------------------------------------------------===// +// Non-Instruction Patterns +//===----------------------------------------------------------------------===// + +def : Pat<(i32 imm:$a), (MOVis imm:$a)>; +def : Pat<(f32 (bitconvert (i32 IRegs:$a))), (f32 FRegs:$a)>; +def : Pat<(i32 (load_input i32_imm:$a)), (i32 (LDiis i32_imm:$a))>; +def : Pat<(sub i32_src:$a, i32_src:$b), (UADDs (INEGs i32_src:$b), i32_src:$a)>; + +def : Pat<(f32 fpimm:$a), (MOVfs fpimm:$a)>; +def : Pat<(i32 (bitconvert (f32 FRegs:$a))), (i32 IRegs:$a)>; +def : Pat<(f32 (load_input i32_src:$a)), (f32 (LDifs i32_src:$a))>; +def : Pat<(fgetsign f32_src:$a), (F2Is (SSGs f32_src:$a))>; + +def : Pat<(setgt f32_src:$a, f32_src:$b), (SGTs f32_src:$a, f32_src:$b)>; +def : Pat<(seteq f32_src:$a, f32_src:$b), (SEQs f32_src:$a, f32_src:$b)>; +def : Pat<(setne f32_src:$a, f32_src:$b), (SNEs f32_src:$a, f32_src:$b)>; +def : Pat<(setlt f32_src:$a, f32_src:$b), (SLTs f32_src:$a, f32_src:$b)>; +def : Pat<(setle f32_src:$a, f32_src:$b), (SLEs f32_src:$a, f32_src:$b)>; +def : Pat<(setgt f32_src:$a, f32_src:$b), (SGTs f32_src:$a, f32_src:$b)>; +def : Pat<(setge f32_src:$a, f32_src:$b), (SGEs f32_src:$a, f32_src:$b)>; + +def : Pat<(v4f32 (bitconvert (v4i32 IVRegs:$a))), (v4f32 FVRegs:$a)>; +def : Pat<(v4i32 (load_input i32_src:$a)), (v4i32 (LDiiv i32_src:$a))>; +def : Pat<(v4i32 (bitconvert (v4f32 FVRegs:$a))), (v4i32 IVRegs:$a)>; +def : Pat<(v4f32 (load_input i32_src:$a)), (v4f32 (LDifv i32_src:$a))>; diff --git a/lib/Target/TGSI/TGSIRegisterInfo.cpp b/lib/Target/TGSI/TGSIRegisterInfo.cpp new file mode 100644 index 00000000000..f3be9ed636d --- /dev/null +++ b/lib/Target/TGSI/TGSIRegisterInfo.cpp @@ -0,0 +1,104 @@ +//===- TGSIRegisterInfo.cpp - TGSI Register Information -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the TGSI implementation of the TargetRegisterInfo class. +// +//===----------------------------------------------------------------------===// + +#include "TGSI.h" +#include "TGSIRegisterInfo.h" +#include "TGSISubtarget.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/IR/Type.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/STLExtras.h" + +#define GET_REGINFO_TARGET_DESC +#include "TGSIGenRegisterInfo.inc" + +using namespace llvm; + +TGSIRegisterInfo::TGSIRegisterInfo(TGSISubtarget &st, + const TargetInstrInfo &tii) + : TGSIGenRegisterInfo(0), Subtarget(st), TII(tii) { +} + +const MCPhysReg *TGSIRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) + const { + static const MCPhysReg regs[] = { + TGSI::TEMP2, TGSI::TEMP3, TGSI::TEMP4, TGSI::TEMP5, TGSI::TEMP6, + TGSI::TEMP7, TGSI::TEMP8, TGSI::TEMP9, TGSI::TEMP10, TGSI::TEMP11, + TGSI::TEMP12, TGSI::TEMP13, TGSI::TEMP14, TGSI::TEMP15, TGSI::TEMP16, + TGSI::TEMP17, TGSI::TEMP18, TGSI::TEMP19, TGSI::TEMP20, TGSI::TEMP21, + TGSI::TEMP22, TGSI::TEMP23, TGSI::TEMP24, TGSI::TEMP25, TGSI::TEMP26, + TGSI::TEMP27, TGSI::TEMP28, TGSI::TEMP29, TGSI::TEMP30, TGSI::TEMP31 + }; + + return regs; +} + +BitVector TGSIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + BitVector rsv(getNumRegs()); + + rsv.set(TGSI::TEMP0x); + rsv.set(TGSI::TEMP0y); + rsv.set(TGSI::TEMP0z); + rsv.set(TGSI::TEMP0w); + rsv.set(TGSI::TEMP0); + + rsv.set(TGSI::ADDR0x); + rsv.set(TGSI::ADDR0y); + rsv.set(TGSI::ADDR0z); + rsv.set(TGSI::ADDR0w); + rsv.set(TGSI::ADDR0); + return rsv; +} + +void TGSIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator ii, + int spadj, unsigned int fiop, + RegScavenger *rs) const { + unsigned i = 0; + MachineInstr &mi = *ii; + DebugLoc dl = mi.getDebugLoc(); + MachineFunction &mf = *mi.getParent()->getParent(); + + assert(spadj == 0); + + while (!mi.getOperand(i).isFI()) { + ++i; + assert(i < mi.getNumOperands() && "Instr doesn't have FrameIndex operand!"); + } + + int frameidx = mi.getOperand(i).getIndex(); + int offset = mf.getFrameInfo()->getObjectOffset(frameidx); + + // Replace frame index with a frame pointer reference. + BuildMI(*mi.getParent(), ii, dl, TII.get(TGSI::UADDs), TGSI::TEMP0y) + .addReg(TGSI::TEMP0x).addImm(offset); + mi.getOperand(i).ChangeToRegister(TGSI::TEMP0y, false); +} + +unsigned TGSIRegisterInfo::getFrameRegister(const MachineFunction &MF) const { + llvm_unreachable("What is the frame register"); + return 0; +} + +unsigned TGSIRegisterInfo::getEHExceptionRegister() const { + llvm_unreachable("What is the exception register"); + return 0; +} + +unsigned TGSIRegisterInfo::getEHHandlerRegister() const { + llvm_unreachable("What is the exception handler register"); + return 0; +} diff --git a/lib/Target/TGSI/TGSIRegisterInfo.h b/lib/Target/TGSI/TGSIRegisterInfo.h new file mode 100644 index 00000000000..1840f08e765 --- /dev/null +++ b/lib/Target/TGSI/TGSIRegisterInfo.h @@ -0,0 +1,59 @@ +//===- TGSIRegisterInfo.h - TGSI Register Information Impl ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the TGSI implementation of the TargetRegisterInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef TGSI_REGISTER_INFO_H +#define TGSI_REGISTER_INFO_H + +#define GET_REGINFO_HEADER +#include "TGSIGenRegisterInfo.inc" + +namespace llvm { + class TGSISubtarget; + class TargetInstrInfo; + class Type; + + namespace TGSIRF { + enum { + INDEX = 0xfff, + COMPONENT = 0xf000, + COMPONENT_X = 0x1000, + COMPONENT_Y = 0x2000, + COMPONENT_Z = 0x4000, + COMPONENT_W = 0x8000, + COMPONENT_XYZW = 0xf000 + }; + } + + struct TGSIRegisterInfo : public TGSIGenRegisterInfo { + TGSISubtarget &Subtarget; + const TargetInstrInfo &TII; + + TGSIRegisterInfo(TGSISubtarget &st, const TargetInstrInfo &tii); + + const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const; + + BitVector getReservedRegs(const MachineFunction &MF) const; + + void eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, unsigned FIOperandNum, + RegScavenger *RS = NULL) const; + + unsigned getFrameRegister(const MachineFunction &MF) const; + + unsigned getEHExceptionRegister() const; + unsigned getEHHandlerRegister() const; + }; + +} + +#endif diff --git a/lib/Target/TGSI/TGSIRegisterInfo.td b/lib/Target/TGSI/TGSIRegisterInfo.td new file mode 100644 index 00000000000..43b9fd1af48 --- /dev/null +++ b/lib/Target/TGSI/TGSIRegisterInfo.td @@ -0,0 +1,216 @@ +//===- TGSIRegisterInfo.td - TGSI Register defs ----------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Declarations that describe the TGSI register file +//===----------------------------------------------------------------------===// + +let Namespace = "TGSI" in { + def sub_x : SubRegIndex; + def sub_y : SubRegIndex; + def sub_z : SubRegIndex; + def sub_w : SubRegIndex; + + class TGSIReg<string n, int id, int c> : Register<n> { + let HWEncoding{11-0} = id; + let HWEncoding{15-12} = c; + } + + class TGSIVReg<string n, int id, list<Register> subregs> : + RegisterWithSubRegs<n, subregs> { + let HWEncoding{11-0} = id; + let HWEncoding{15-12} = 0xf; + let SubRegIndices = [sub_x, sub_y, sub_z, sub_w]; + } +} + +// Temporary registers +def TEMP0x : TGSIReg<"TEMP0x", 0, 1>; +def TEMP0y : TGSIReg<"TEMP0y", 0, 2>; +def TEMP0z : TGSIReg<"TEMP0z", 0, 4>; +def TEMP0w : TGSIReg<"TEMP0w", 0, 8>; +def TEMP0 : TGSIVReg<"TEMP0", 0, [TEMP0x, TEMP0y, TEMP0z, TEMP0w]>; +def TEMP1x : TGSIReg<"TEMP1x", 1, 1>; +def TEMP1y : TGSIReg<"TEMP1y", 1, 2>; +def TEMP1z : TGSIReg<"TEMP1z", 1, 4>; +def TEMP1w : TGSIReg<"TEMP1w", 1, 8>; +def TEMP1 : TGSIVReg<"TEMP1", 1, [TEMP1x, TEMP1y, TEMP1z, TEMP1w]>; +def TEMP2x : TGSIReg<"TEMP2x", 2, 1>; +def TEMP2y : TGSIReg<"TEMP2y", 2, 2>; +def TEMP2z : TGSIReg<"TEMP2z", 2, 4>; +def TEMP2w : TGSIReg<"TEMP2w", 2, 8>; +def TEMP2 : TGSIVReg<"TEMP2", 2, [TEMP2x, TEMP2y, TEMP2z, TEMP2w]>; +def TEMP3x : TGSIReg<"TEMP3x", 3, 1>; +def TEMP3y : TGSIReg<"TEMP3y", 3, 2>; +def TEMP3z : TGSIReg<"TEMP3z", 3, 4>; +def TEMP3w : TGSIReg<"TEMP3w", 3, 8>; +def TEMP3 : TGSIVReg<"TEMP3", 3, [TEMP3x, TEMP3y, TEMP3z, TEMP3w]>; +def TEMP4x : TGSIReg<"TEMP4x", 4, 1>; +def TEMP4y : TGSIReg<"TEMP4y", 4, 2>; +def TEMP4z : TGSIReg<"TEMP4z", 4, 4>; +def TEMP4w : TGSIReg<"TEMP4w", 4, 8>; +def TEMP4 : TGSIVReg<"TEMP4", 4, [TEMP4x, TEMP4y, TEMP4z, TEMP4w]>; +def TEMP5x : TGSIReg<"TEMP5x", 5, 1>; +def TEMP5y : TGSIReg<"TEMP5y", 5, 2>; +def TEMP5z : TGSIReg<"TEMP5z", 5, 4>; +def TEMP5w : TGSIReg<"TEMP5w", 5, 8>; +def TEMP5 : TGSIVReg<"TEMP5", 5, [TEMP5x, TEMP5y, TEMP5z, TEMP5w]>; +def TEMP6x : TGSIReg<"TEMP6x", 6, 1>; +def TEMP6y : TGSIReg<"TEMP6y", 6, 2>; +def TEMP6z : TGSIReg<"TEMP6z", 6, 4>; +def TEMP6w : TGSIReg<"TEMP6w", 6, 8>; +def TEMP6 : TGSIVReg<"TEMP6", 6, [TEMP6x, TEMP6y, TEMP6z, TEMP6w]>; +def TEMP7x : TGSIReg<"TEMP7x", 7, 1>; +def TEMP7y : TGSIReg<"TEMP7y", 7, 2>; +def TEMP7z : TGSIReg<"TEMP7z", 7, 4>; +def TEMP7w : TGSIReg<"TEMP7w", 7, 8>; +def TEMP7 : TGSIVReg<"TEMP7", 7, [TEMP7x, TEMP7y, TEMP7z, TEMP7w]>; +def TEMP8x : TGSIReg<"TEMP8x", 8, 1>; +def TEMP8y : TGSIReg<"TEMP8y", 8, 2>; +def TEMP8z : TGSIReg<"TEMP8z", 8, 4>; +def TEMP8w : TGSIReg<"TEMP8w", 8, 8>; +def TEMP8 : TGSIVReg<"TEMP8", 8, [TEMP8x, TEMP8y, TEMP8z, TEMP8w]>; +def TEMP9x : TGSIReg<"TEMP9x", 9, 1>; +def TEMP9y : TGSIReg<"TEMP9y", 9, 2>; +def TEMP9z : TGSIReg<"TEMP9z", 9, 4>; +def TEMP9w : TGSIReg<"TEMP9w", 9, 8>; +def TEMP9 : TGSIVReg<"TEMP9", 9, [TEMP9x, TEMP9y, TEMP9z, TEMP9w]>; +def TEMP10x : TGSIReg<"TEMP10x", 10, 1>; +def TEMP10y : TGSIReg<"TEMP10y", 10, 2>; +def TEMP10z : TGSIReg<"TEMP10z", 10, 4>; +def TEMP10w : TGSIReg<"TEMP10w", 10, 8>; +def TEMP10 : TGSIVReg<"TEMP10", 10, [TEMP10x, TEMP10y, TEMP10z, TEMP10w]>; +def TEMP11x : TGSIReg<"TEMP11x", 11, 1>; +def TEMP11y : TGSIReg<"TEMP11y", 11, 2>; +def TEMP11z : TGSIReg<"TEMP11z", 11, 4>; +def TEMP11w : TGSIReg<"TEMP11w", 11, 8>; +def TEMP11 : TGSIVReg<"TEMP11", 11, [TEMP11x, TEMP11y, TEMP11z, TEMP11w]>; +def TEMP12x : TGSIReg<"TEMP12x", 12, 1>; +def TEMP12y : TGSIReg<"TEMP12y", 12, 2>; +def TEMP12z : TGSIReg<"TEMP12z", 12, 4>; +def TEMP12w : TGSIReg<"TEMP12w", 12, 8>; +def TEMP12 : TGSIVReg<"TEMP12", 12, [TEMP12x, TEMP12y, TEMP12z, TEMP12w]>; +def TEMP13x : TGSIReg<"TEMP13x", 13, 1>; +def TEMP13y : TGSIReg<"TEMP13y", 13, 2>; +def TEMP13z : TGSIReg<"TEMP13z", 13, 4>; +def TEMP13w : TGSIReg<"TEMP13w", 13, 8>; +def TEMP13 : TGSIVReg<"TEMP13", 13, [TEMP13x, TEMP13y, TEMP13z, TEMP13w]>; +def TEMP14x : TGSIReg<"TEMP14x", 14, 1>; +def TEMP14y : TGSIReg<"TEMP14y", 14, 2>; +def TEMP14z : TGSIReg<"TEMP14z", 14, 4>; +def TEMP14w : TGSIReg<"TEMP14w", 14, 8>; +def TEMP14 : TGSIVReg<"TEMP14", 14, [TEMP14x, TEMP14y, TEMP14z, TEMP14w]>; +def TEMP15x : TGSIReg<"TEMP15x", 15, 1>; +def TEMP15y : TGSIReg<"TEMP15y", 15, 2>; +def TEMP15z : TGSIReg<"TEMP15z", 15, 4>; +def TEMP15w : TGSIReg<"TEMP15w", 15, 8>; +def TEMP15 : TGSIVReg<"TEMP15", 15, [TEMP15x, TEMP15y, TEMP15z, TEMP15w]>; +def TEMP16x : TGSIReg<"TEMP16x", 16, 1>; +def TEMP16y : TGSIReg<"TEMP16y", 16, 2>; +def TEMP16z : TGSIReg<"TEMP16z", 16, 4>; +def TEMP16w : TGSIReg<"TEMP16w", 16, 8>; +def TEMP16 : TGSIVReg<"TEMP16", 16, [TEMP16x, TEMP16y, TEMP16z, TEMP16w]>; +def TEMP17x : TGSIReg<"TEMP17x", 17, 1>; +def TEMP17y : TGSIReg<"TEMP17y", 17, 2>; +def TEMP17z : TGSIReg<"TEMP17z", 17, 4>; +def TEMP17w : TGSIReg<"TEMP17w", 17, 8>; +def TEMP17 : TGSIVReg<"TEMP17", 17, [TEMP17x, TEMP17y, TEMP17z, TEMP17w]>; +def TEMP18x : TGSIReg<"TEMP18x", 18, 1>; +def TEMP18y : TGSIReg<"TEMP18y", 18, 2>; +def TEMP18z : TGSIReg<"TEMP18z", 18, 4>; +def TEMP18w : TGSIReg<"TEMP18w", 18, 8>; +def TEMP18 : TGSIVReg<"TEMP18", 18, [TEMP18x, TEMP18y, TEMP18z, TEMP18w]>; +def TEMP19x : TGSIReg<"TEMP19x", 19, 1>; +def TEMP19y : TGSIReg<"TEMP19y", 19, 2>; +def TEMP19z : TGSIReg<"TEMP19z", 19, 4>; +def TEMP19w : TGSIReg<"TEMP19w", 19, 8>; +def TEMP19 : TGSIVReg<"TEMP19", 19, [TEMP19x, TEMP19y, TEMP19z, TEMP19w]>; +def TEMP20x : TGSIReg<"TEMP20x", 20, 1>; +def TEMP20y : TGSIReg<"TEMP20y", 20, 2>; +def TEMP20z : TGSIReg<"TEMP20z", 20, 4>; +def TEMP20w : TGSIReg<"TEMP20w", 20, 8>; +def TEMP20 : TGSIVReg<"TEMP20", 20, [TEMP20x, TEMP20y, TEMP20z, TEMP20w]>; +def TEMP21x : TGSIReg<"TEMP21x", 21, 1>; +def TEMP21y : TGSIReg<"TEMP21y", 21, 2>; +def TEMP21z : TGSIReg<"TEMP21z", 21, 4>; +def TEMP21w : TGSIReg<"TEMP21w", 21, 8>; +def TEMP21 : TGSIVReg<"TEMP21", 21, [TEMP21x, TEMP21y, TEMP21z, TEMP21w]>; +def TEMP22x : TGSIReg<"TEMP22x", 22, 1>; +def TEMP22y : TGSIReg<"TEMP22y", 22, 2>; +def TEMP22z : TGSIReg<"TEMP22z", 22, 4>; +def TEMP22w : TGSIReg<"TEMP22w", 22, 8>; +def TEMP22 : TGSIVReg<"TEMP22", 22, [TEMP22x, TEMP22y, TEMP22z, TEMP22w]>; +def TEMP23x : TGSIReg<"TEMP23x", 23, 1>; +def TEMP23y : TGSIReg<"TEMP23y", 23, 2>; +def TEMP23z : TGSIReg<"TEMP23z", 23, 4>; +def TEMP23w : TGSIReg<"TEMP23w", 23, 8>; +def TEMP23 : TGSIVReg<"TEMP23", 23, [TEMP23x, TEMP23y, TEMP23z, TEMP23w]>; +def TEMP24x : TGSIReg<"TEMP24x", 24, 1>; +def TEMP24y : TGSIReg<"TEMP24y", 24, 2>; +def TEMP24z : TGSIReg<"TEMP24z", 24, 4>; +def TEMP24w : TGSIReg<"TEMP24w", 24, 8>; +def TEMP24 : TGSIVReg<"TEMP24", 24, [TEMP24x, TEMP24y, TEMP24z, TEMP24w]>; +def TEMP25x : TGSIReg<"TEMP25x", 25, 1>; +def TEMP25y : TGSIReg<"TEMP25y", 25, 2>; +def TEMP25z : TGSIReg<"TEMP25z", 25, 4>; +def TEMP25w : TGSIReg<"TEMP25w", 25, 8>; +def TEMP25 : TGSIVReg<"TEMP25", 25, [TEMP25x, TEMP25y, TEMP25z, TEMP25w]>; +def TEMP26x : TGSIReg<"TEMP26x", 26, 1>; +def TEMP26y : TGSIReg<"TEMP26y", 26, 2>; +def TEMP26z : TGSIReg<"TEMP26z", 26, 4>; +def TEMP26w : TGSIReg<"TEMP26w", 26, 8>; +def TEMP26 : TGSIVReg<"TEMP26", 26, [TEMP26x, TEMP26y, TEMP26z, TEMP26w]>; +def TEMP27x : TGSIReg<"TEMP27x", 27, 1>; +def TEMP27y : TGSIReg<"TEMP27y", 27, 2>; +def TEMP27z : TGSIReg<"TEMP27z", 27, 4>; +def TEMP27w : TGSIReg<"TEMP27w", 27, 8>; +def TEMP27 : TGSIVReg<"TEMP27", 27, [TEMP27x, TEMP27y, TEMP27z, TEMP27w]>; +def TEMP28x : TGSIReg<"TEMP28x", 28, 1>; +def TEMP28y : TGSIReg<"TEMP28y", 28, 2>; +def TEMP28z : TGSIReg<"TEMP28z", 28, 4>; +def TEMP28w : TGSIReg<"TEMP28w", 28, 8>; +def TEMP28 : TGSIVReg<"TEMP28", 28, [TEMP28x, TEMP28y, TEMP28z, TEMP28w]>; +def TEMP29x : TGSIReg<"TEMP29x", 29, 1>; +def TEMP29y : TGSIReg<"TEMP29y", 29, 2>; +def TEMP29z : TGSIReg<"TEMP29z", 29, 4>; +def TEMP29w : TGSIReg<"TEMP29w", 29, 8>; +def TEMP29 : TGSIVReg<"TEMP29", 29, [TEMP29x, TEMP29y, TEMP29z, TEMP29w]>; +def TEMP30x : TGSIReg<"TEMP30x", 30, 1>; +def TEMP30y : TGSIReg<"TEMP30y", 30, 2>; +def TEMP30z : TGSIReg<"TEMP30z", 30, 4>; +def TEMP30w : TGSIReg<"TEMP30w", 30, 8>; +def TEMP30 : TGSIVReg<"TEMP30", 30, [TEMP30x, TEMP30y, TEMP30z, TEMP30w]>; +def TEMP31x : TGSIReg<"TEMP31x", 31, 1>; +def TEMP31y : TGSIReg<"TEMP31y", 31, 2>; +def TEMP31z : TGSIReg<"TEMP31z", 31, 4>; +def TEMP31w : TGSIReg<"TEMP31w", 31, 8>; +def TEMP31 : TGSIVReg<"TEMP31", 31, [TEMP31x, TEMP31y, TEMP31z, TEMP31w]>; + +// Address register +def ADDR0x : TGSIReg<"ADDR0x", 0, 1>; +def ADDR0y : TGSIReg<"ADDR0y", 0, 2>; +def ADDR0z : TGSIReg<"ADDR0z", 0, 4>; +def ADDR0w : TGSIReg<"ADDR0w", 0, 8>; +def ADDR0 : TGSIVReg<"ADDR0", 0, [ADDR0x, ADDR0y, ADDR0z, ADDR0w]>; + +// Register classes. +// +def IRegs : RegisterClass<"TGSI", [i32], 32, + (add (sequence "TEMP%ux", 0, 31), (sequence "TEMP%uy", 0, 31), + (sequence "TEMP%uz", 0, 31), (sequence "TEMP%uw", 0, 31))>; +def IVRegs : RegisterClass<"TGSI", [v4i32], 128, (sequence "TEMP%u", 0, 31)>; +def FRegs : RegisterClass<"TGSI", [f32], 32, + (add (sequence "TEMP%ux", 0, 31), (sequence "TEMP%uy", 0, 31), + (sequence "TEMP%uz", 0, 31), (sequence "TEMP%uw", 0, 31))>; +def FVRegs : RegisterClass<"TGSI", [v4f32], 128, (sequence "TEMP%u", 0, 31)>; +def ARegs : RegisterClass<"TGSI", [i32], 32, + (add (sequence "ADDR%ux", 0, 0), (sequence "ADDR%uy", 0, 0), + (sequence "ADDR%uz", 0, 0), (sequence "ADDR%uw", 0, 0))>; +def AVRegs : RegisterClass<"TGSI", [i32], 128, (sequence "ADDR%u", 0, 0)>; + diff --git a/lib/Target/TGSI/TGSISelectionDAGInfo.cpp b/lib/Target/TGSI/TGSISelectionDAGInfo.cpp new file mode 100644 index 00000000000..6faa560dc35 --- /dev/null +++ b/lib/Target/TGSI/TGSISelectionDAGInfo.cpp @@ -0,0 +1,23 @@ +//===-- TGSISelectionDAGInfo.cpp - TGSI SelectionDAG Info ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the TGSISelectionDAGInfo class. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "tgsi-selectiondag-info" +#include "TGSITargetMachine.h" +using namespace llvm; + +TGSISelectionDAGInfo::TGSISelectionDAGInfo(const TGSITargetMachine &TM) + : TargetSelectionDAGInfo(TM) { +} + +TGSISelectionDAGInfo::~TGSISelectionDAGInfo() { +} diff --git a/lib/Target/TGSI/TGSISelectionDAGInfo.h b/lib/Target/TGSI/TGSISelectionDAGInfo.h new file mode 100644 index 00000000000..799a841efc7 --- /dev/null +++ b/lib/Target/TGSI/TGSISelectionDAGInfo.h @@ -0,0 +1,30 @@ +//===-- TGSISelectionDAGInfo.h - TGSI SelectionDAG Info -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the TGSI subclass for TargetSelectionDAGInfo. +// +//===----------------------------------------------------------------------===// + +#ifndef TGSI_SELECTION_DAG_INFO_H +#define TGSI_SELECTION_DAG_INFO_H + +#include "llvm/Target/TargetSelectionDAGInfo.h" + +namespace llvm { + class TGSITargetMachine; + + class TGSISelectionDAGInfo : public TargetSelectionDAGInfo { + public: + explicit TGSISelectionDAGInfo(const TGSITargetMachine &TM); + ~TGSISelectionDAGInfo(); + }; + +} + +#endif diff --git a/lib/Target/TGSI/TGSISubtarget.cpp b/lib/Target/TGSI/TGSISubtarget.cpp new file mode 100644 index 00000000000..c6add741f80 --- /dev/null +++ b/lib/Target/TGSI/TGSISubtarget.cpp @@ -0,0 +1,33 @@ +//===- TGSISubtarget.cpp - TGSI Subtarget Information -------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the TGSI specific subclass of TargetSubtargetInfo. +// +//===----------------------------------------------------------------------===// + +#include "TGSISubtarget.h" +#include "TGSI.h" +#include "llvm/Support/TargetRegistry.h" + +#define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR +#include "TGSIGenSubtargetInfo.inc" + +using namespace llvm; + +TGSISubtarget::TGSISubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS) : + TGSIGenSubtargetInfo(TT, CPU, FS) { + + // Determine default and user specified characteristics + std::string CPUName = CPU.empty() ? "TGSI" : CPU; + + // Parse features string. + ParseSubtargetFeatures(CPUName, FS); +} diff --git a/lib/Target/TGSI/TGSISubtarget.h b/lib/Target/TGSI/TGSISubtarget.h new file mode 100644 index 00000000000..6f434408cf9 --- /dev/null +++ b/lib/Target/TGSI/TGSISubtarget.h @@ -0,0 +1,40 @@ +//=====-- TGSISubtarget.h - Define Subtarget for the TGSI ----*- C++ -*-====// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the TGSI specific subclass of TargetSubtargetInfo. +// +//===----------------------------------------------------------------------===// + +#ifndef TGSI_SUBTARGET_H +#define TGSI_SUBTARGET_H + +#include "llvm/Target/TargetSubtargetInfo.h" +#include <string> + +#define GET_SUBTARGETINFO_HEADER +#include "TGSIGenSubtargetInfo.inc" + +namespace llvm { + class StringRef; + + class TGSISubtarget : public TGSIGenSubtargetInfo { + public: + TGSISubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS); + + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); + + std::string getDataLayout() const { + return std::string("E-p:32:32-i64:64:64-f64:64:64-f128:128:128-n32"); + } + }; + +} + +#endif diff --git a/lib/Target/TGSI/TGSITargetMachine.cpp b/lib/Target/TGSI/TGSITargetMachine.cpp new file mode 100644 index 00000000000..0f562ff7946 --- /dev/null +++ b/lib/Target/TGSI/TGSITargetMachine.cpp @@ -0,0 +1,59 @@ +//===-- TGSITargetMachine.cpp - Define TargetMachine for TGSI -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the TGSI specific subclass of TargetMachine. +// +//===----------------------------------------------------------------------===// + +#include "TGSI.h" +#include "TGSITargetMachine.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/PassManager.h" +#include "llvm/Support/TargetRegistry.h" +using namespace llvm; + +namespace { + class TGSIPassConfig : public TargetPassConfig { + public: + TGSIPassConfig(TGSITargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + TGSITargetMachine &getTGSITargetMachine() const { + return getTM<TGSITargetMachine>(); + } + + virtual bool addInstSelector(); + }; +} + +extern "C" void LLVMInitializeTGSITarget() { + RegisterTargetMachine<TGSITargetMachine> X(TheTGSITarget); +} + +TGSITargetMachine::TGSITargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + Subtarget(TT, CPU, FS), + dl(Subtarget.getDataLayout()), + InstrInfo(Subtarget), + TLInfo(*this), TSInfo(*this), + FrameLowering(Subtarget) { + } + +TargetPassConfig *TGSITargetMachine::createPassConfig(PassManagerBase &PM) { + return new TGSIPassConfig(this, PM); +} + +bool TGSIPassConfig::addInstSelector() { + addPass(createTGSIISelDag(getTGSITargetMachine())); + return false; +} diff --git a/lib/Target/TGSI/TGSITargetMachine.h b/lib/Target/TGSI/TGSITargetMachine.h new file mode 100644 index 00000000000..3c56cc29645 --- /dev/null +++ b/lib/Target/TGSI/TGSITargetMachine.h @@ -0,0 +1,62 @@ +//===-- TGSITargetMachine.h - Define TargetMachine for TGSI ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the TGSI specific subclass of TargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef TGSI_TARGET_MACHINE_H +#define TGSI_TARGET_MACHINE_H + +#include "TGSIInstrInfo.h" +#include "TGSIISelLowering.h" +#include "TGSIFrameLowering.h" +#include "TGSISelectionDAGInfo.h" +#include "TGSISubtarget.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetFrameLowering.h" + +namespace llvm { + class TGSITargetMachine : public LLVMTargetMachine { + TGSISubtarget Subtarget; + const DataLayout dl; // Calculates type size & alignment + TGSIInstrInfo InstrInfo; + TGSITargetLowering TLInfo; + TGSISelectionDAGInfo TSInfo; + TGSIFrameLowering FrameLowering; + public: + TGSITargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); + + virtual const TGSIInstrInfo *getInstrInfo() const { return &InstrInfo; } + virtual const TargetFrameLowering *getFrameLowering() const { + return &FrameLowering; + } + virtual const TGSISubtarget *getSubtargetImpl() const{ return &Subtarget; } + virtual const TargetRegisterInfo *getRegisterInfo() const { + return &InstrInfo.getRegisterInfo(); + } + virtual const TGSITargetLowering* getTargetLowering() const { + return &TLInfo; + } + virtual const TGSISelectionDAGInfo* getSelectionDAGInfo() const { + return &TSInfo; + } + virtual const DataLayout *getDataLayout() const { return &dl; } + + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); + }; + +} + +#endif diff --git a/lib/Target/TGSI/TargetInfo/CMakeLists.txt b/lib/Target/TGSI/TargetInfo/CMakeLists.txt new file mode 100644 index 00000000000..e351d05628e --- /dev/null +++ b/lib/Target/TGSI/TargetInfo/CMakeLists.txt @@ -0,0 +1,7 @@ +include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) + +add_llvm_library(LLVMTGSIInfo + TGSITargetInfo.cpp + ) + +add_dependencies(LLVMTGSIInfo TGSICommonTableGen) diff --git a/lib/Target/TGSI/TargetInfo/LLVMBuild.txt b/lib/Target/TGSI/TargetInfo/LLVMBuild.txt new file mode 100644 index 00000000000..09eee054943 --- /dev/null +++ b/lib/Target/TGSI/TargetInfo/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/TGSI/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = TGSIInfo +parent = TGSI +required_libraries = MC Support Target +add_to_library_groups = TGSI diff --git a/lib/Target/TGSI/TargetInfo/Makefile b/lib/Target/TGSI/TargetInfo/Makefile new file mode 100644 index 00000000000..2f840fdb2b8 --- /dev/null +++ b/lib/Target/TGSI/TargetInfo/Makefile @@ -0,0 +1,15 @@ +##===- lib/Target/TGSI/TargetInfo/Makefile ----------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## +LEVEL = ../../../.. +LIBRARYNAME = LLVMTGSIInfo + +# Hack: we need to include 'main' target directory to grab private headers +CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/lib/Target/TGSI/TargetInfo/TGSITargetInfo.cpp b/lib/Target/TGSI/TargetInfo/TGSITargetInfo.cpp new file mode 100644 index 00000000000..bf7a8b5d736 --- /dev/null +++ b/lib/Target/TGSI/TargetInfo/TGSITargetInfo.cpp @@ -0,0 +1,19 @@ +//===-- TGSITargetInfo.cpp - TGSI Target Implementation -----------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "TGSI.h" +#include "llvm/IR/Module.h" +#include "llvm/Support/TargetRegistry.h" +using namespace llvm; + +Target llvm::TheTGSITarget; + +extern "C" void LLVMInitializeTGSITargetInfo() { + RegisterTarget<Triple::tgsi> X(TheTGSITarget, "tgsi", "TGSI"); +} |