1 files changed, 78 insertions, 0 deletions
diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp b/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp
new file mode 100644
index 00000000000..ed8dd5eea46
--- /dev/null
+++ b/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp
@@ -0,0 +1,78 @@
+//===-- TGSIMCInstPrinter.cpp - Convert TGSI MCInst to assembly syntax ----===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an TGSI MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#include "MCTargetDesc/TGSIMCTargetDesc.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstPrinter.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+namespace {
+   class TGSIMCInstPrinter : public MCInstPrinter {
+   public:
+      TGSIMCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
+                        const MCRegisterInfo &mri)
+         : MCInstPrinter(mai, mii, mri) {}
+
+      virtual void printInst(const MCInst *mi, raw_ostream &os,
+                             StringRef annot);
+      virtual void printRegName(raw_ostream &os, unsigned reg) const;
+
+      // Autogenerated by tblgen.
+      void printInstruction(const MCInst *MI, raw_ostream &O);
+      static const char *getInstructionName(unsigned Opcode);
+      static const char *getRegisterName(unsigned RegNo);
+
+      void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+   };
+}
+
+#include "TGSIGenAsmWriter.inc"
+
+void TGSIMCInstPrinter::printInst(const MCInst *mi, raw_ostream &os,
+                                  StringRef annot) {
+   printInstruction(mi, os);
+   printAnnotation(os, annot);
+}
+
+void TGSIMCInstPrinter::printRegName(raw_ostream &os, unsigned reg) const {
+   os << getRegisterName(reg);
+}
+
+void TGSIMCInstPrinter::printOperand(const MCInst *mi, unsigned op_idx,
+                                     raw_ostream &os) {
+   const MCOperand &op = mi->getOperand(op_idx);
+
+   if (op.isReg())
+      os << getRegisterName(op.getReg());
+   else if (op.isImm())
+      os << op.getImm();
+   else if (op.isFPImm())
+      os << op.getFPImm();
+   else if (op.isExpr())
+      os << *op.getExpr();
+   else
+      assert(0);
+}
+
+MCInstPrinter *llvm::createTGSIMCInstPrinter(const Target &t,
+                                             unsigned SyntaxVariant,
+                                             const MCAsmInfo &mai,
+                                             const MCInstrInfo &mii,
+                                             const MCRegisterInfo &mri,
+                                             const MCSubtargetInfo &sti) {
+   return new TGSIMCInstPrinter(mai, mii, mri);
+}
+