diff options
| author | Joakim Sindholt <opensource@zhasha.com> | 2009-10-17 20:24:02 +0200 |
|---|---|---|
| committer | Joakim Sindholt <opensource@zhasha.com> | 2009-10-17 20:24:02 +0200 |
| commit | 5fd46ee9ac6d57a7886af0f2bc10e17a09a2f6b0 (patch) | |
| tree | 1cd1dcc1d32e94e962372c0a34cb5f84a0641e44 | |
| parent | 8bd15ebd0e100dc2b77c623c068d08d3519bff86 (diff) | |
doc2xml: Update with r500 accel guide 1.4
| -rw-r--r-- | doc2xml/R5xx_Acceleration_v1.4.txt (renamed from doc2xml/R5xx_Acceleration_v1.3.txt) | 895 | ||||
| -rwxr-xr-x | doc2xml/radeonreg.py | 4 |
2 files changed, 597 insertions, 302 deletions
diff --git a/doc2xml/R5xx_Acceleration_v1.3.txt b/doc2xml/R5xx_Acceleration_v1.4.txt index 3924473..beb5524 100644 --- a/doc2xml/R5xx_Acceleration_v1.3.txt +++ b/doc2xml/R5xx_Acceleration_v1.4.txt @@ -1,11 +1,11 @@ - Revision 1.3 March 30, 2008 + Revision 1.4 October 13, 2009 - 10. Registers + 11. Registers -10.1 Command Processor Registers +11.1 Command Processor Registers CP:CP_CSQ2_STAT · [R] · 32 bits · Access: 8/16/32 · MMReg:0x7fc @@ -51,8 +51,8 @@ Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 138 - Revision 1.3 March 30, 2008 +Proprietary 145 + Revision 1.4 October 13, 2009 @@ -109,8 +109,8 @@ INDIRECT2_START 6:0 none Start location of Ind Indirect Queue #2 will reside in locations © 2008 Advanced Micro Devices, Inc. -Proprietary 139 - Revision 1.3 March 30, 2008 +Proprietary 146 + Revision 1.4 October 13, 2009 @@ -165,8 +165,8 @@ DESCRIPTION: Destination Address for PIO GUI DMAs Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 140 - Revision 1.3 March 30, 2008 +Proprietary 147 + Revision 1.4 October 13, 2009 @@ -223,8 +223,8 @@ IB_BUFSZ 22:0 0x0 Indirect Buffer Size. © 2008 Advanced Micro Devices, Inc. -Proprietary 141 - Revision 1.3 March 30, 2008 +Proprietary 148 + Revision 1.4 October 13, 2009 @@ -279,8 +279,8 @@ DESCRIPTION: MicroEngine RAM Read Address Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 142 - Revision 1.3 March 30, 2008 +Proprietary 149 + Revision 1.4 October 13, 2009 @@ -338,8 +338,8 @@ RB_NO_UPDATE 27 0x0 Ring Buffer No Writ © 2008 Advanced Micro Devices, Inc. -Proprietary 143 - Revision 1.3 March 30, 2008 +Proprietary 150 + Revision 1.4 October 13, 2009 @@ -395,8 +395,8 @@ PRE_WRITE_TIMER 27:0 0x0 Pre-Write Timer. The n the CP_RB_WPTR register will be delayed until actually taking effect. Default = 0 © 2008 Advanced Micro Devices, Inc. -Proprietary 144 - Revision 1.3 March 30, 2008 +Proprietary 151 + Revision 1.4 October 13, 2009 @@ -450,8 +450,8 @@ CP:CP_VID_COMMAND · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7cc © 2008 Advanced Micro Devices, Inc. -Proprietary 145 - Revision 1.3 March 30, 2008 +Proprietary 152 + Revision 1.4 October 13, 2009 @@ -498,13 +498,13 @@ RING_VP_FETCH 9 0x0 0=Physical (Default), © 2008 Advanced Micro Devices, Inc. -Proprietary 146 - Revision 1.3 March 30, 2008 +Proprietary 153 + Revision 1.4 October 13, 2009 -10.2 Color Buffer Registers +11.2 Color Buffer Registers CB:RB3D_AARESOLVE_CTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e88 DESCRIPTION: Resolve Buffer Control. Unpipelined @@ -554,8 +554,8 @@ DESCRIPTION: Alpha Blend Control for Alpha Channel. Pipelined through the blende Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 147 - Revision 1.3 March 30, 2008 +Proprietary 154 + Revision 1.4 October 13, 2009 @@ -614,8 +614,8 @@ SRCBLEND 21:16 none Source Blend Function 34 - GL_SRC_COLOR © 2008 Advanced Micro Devices, Inc. -Proprietary 148 - Revision 1.3 March 30, 2008 +Proprietary 155 + Revision 1.4 October 13, 2009 @@ -675,8 +675,8 @@ DESTBLEND 29:24 none Destination Blend Fun 19 - RESERVED © 2008 Advanced Micro Devices, Inc. -Proprietary 149 - Revision 1.3 March 30, 2008 +Proprietary 156 + Revision 1.4 October 13, 2009 @@ -736,8 +736,8 @@ ALPHA_BLEND_ENABLE 0 0x0 Allow alpha blending wi © 2008 Advanced Micro Devices, Inc. -Proprietary 150 - Revision 1.3 March 30, 2008 +Proprietary 157 + Revision 1.4 October 13, 2009 @@ -794,8 +794,8 @@ SRCBLEND 21:16 none Source Blend Function © 2008 Advanced Micro Devices, Inc. -Proprietary 151 - Revision 1.3 March 30, 2008 +Proprietary 158 + Revision 1.4 October 13, 2009 @@ -854,8 +854,8 @@ Proprietary 50 - RESERVED © 2008 Advanced Micro Devices, Inc. -Proprietary 152 - Revision 1.3 March 30, 2008 +Proprietary 159 + Revision 1.4 October 13, 2009 @@ -915,8 +915,8 @@ DESTBLEND 29:24 none Destination Blend Fun 35 - GL_ONE_MINUS_SRC_COLOR © 2008 Advanced Micro Devices, Inc. -Proprietary 153 - Revision 1.3 March 30, 2008 +Proprietary 160 + Revision 1.4 October 13, 2009 @@ -975,8 +975,8 @@ Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 154 - Revision 1.3 March 30, 2008 +Proprietary 161 + Revision 1.4 October 13, 2009 @@ -1031,8 +1031,8 @@ AA_COMPRESSION_ENABLE 9 none Enable 01 - Enable AA compression © 2008 Advanced Micro Devices, Inc. -Proprietary 155 - Revision 1.3 March 30, 2008 +Proprietary 162 + Revision 1.4 October 13, 2009 @@ -1088,8 +1088,8 @@ DESCRIPTION: Color Compare Mask. Stalls the 2d/3d datapath until it is idle. Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 156 - Revision 1.3 March 30, 2008 +Proprietary 163 + Revision 1.4 October 13, 2009 @@ -1146,8 +1146,8 @@ COLORFORMAT 24:21 0x6 3D destination color 06 - ARGB8888 © 2008 Advanced Micro Devices, Inc. -Proprietary 157 - Revision 1.3 March 30, 2008 +Proprietary 164 + Revision 1.4 October 13, 2009 @@ -1203,8 +1203,8 @@ RED_MASK1 6 0x1 mask bit for the red ch POSSIBLE VALUES: © 2008 Advanced Micro Devices, Inc. -Proprietary 158 - Revision 1.3 March 30, 2008 +Proprietary 165 + Revision 1.4 October 13, 2009 @@ -1259,8 +1259,8 @@ ALPHA_MASK3 15 0x1 mask bit for the alpha ch © 2008 Advanced Micro Devices, Inc. -Proprietary 159 - Revision 1.3 March 30, 2008 +Proprietary 166 + Revision 1.4 October 13, 2009 @@ -1314,8 +1314,8 @@ Field Name Bits Default Description RED 15:0 none red constant color in 0.10 fixed or FP16 format © 2008 Advanced Micro Devices, Inc. -Proprietary 160 - Revision 1.3 March 30, 2008 +Proprietary 167 + Revision 1.4 October 13, 2009 @@ -1372,8 +1372,8 @@ DC_FREE 3:2 0x0 Setting this bit inva written to memory. A purge is achieved by setting both © 2008 Advanced Micro Devices, Inc. -Proprietary 161 - Revision 1.3 March 30, 2008 +Proprietary 168 + Revision 1.4 October 13, 2009 @@ -1419,13 +1419,13 @@ ROP 11:8 none ROP2 code for 3D fragm © 2008 Advanced Micro Devices, Inc. -Proprietary 162 - Revision 1.3 March 30, 2008 +Proprietary 169 + Revision 1.4 October 13, 2009 -10.3 Fog Registers +11.3 Fog Registers FG:FG_ALPHA_FUNC · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bd4 DESCRIPTION: Alpha Function @@ -1474,8 +1474,8 @@ ALP_OFF_EN 24 0x0 Alpha offset enable/di © 2008 Advanced Micro Devices, Inc. -Proprietary 163 - Revision 1.3 March 30, 2008 +Proprietary 170 + Revision 1.4 October 13, 2009 @@ -1530,8 +1530,8 @@ FN 2:1 0x0 Fog generation functi © 2008 Advanced Micro Devices, Inc. -Proprietary 164 - Revision 1.3 March 30, 2008 +Proprietary 171 + Revision 1.4 October 13, 2009 @@ -1574,13 +1574,13 @@ FACTOR 9:0 0x0 Constant fog factor; fi © 2008 Advanced Micro Devices, Inc. -Proprietary 165 - Revision 1.3 March 30, 2008 +Proprietary 172 + Revision 1.4 October 13, 2009 -10.4 Geometry Assembly Registers +11.4 Geometry Assembly Registers GA:GA_COLOR_CONTROL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4278 DESCRIPTION: Specifies per RGB or Alpha shading method. @@ -1629,8 +1629,8 @@ RGB3_SHADING 13:12 0x0 Specifies solid, flat 02 - Gouraud shading © 2008 Advanced Micro Devices, Inc. -Proprietary 166 - Revision 1.3 March 30, 2008 +Proprietary 173 + Revision 1.4 October 13, 2009 @@ -1686,8 +1686,8 @@ TEX3_SHADING_PS3 7:6 0x0 Specifies undefined(0) TEX4_SHADING_PS3 9:8 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture. © 2008 Advanced Micro Devices, Inc. -Proprietary 167 - Revision 1.3 March 30, 2008 +Proprietary 174 + Revision 1.4 October 13, 2009 @@ -1742,8 +1742,8 @@ COLOR0_TEX_OVERRIDE 25:22 0x0 Specifies if each colo which one. © 2008 Advanced Micro Devices, Inc. -Proprietary 168 - Revision 1.3 March 30, 2008 +Proprietary 175 + Revision 1.4 October 13, 2009 @@ -1799,8 +1799,8 @@ REG_READWRITE 2 0x0 R520+: When set, GA su POSSIBLE VALUES: © 2008 Advanced Micro Devices, Inc. -Proprietary 169 - Revision 1.3 March 30, 2008 +Proprietary 176 + Revision 1.4 October 13, 2009 @@ -1856,8 +1856,8 @@ COLOR_RED 31:0 0x0 FP20 format for red fil © 2008 Advanced Micro Devices, Inc. -Proprietary 170 - Revision 1.3 March 30, 2008 +Proprietary 177 + Revision 1.4 October 13, 2009 @@ -1907,8 +1907,8 @@ PIPE0_RS_IDLE 23 0x0 Idle status of physical © 2008 Advanced Micro Devices, Inc. -Proprietary 171 - Revision 1.3 March 30, 2008 +Proprietary 178 + Revision 1.4 October 13, 2009 @@ -1964,8 +1964,8 @@ LINE_RESET 1:0 0x0 Specify type of reset © 2008 Advanced Micro Devices, Inc. -Proprietary 172 - Revision 1.3 March 30, 2008 +Proprietary 179 + Revision 1.4 October 13, 2009 @@ -2020,8 +2020,8 @@ GA:GA_POINT_S1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4208 DESCRIPTION: S Texture Coordinate of Vertex 2 for Point texture stuffing (URC) © 2008 Advanced Micro Devices, Inc. -Proprietary 173 - Revision 1.3 March 30, 2008 +Proprietary 180 + Revision 1.4 October 13, 2009 @@ -2077,8 +2077,8 @@ FRONT_PTYPE 6:4 0x0 Specifies how to rende 03 - Reserved 3 - 7. © 2008 Advanced Micro Devices, Inc. -Proprietary 174 - Revision 1.3 March 30, 2008 +Proprietary 181 + Revision 1.4 October 13, 2009 @@ -2134,8 +2134,8 @@ COLOR_BLUE 31:16 0x0 Component blue value. GA:GA_SOLID_RG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x427c © 2008 Advanced Micro Devices, Inc. -Proprietary 175 - Revision 1.3 March 30, 2008 +Proprietary 182 + Revision 1.4 October 13, 2009 @@ -2191,13 +2191,13 @@ CLAMP 17 0x0 POSSIBLE VALUES: © 2008 Advanced Micro Devices, Inc. -Proprietary 176 - Revision 1.3 March 30, 2008 +Proprietary 183 + Revision 1.4 October 13, 2009 -10.5 Graphics Backend Registers +11.5 Graphics Backend Registers GB:GB_AA_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4020 DESCRIPTION: Specifies the graphics pipeline configuration for antialiasing. @@ -2247,8 +2247,8 @@ STENCIL_AUTO 5:4 0x0 Specifies if the auto d 02 - Force 0 into dzy low bit. © 2008 Advanced Micro Devices, Inc. -Proprietary 177 - Revision 1.3 March 30, 2008 +Proprietary 184 + Revision 1.4 October 13, 2009 @@ -2305,8 +2305,8 @@ TEX6_SOURCE 29:28 0x0 Specifies the sources texture. © 2008 Advanced Micro Devices, Inc. -Proprietary 178 - Revision 1.3 March 30, 2008 +Proprietary 185 + Revision 1.4 October 13, 2009 @@ -2362,8 +2362,8 @@ RS_CFIFO_SIZE 9:8 0x0 Size of ras input FIFO © 2008 Advanced Micro Devices, Inc. -Proprietary 179 - Revision 1.3 March 30, 2008 +Proprietary 186 + Revision 1.4 October 13, 2009 @@ -2417,8 +2417,8 @@ RS_HIGHWATER_TEX 23:18 0x0 High water mark for RS © 2008 Advanced Micro Devices, Inc. -Proprietary 180 - Revision 1.3 March 30, 2008 +Proprietary 187 + Revision 1.4 October 13, 2009 @@ -2472,8 +2472,8 @@ GB:GB_PIPE_SELECT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x402c DESCRIPTION: Selects which of 4 pipes are active. © 2008 Advanced Micro Devices, Inc. -Proprietary 181 - Revision 1.3 March 30, 2008 +Proprietary 188 + Revision 1.4 October 13, 2009 @@ -2528,8 +2528,8 @@ W_SELECT 4 0x0 Specifies source for o FOG_STUFF_ENABLE 5 0x0 Controls enabling of fog stuffing into texture coordinate. © 2008 Advanced Micro Devices, Inc. -Proprietary 182 - Revision 1.3 March 30, 2008 +Proprietary 189 + Revision 1.4 October 13, 2009 @@ -2585,8 +2585,8 @@ SUPER_SIZE 8:6 0x0 Specifies number of ti 07 - 128 tiles (two 8x8 : ST-A,B). © 2008 Advanced Micro Devices, Inc. -Proprietary 183 - Revision 1.3 March 30, 2008 +Proprietary 190 + Revision 1.4 October 13, 2009 @@ -2641,8 +2641,8 @@ Z_EXTENDED 24 0x0 Support for extended s POSSIBLE VALUES: © 2008 Advanced Micro Devices, Inc. -Proprietary 184 - Revision 1.3 March 30, 2008 +Proprietary 191 + Revision 1.4 October 13, 2009 @@ -2665,15 +2665,247 @@ Z_PEQ_SIZE 0 0x0 Specifies the z plane e +GB:PS3_ENABLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4118 +DESCRIPTION: PS3 mode enable register +Field Name Bits Default Description +PS3_MODE 0 0x0 When reset (default), follows R300/PS2 mode; when set, + allows for new ps3 mode. + + POSSIBLE VALUES: + 00 - Default PS2 mode + 01 - New PS3 mode + + +GB:PS3_TEX_SOURCE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4120 +DESCRIPTION: Specifies source for texture components in PS3 mode +Field Name Bits Default Description +TEX0_SOURCE 1:0 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX1_SOURCE 3:2 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + +© 2008 Advanced Micro Devices, Inc. +Proprietary 192 + Revision 1.4 October 13, 2009 + + + + + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX2_SOURCE 5:4 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX3_SOURCE 7:6 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX4_SOURCE 9:8 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX5_SOURCE 11:10 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX6_SOURCE 13:12 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX7_SOURCE 15:14 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 193 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX8_SOURCE 17:16 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX9_SOURCE 19:18 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). + + +GB:PS3_VTX_FMT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x411c +DESCRIPTION: PS3 vertex format register +Field Name Bits Default Description +TEX_0_COMP_CNT 2:0 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_1_COMP_CNT 5:3 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 194 + Revision 1.4 October 13, 2009 + + + + + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_2_COMP_CNT 8:6 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_3_COMP_CNT 11:9 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_4_COMP_CNT 14:12 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_5_COMP_CNT 17:15 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_6_COMP_CNT 20:18 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + © 2008 Advanced Micro Devices, Inc. -Proprietary 185 - Revision 1.3 March 30, 2008 +Proprietary 195 + Revision 1.4 October 13, 2009 + + + + + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_7_COMP_CNT 23:21 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_8_COMP_CNT 26:24 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_9_COMP_CNT 29:27 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_10_COMP_CNT 31:30 0x0 How many active components (0,2,3,4) are in texture 10. + POSSIBLE VALUES: + 00 - Not active + 01 - 2 component (GA/SU) + 02 - 3 component (GA/SU) + 03 - 4 component (GA/SU) + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 196 + Revision 1.4 October 13, 2009 -10.6 Rasterizer Registers + +11.6 Rasterizer Registers RS:RS_COUNT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4300 DESCRIPTION: This register specifies the rasterizer input packet configuration @@ -2719,15 +2951,15 @@ TEX_ADJ 25 0x0 Specifies whether to s POSSIBLE VALUES: 00 - Sample texture coordinates at real pixel centers - 01 - Sample texture coordinates at adjusted pixel © 2008 Advanced Micro Devices, Inc. -Proprietary 186 - Revision 1.3 March 30, 2008 +Proprietary 197 + Revision 1.4 October 13, 2009 + 01 - Sample texture coordinates at adjusted pixel centers W_CN 26 0x0 Specifies that the rasterizer should output w @@ -2776,15 +3008,15 @@ COL_FMT 30:27 0x0 Specifies the format o 02 - Three components (R,G,B,1) 04 - One component (0,0,0,A) 05 - Zero components (0,0,0,0) - 06 - Zero components (0,0,0,1) © 2008 Advanced Micro Devices, Inc. -Proprietary 187 - Revision 1.3 March 30, 2008 +Proprietary 198 + Revision 1.4 October 13, 2009 + 06 - Zero components (0,0,0,1) 08 - One component (1,1,1,A) 09 - Zero components (1,1,1,0) 10 - Zero components (1,1,1,1) @@ -2801,13 +3033,13 @@ OFFSET_EN 31 0x0 Enable application of the © 2008 Advanced Micro Devices, Inc. -Proprietary 188 - Revision 1.3 March 30, 2008 +Proprietary 199 + Revision 1.4 October 13, 2009 -10.7 Clipping Registers +11.7 Clipping Registers SC:SC_CLIP_0_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43b0 DESCRIPTION: OpenGL Clip rectangles Field Name Bits Default Description @@ -2856,8 +3088,8 @@ SC:SC_CLIP_3_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43c8 Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 189 - Revision 1.3 March 30, 2008 +Proprietary 200 + Revision 1.4 October 13, 2009 @@ -2915,8 +3147,8 @@ ER_TRI 4:0 0x0 Edge rules for triangl 12 - L-out,R-out,HT-in,HB-in © 2008 Advanced Micro Devices, Inc. -Proprietary 190 - Revision 1.3 March 30, 2008 +Proprietary 201 + Revision 1.4 October 13, 2009 @@ -2976,8 +3208,8 @@ ER_POINT 9:5 0x0 Edge rules for triangles 20 - T-out,B-in,VL-in,VR-in © 2008 Advanced Micro Devices, Inc. -Proprietary 191 - Revision 1.3 March 30, 2008 +Proprietary 202 + Revision 1.4 October 13, 2009 @@ -3037,8 +3269,8 @@ ER_LINE_LR 14:10 0x0 Edge rules for triangl 28 - T-out,B-out,VL-in,VR-in © 2008 Advanced Micro Devices, Inc. -Proprietary 192 - Revision 1.3 March 30, 2008 +Proprietary 203 + Revision 1.4 October 13, 2009 @@ -3097,8 +3329,8 @@ ER_LINE_TB 24:20 0x0 Edge rules for triangl bottom edge is in, bit 1 specifies whether a sample on a © 2008 Advanced Micro Devices, Inc. -Proprietary 193 - Revision 1.3 March 30, 2008 +Proprietary 204 + Revision 1.4 October 13, 2009 @@ -3158,8 +3390,8 @@ ER_LINE_BT 29:25 0x0 Edge rules for triangl © 2008 Advanced Micro Devices, Inc. -Proprietary 194 - Revision 1.3 March 30, 2008 +Proprietary 205 + Revision 1.4 October 13, 2009 @@ -3216,8 +3448,8 @@ HZ_MAX 1 0x0 Specifies whether to co HZ_ADJ 4:2 0x0 Specifies adjustment to get added or subtracted from © 2008 Advanced Micro Devices, Inc. -Proprietary 195 - Revision 1.3 March 30, 2008 +Proprietary 206 + Revision 1.4 October 13, 2009 @@ -3272,13 +3504,13 @@ SCREENDOOR 23:0 0x0 Screen door sample mas © 2008 Advanced Micro Devices, Inc. -Proprietary 196 - Revision 1.3 March 30, 2008 +Proprietary 207 + Revision 1.4 October 13, 2009 -10.8 Setup Unit Registers +11.8 Setup Unit Registers SU:SU_CULL_MODE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42b8 DESCRIPTION: Culling Enables @@ -3328,8 +3560,8 @@ OFFSET 31:0 0x0 Specifies polygon offs © 2008 Advanced Micro Devices, Inc. -Proprietary 197 - Revision 1.3 March 30, 2008 +Proprietary 208 + Revision 1.4 October 13, 2009 @@ -3385,8 +3617,8 @@ SCALE 31:0 0x0 Specifies polygon offse 1/16) © 2008 Advanced Micro Devices, Inc. -Proprietary 198 - Revision 1.3 March 30, 2008 +Proprietary 209 + Revision 1.4 October 13, 2009 @@ -3439,8 +3671,8 @@ T1C1 5 0x0 tNcM -- Enable texture 00 - Disable cylindrical wrapping. © 2008 Advanced Micro Devices, Inc. -Proprietary 199 - Revision 1.3 March 30, 2008 +Proprietary 210 + Revision 1.4 October 13, 2009 @@ -3496,8 +3728,8 @@ T3C1 13 0x0 tNcM -- Enable texture wr 01 - Enable cylindrical wrapping. © 2008 Advanced Micro Devices, Inc. -Proprietary 200 - Revision 1.3 March 30, 2008 +Proprietary 211 + Revision 1.4 October 13, 2009 @@ -3553,8 +3785,8 @@ T5C1 21 0x0 tNcM -- Enable texture wr T5C2 22 0x0 tNcM -- Enable texture wrapping on component M © 2008 Advanced Micro Devices, Inc. -Proprietary 201 - Revision 1.3 March 30, 2008 +Proprietary 212 + Revision 1.4 October 13, 2009 @@ -3610,8 +3842,8 @@ T7C2 30 0x0 tNcM -- Enable texture wr (S,T,R,Q) of texture N. © 2008 Advanced Micro Devices, Inc. -Proprietary 202 - Revision 1.3 March 30, 2008 +Proprietary 213 + Revision 1.4 October 13, 2009 @@ -3634,44 +3866,107 @@ Field Name Bits Default Description T9C0 0 0x0 tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N. - POSSIBLE VALUES: - 00 - Disable cylindrical wrapping. - 01 - Enable cylindrical wrapping. + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. T9C1 1 0x0 tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N. - POSSIBLE VALUES: - 00 - Disable cylindrical wrapping. - 01 - Enable cylindrical wrapping. + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. T9C2 2 0x0 tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N. + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T9C3 3 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C0 4 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C1 5 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 214 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C2 6 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C3 7 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. + + + +SU:SU_TEX_WRAP_PS3 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4114 +DESCRIPTION: Specifies texture wrapping for new PS3 textures. +Field Name Bits Default Description +T9C0 0 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + POSSIBLE VALUES: 00 - Disable cylindrical wrapping. 01 - Enable cylindrical wrapping. -T9C3 3 0x0 tNcM -- Enable texture wrapping on component M +T9C1 1 0x0 tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N. POSSIBLE VALUES: 00 - Disable cylindrical wrapping. 01 - Enable cylindrical wrapping. -T8C0 4 0x0 tNcM -- Enable texture wrapping on component M +T9C2 2 0x0 tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N. POSSIBLE VALUES: 00 - Disable cylindrical wrapping. 01 - Enable cylindrical wrapping. -T8C1 5 0x0 tNcM -- Enable texture wrapping on component M +T9C3 3 0x0 tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N. + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + © 2008 Advanced Micro Devices, Inc. -Proprietary 203 - Revision 1.3 March 30, 2008 +Proprietary 215 + Revision 1.4 October 13, 2009 + 01 - Enable cylindrical wrapping. +T8C0 4 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C1 5 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + POSSIBLE VALUES: 00 - Disable cylindrical wrapping. 01 - Enable cylindrical wrapping. @@ -3692,13 +3987,13 @@ T8C3 7 0x0 tNcM -- Enable texture wra © 2008 Advanced Micro Devices, Inc. -Proprietary 204 - Revision 1.3 March 30, 2008 +Proprietary 216 + Revision 1.4 October 13, 2009 -10.9 Texture Registers +11.9 Texture Registers TX:TX_BORDER_COLOR_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x45c0-0x45fc DESCRIPTION: Border Color @@ -3747,8 +4042,8 @@ TEX_4_ENABLE 4 none Texture Map Enables. TEX_5_ENABLE 5 none Texture Map Enables. © 2008 Advanced Micro Devices, Inc. -Proprietary 205 - Revision 1.3 March 30, 2008 +Proprietary 217 + Revision 1.4 October 13, 2009 @@ -3802,8 +4097,8 @@ TEX_14_ENABLE 14 none Texture Map Enables. 00 - Disable, ARGB = 1,0,0,0 © 2008 Advanced Micro Devices, Inc. -Proprietary 206 - Revision 1.3 March 30, 2008 +Proprietary 218 + Revision 1.4 October 13, 2009 @@ -3860,8 +4155,8 @@ MAG_FILTER 10:9 none Filter used when textu 01 - Point © 2008 Advanced Micro Devices, Inc. -Proprietary 207 - Revision 1.3 March 30, 2008 +Proprietary 219 + Revision 1.4 October 13, 2009 @@ -3917,8 +4212,8 @@ LOD_BIAS 12:3 none (s4.5). Ranges from - measured in mipmap levels. Added to the signed, © 2008 Advanced Micro Devices, Inc. -Proprietary 208 - Revision 1.3 March 30, 2008 +Proprietary 220 + Revision 1.4 October 13, 2009 @@ -3973,8 +4268,8 @@ DESCRIPTION: Filter4 Kernel Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 209 - Revision 1.3 March 30, 2008 +Proprietary 221 + Revision 1.4 October 13, 2009 @@ -4030,8 +4325,8 @@ TXPITCH_EN 31 none Indicates when TXPITC TX:TX_FORMAT1_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x44c0-0x44fc © 2008 Advanced Micro Devices, Inc. -Proprietary 210 - Revision 1.3 March 30, 2008 +Proprietary 222 + Revision 1.4 October 13, 2009 @@ -4090,8 +4385,8 @@ SIGNED_COMP0 5 none Component filter shoul signed © 2008 Advanced Micro Devices, Inc. -Proprietary 211 - Revision 1.3 March 30, 2008 +Proprietary 223 + Revision 1.4 October 13, 2009 @@ -4148,8 +4443,8 @@ SEL_GREEN 17:15 none Specifies swizzling f 01 - Select Texture Component1. © 2008 Advanced Micro Devices, Inc. -Proprietary 212 - Revision 1.3 March 30, 2008 +Proprietary 224 + Revision 1.4 October 13, 2009 @@ -4206,8 +4501,8 @@ CACHE 31:27 none This field is ignored 08 - EIGHTH_REGION_0 © 2008 Advanced Micro Devices, Inc. -Proprietary 213 - Revision 1.3 March 30, 2008 +Proprietary 225 + Revision 1.4 October 13, 2009 @@ -4264,8 +4559,8 @@ SEL_FILTER4 19:18 none If filter4 is enabled 01 - Select Texture Component1. © 2008 Advanced Micro Devices, Inc. -Proprietary 214 - Revision 1.3 March 30, 2008 +Proprietary 226 + Revision 1.4 October 13, 2009 @@ -4311,13 +4606,13 @@ TXOFFSET 31:5 none 32-byte aligned pointe © 2008 Advanced Micro Devices, Inc. -Proprietary 215 - Revision 1.3 March 30, 2008 +Proprietary 227 + Revision 1.4 October 13, 2009 -10.10 Fragment Shader Registers +11.10 Fragment Shader Registers US:US_ALU_ALPHA_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xa800-0xaffc DESCRIPTION: ALU Alpha Instruction @@ -4368,8 +4663,8 @@ ALPHA_SWIZ_A 16:14 0x0 Specifies the channel © 2008 Advanced Micro Devices, Inc. -Proprietary 216 - Revision 1.3 March 30, 2008 +Proprietary 228 + Revision 1.4 October 13, 2009 @@ -4425,8 +4720,8 @@ OMOD 28:26 0x0 Specifies the output m 04 - Result / 2 © 2008 Advanced Micro Devices, Inc. -Proprietary 217 - Revision 1.3 March 30, 2008 +Proprietary 229 + Revision 1.4 October 13, 2009 @@ -4483,8 +4778,8 @@ ADDR0_REL 9 0x0 Specifies whether the implements relative addressing. © 2008 Advanced Micro Devices, Inc. -Proprietary 218 - Revision 1.3 March 30, 2008 +Proprietary 230 + Revision 1.4 October 13, 2009 @@ -4540,8 +4835,8 @@ ADDR2_REL 29 0x0 Specifies whether the POSSIBLE VALUES: © 2008 Advanced Micro Devices, Inc. -Proprietary 219 - Revision 1.3 March 30, 2008 +Proprietary 231 + Revision 1.4 October 13, 2009 @@ -4599,8 +4894,8 @@ RGB_ADDRD_REL 11 0x0 Specifies whether the © 2008 Advanced Micro Devices, Inc. -Proprietary 220 - Revision 1.3 March 30, 2008 +Proprietary 232 + Revision 1.4 October 13, 2009 @@ -4658,8 +4953,8 @@ RGB_MOD_C 24:23 0x0 Specifies the input mo 03 - NAB: Take negative absolute value of input © 2008 Advanced Micro Devices, Inc. -Proprietary 221 - Revision 1.3 March 30, 2008 +Proprietary 233 + Revision 1.4 October 13, 2009 @@ -4716,8 +5011,8 @@ RED_SWIZ_A 4:2 0x0 Specifies, per channel 05 - Half © 2008 Advanced Micro Devices, Inc. -Proprietary 222 - Revision 1.3 March 30, 2008 +Proprietary 234 + Revision 1.4 October 13, 2009 @@ -4774,8 +5069,8 @@ RED_SWIZ_B 17:15 0x0 Specifies, per channel 05 - Half © 2008 Advanced Micro Devices, Inc. -Proprietary 223 - Revision 1.3 March 30, 2008 +Proprietary 235 + Revision 1.4 October 13, 2009 @@ -4833,8 +5128,8 @@ TARGET 30:29 0x0 This specifies which ( © 2008 Advanced Micro Devices, Inc. -Proprietary 224 - Revision 1.3 March 30, 2008 +Proprietary 236 + Revision 1.4 October 13, 2009 @@ -4890,8 +5185,8 @@ ADDR1 17:10 0x0 Specifies the identit to 255 and specifies a location within the constant © 2008 Advanced Micro Devices, Inc. -Proprietary 225 - Revision 1.3 March 30, 2008 +Proprietary 237 + Revision 1.4 October 13, 2009 @@ -4948,8 +5243,8 @@ SRCP_OP 31:30 0x0 Specifies how the pre- 00 - 1.0-2.0*RGB0 © 2008 Advanced Micro Devices, Inc. -Proprietary 226 - Revision 1.3 March 30, 2008 +Proprietary 238 + Revision 1.4 October 13, 2009 @@ -5006,8 +5301,8 @@ RGB_PRED_INV 6 0x0 Specifies whether the p POSSIBLE VALUES: 00 - Normal predication © 2008 Advanced Micro Devices, Inc. -Proprietary 227 - Revision 1.3 March 30, 2008 +Proprietary 239 + Revision 1.4 October 13, 2009 @@ -5064,8 +5359,8 @@ ALPHA_WMASK 14 0x0 Specifies whether the 00 - NONE: Do not write register. © 2008 Advanced Micro Devices, Inc. -Proprietary 228 - Revision 1.3 March 30, 2008 +Proprietary 240 + Revision 1.4 October 13, 2009 @@ -5122,8 +5417,8 @@ ALPHA_PRED_INV 22 0x0 Specifies whether the © 2008 Advanced Micro Devices, Inc. -Proprietary 229 - Revision 1.3 March 30, 2008 +Proprietary 241 + Revision 1.4 October 13, 2009 @@ -5180,8 +5475,8 @@ OFFSET_ADDR 8:0 0x0 Specifies the offset t © 2008 Advanced Micro Devices, Inc. -Proprietary 230 - Revision 1.3 March 30, 2008 +Proprietary 242 + Revision 1.4 October 13, 2009 @@ -5236,8 +5531,8 @@ JUMP_GLOBAL 31 0x0 Specifies whether to i US:US_FC_BOOL_CONST · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4620 DESCRIPTION: Static Boolean Constants for Flow Control Branching Instructions. Quad-buffered. © 2008 Advanced Micro Devices, Inc. -Proprietary 231 - Revision 1.3 March 30, 2008 +Proprietary 243 + Revision 1.4 October 13, 2009 @@ -5294,8 +5589,8 @@ OP 2:0 0x0 Specifies the type of f but don`t pop the loop register if it jumps. © 2008 Advanced Micro Devices, Inc. -Proprietary 232 - Revision 1.3 March 30, 2008 +Proprietary 244 + Revision 1.4 October 13, 2009 @@ -5352,8 +5647,8 @@ B_OP0 25:24 0x0 The branch state opera decrement branch counter by B_POP_CNT for inactive © 2008 Advanced Micro Devices, Inc. -Proprietary 233 - Revision 1.3 March 30, 2008 +Proprietary 245 + Revision 1.4 October 13, 2009 @@ -5410,8 +5705,8 @@ TXDEPTH 25:22 0x0 POSSIBLE VALUES: © 2008 Advanced Micro Devices, Inc. -Proprietary 234 - Revision 1.3 March 30, 2008 +Proprietary 246 + Revision 1.4 October 13, 2009 @@ -5468,8 +5763,8 @@ ROUND_ADJ 20 0x0 POSSIBLE VALUES: © 2008 Advanced Micro Devices, Inc. -Proprietary 235 - Revision 1.3 March 30, 2008 +Proprietary 247 + Revision 1.4 October 13, 2009 @@ -5524,8 +5819,8 @@ SRC_Q_SWIZ 15:14 0x0 Specify which colour c POSSIBLE VALUES: 00 - Use R channel as Q coordinate © 2008 Advanced Micro Devices, Inc. -Proprietary 236 - Revision 1.3 March 30, 2008 +Proprietary 248 + Revision 1.4 October 13, 2009 @@ -5582,8 +5877,8 @@ DESCRIPTION: Additional texture addresses and swizzles for DX/DY inputs Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 237 - Revision 1.3 March 30, 2008 +Proprietary 249 + Revision 1.4 October 13, 2009 @@ -5639,8 +5934,8 @@ DY_ADDR_REL 23 0x0 Specifies whether the 00 - NONE: Do not modify source address © 2008 Advanced Micro Devices, Inc. -Proprietary 238 - Revision 1.3 March 30, 2008 +Proprietary 250 + Revision 1.4 October 13, 2009 @@ -5697,8 +5992,8 @@ INST 24:22 0x0 Specifies the operatio 04 - LODBIAS: Do texture lookup with lod bias © 2008 Advanced Micro Devices, Inc. -Proprietary 239 - Revision 1.3 March 30, 2008 +Proprietary 251 + Revision 1.4 October 13, 2009 @@ -5753,13 +6048,13 @@ W_SRC 2 0x0 Source for W © 2008 Advanced Micro Devices, Inc. -Proprietary 240 - Revision 1.3 March 30, 2008 +Proprietary 252 + Revision 1.4 October 13, 2009 -10.11 Vertex Registers +11.11 Vertex Registers VAP:VAP_ALT_NUM_VERTICES · [R/W] · 32 bits · Access: 32 · MMReg:0x2088 DESCRIPTION: Alternate Number of Vertices to allow > 16-bits of Vertex count @@ -5807,8 +6102,8 @@ PVS_NUM_SLOTS 3:0 0x0 Specifies the number memory for each vertex, but less parallel processing. © 2008 Advanced Micro Devices, Inc. -Proprietary 241 - Revision 1.3 March 30, 2008 +Proprietary 253 + Revision 1.4 October 13, 2009 @@ -5864,8 +6159,8 @@ MAX_MPS 19:16 0x0 Maximum number of MPs For A12, © 2008 Advanced Micro Devices, Inc. -Proprietary 242 - Revision 1.3 March 30, 2008 +Proprietary 254 + Revision 1.4 October 13, 2009 @@ -5921,8 +6216,8 @@ DATA_REGISTER 31:0 0x0 32-bit floating point v guard band. © 2008 Advanced Micro Devices, Inc. -Proprietary 243 - Revision 1.3 March 30, 2008 +Proprietary 255 + Revision 1.4 October 13, 2009 @@ -5975,8 +6270,8 @@ TEX_0_COMP_CNT 2:0 0x0 Number of words in text © 2008 Advanced Micro Devices, Inc. -Proprietary 244 - Revision 1.3 March 30, 2008 +Proprietary 256 + Revision 1.4 October 13, 2009 @@ -6033,8 +6328,8 @@ DATAPORT0 31:0 0x0 1st of 16 consecutive (master with mirrors) information. © 2008 Advanced Micro Devices, Inc. -Proprietary 245 - Revision 1.3 March 30, 2008 +Proprietary 257 + Revision 1.4 October 13, 2009 @@ -6092,8 +6387,8 @@ DATA_TYPE_0 3:0 0x0 The data type for eleme Sames as 2 FLOAT_4 but must use consecutive © 2008 Advanced Micro Devices, Inc. -Proprietary 246 - Revision 1.3 March 30, 2008 +Proprietary 258 + Revision 1.4 October 13, 2009 @@ -6149,8 +6444,8 @@ DESCRIPTION: Programmable Stream Control Extension Word 0 Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 247 - Revision 1.3 March 30, 2008 +Proprietary 259 + Revision 1.4 October 13, 2009 @@ -6204,8 +6499,8 @@ SGN_NORM_METHOD_8 17:16 0x0 See SGN_NORM_METHOD_0 © 2008 Advanced Micro Devices, Inc. -Proprietary 248 - Revision 1.3 March 30, 2008 +Proprietary 260 + Revision 1.4 October 13, 2009 @@ -6260,8 +6555,8 @@ VAP:VAP_PVS_FLOW_CNTL_ADDRS_[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x DESCRIPTION: Programmable Vertex Shader Flow Control Addresses Register 0 © 2008 Advanced Micro Devices, Inc. -Proprietary 249 - Revision 1.3 March 30, 2008 +Proprietary 261 + Revision 1.4 October 13, 2009 @@ -6319,8 +6614,8 @@ PVS_FC_LOOP_CNT_JMP_INST_0 31:16 0x0 This field has multiple VAP:VAP_PVS_FLOW_CNTL_ADDRS_UW_[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x2504- © 2008 Advanced Micro Devices, Inc. -Proprietary 250 - Revision 1.3 March 30, 2008 +Proprietary 262 + Revision 1.4 October 13, 2009 @@ -6377,8 +6672,8 @@ PVS_FC_OPC_0 1:0 0x0 This opcode fie © 2008 Advanced Micro Devices, Inc. -Proprietary 251 - Revision 1.3 March 30, 2008 +Proprietary 263 + Revision 1.4 October 13, 2009 @@ -6433,8 +6728,8 @@ VAP:VAP_PVS_VECTOR_INDX_REG · [R/W] · 32 bits · Access: 32 · MMReg:0x2200 © 2008 Advanced Micro Devices, Inc. -Proprietary 252 - Revision 1.3 March 30, 2008 +Proprietary 264 + Revision 1.4 October 13, 2009 @@ -6488,8 +6783,8 @@ TEX_ALPHA_SHADE_FUNC_4 17 0x0 Default = 0 © 2008 Advanced Micro Devices, Inc. -Proprietary 253 - Revision 1.3 March 30, 2008 +Proprietary 265 + Revision 1.4 October 13, 2009 @@ -6545,8 +6840,8 @@ PRIM_TYPE 3:0 0x0 Primitive Type [ Index5, Index4 ] © 2008 Advanced Micro Devices, Inc. -Proprietary 254 - Revision 1.3 March 30, 2008 +Proprietary 266 + Revision 1.4 October 13, 2009 @@ -6603,8 +6898,8 @@ MIN_INDX 23:0 0x0 If index to be fetched VAP:VAP_VPORT_XOFFSET · [R/W] · 32 bits · Access: 32 · MMReg:0x1d9c, MMReg:0x209c © 2008 Advanced Micro Devices, Inc. -Proprietary 255 - Revision 1.3 March 30, 2008 +Proprietary 267 + Revision 1.4 October 13, 2009 @@ -6658,8 +6953,8 @@ VPORT_X_OFFSET_ENA 1 0x0 Viewport Transform Offs VPORT_Y_SCALE_ENA 2 0x0 Viewport Transform Scale Enable for Y component VPORT_Y_OFFSET_ENA 3 0x0 Viewport Transform Offset Enable for Y component © 2008 Advanced Micro Devices, Inc. -Proprietary 256 - Revision 1.3 March 30, 2008 +Proprietary 268 + Revision 1.4 October 13, 2009 @@ -6714,8 +7009,8 @@ VC_FORCE_PREFETCH 5 0x0 Force Vertex Data Pre- VAP_VF_CNTL.PRIM_WALK is set to Vertex List © 2008 Advanced Micro Devices, Inc. -Proprietary 257 - Revision 1.3 March 30, 2008 +Proprietary 269 + Revision 1.4 October 13, 2009 @@ -6769,8 +7064,8 @@ VAP:VAP_VTX_STATE_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x2180 DESCRIPTION: VAP Vertex State Control Register © 2008 Advanced Micro Devices, Inc. -Proprietary 258 - Revision 1.3 March 30, 2008 +Proprietary 270 + Revision 1.4 October 13, 2009 @@ -6826,8 +7121,8 @@ DATA_REGISTER 31:0 0x0 BLND_WT_0 VAP:VAP_VTX_ST_CLR_[0-7]_A · [R/W] · 32 bits · Access: 32 · MMReg:0x232c-0x239c © 2008 Advanced Micro Devices, Inc. -Proprietary 259 - Revision 1.3 March 30, 2008 +Proprietary 271 + Revision 1.4 October 13, 2009 @@ -6883,8 +7178,8 @@ DATA_REGISTER 0 0x0 EDGE_FLAGS VAP:VAP_VTX_ST_END_OF_PKT · [W] · 32 bits · Access: 32 · MMReg:0x24ac © 2008 Advanced Micro Devices, Inc. -Proprietary 260 - Revision 1.3 March 30, 2008 +Proprietary 272 + Revision 1.4 October 13, 2009 @@ -6940,8 +7235,8 @@ DATA_REGISTER 31:0 0x0 NORM_1_Y VAP:VAP_VTX_ST_NORM_1_Z · [R/W] · 32 bits · Access: 32 · MMReg:0x2458 © 2008 Advanced Micro Devices, Inc. -Proprietary 261 - Revision 1.3 March 30, 2008 +Proprietary 273 + Revision 1.4 October 13, 2009 @@ -6997,8 +7292,8 @@ DATA_REGISTER 31:0 0x0 POS_0_Y_2 VAP:VAP_VTX_ST_POS_0_Y_3 · [W] · 32 bits · Access: 32 · MMReg:0x24a4 © 2008 Advanced Micro Devices, Inc. -Proprietary 262 - Revision 1.3 March 30, 2008 +Proprietary 274 + Revision 1.4 October 13, 2009 @@ -7054,8 +7349,8 @@ DATA_REGISTER 31:0 0x0 POS_1_Y VAP:VAP_VTX_ST_POS_1_Z · [R/W] · 32 bits · Access: 32 · MMReg:0x2448 © 2008 Advanced Micro Devices, Inc. -Proprietary 263 - Revision 1.3 March 30, 2008 +Proprietary 275 + Revision 1.4 October 13, 2009 @@ -7111,8 +7406,8 @@ DATA_REGISTER 31:0 0x0 TEX_0_S VAP:VAP_VTX_ST_TEX_[0-7]_T · [R/W] · 32 bits · Access: 32 · MMReg:0x23a4-0x2414 © 2008 Advanced Micro Devices, Inc. -Proprietary 264 - Revision 1.3 March 30, 2008 +Proprietary 276 + Revision 1.4 October 13, 2009 @@ -7160,13 +7455,13 @@ DATA_REGISTER 31:0 0x0 USR_CLR_R © 2008 Advanced Micro Devices, Inc. -Proprietary 265 - Revision 1.3 March 30, 2008 +Proprietary 277 + Revision 1.4 October 13, 2009 -10.12 Z Buffer Registers +11.12 Z Buffer Registers ZB:ZB_BW_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f1c @@ -7217,8 +7512,8 @@ ALUE to be equal to ZB_STENCILREFMASK.stencilref&ZB_STENCILREFMA © 2008 Advanced Micro Devices, Inc. -Proprietary 266 - Revision 1.3 March 30, 2008 +Proprietary 278 + Revision 1.4 October 13, 2009 @@ -7274,8 +7569,8 @@ SABLE 01 - Disable contiguous samples © 2008 Advanced Micro Devices, Inc. -Proprietary 267 - Revision 1.3 March 30, 2008 +Proprietary 279 + Revision 1.4 October 13, 2009 @@ -7331,8 +7626,8 @@ STENCIL_FRONT_BACK 4 0x0 When STENCIL_ENABLE is s registers determine the operation independent of the front/back face state of the quad. © 2008 Advanced Micro Devices, Inc. -Proprietary 268 - Revision 1.3 March 30, 2008 +Proprietary 280 + Revision 1.4 October 13, 2009 @@ -7387,8 +7682,8 @@ DEPTHMICROTILE 18:17 0x0 Specifies whether 00 - 32 byte cache line is linear © 2008 Advanced Micro Devices, Inc. -Proprietary 269 - Revision 1.3 March 30, 2008 +Proprietary 281 + Revision 1.4 October 13, 2009 @@ -7445,8 +7740,8 @@ DEPTHFORMAT 3:0 0x0 Specifies the format o 06 - RESERVED © 2008 Advanced Micro Devices, Inc. -Proprietary 270 - Revision 1.3 March 30, 2008 +Proprietary 282 + Revision 1.4 October 13, 2009 @@ -7502,8 +7797,8 @@ ZB:ZB_HIZ_WRINDEX · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f48 DESCRIPTION: Hierarchical Z Write Index Field Name Bits Default Description © 2008 Advanced Micro Devices, Inc. -Proprietary 271 - Revision 1.3 March 30, 2008 +Proprietary 283 + Revision 1.4 October 13, 2009 @@ -7559,8 +7854,8 @@ ZC_FREE 1 0x0 Setting this bit inval 00 - No effect © 2008 Advanced Micro Devices, Inc. -Proprietary 272 - Revision 1.3 March 30, 2008 +Proprietary 284 + Revision 1.4 October 13, 2009 @@ -7617,8 +7912,8 @@ STENCILFUNC 5:3 0x0 Specifies the stencil f © 2008 Advanced Micro Devices, Inc. -Proprietary 273 - Revision 1.3 March 30, 2008 +Proprietary 285 + Revision 1.4 October 13, 2009 @@ -7674,8 +7969,8 @@ ZERO_OUTPUT_MASK 27 0x0 Zeroes the zb coverage © 2008 Advanced Micro Devices, Inc. -Proprietary 274 - Revision 1.3 March 30, 2008 +Proprietary 286 + Revision 1.4 October 13, 2009 @@ -7690,4 +7985,4 @@ ZTOP 0 0x0 POSSIBLE VALUES: © 2008 Advanced Micro Devices, Inc. -Proprietary 275 +Proprietary 287 diff --git a/doc2xml/radeonreg.py b/doc2xml/radeonreg.py index 1d05805..a23aeaa 100755 --- a/doc2xml/radeonreg.py +++ b/doc2xml/radeonreg.py @@ -364,13 +364,13 @@ def ReferenceEnums(regs): # read the pdf dumps r300regs = FormatPDFDump(ReadPDFDump('R3xx_3D_Registers.txt')) -r500regs = FormatPDFDump(ReadPDFDump('R5xx_Acceleration_v1.3.txt')) +r500regs = FormatPDFDump(ReadPDFDump('R5xx_Acceleration_v1.4.txt')) # cat <txtfile> | grep · | wc -l # this gives the exact number of registry entries. # confirm that we caught ALL registers if len(r300regs) != 207: print 'len(r300regs) == %d, expected 207' % len(r300regs) -if len(r500regs) != 278: print 'len(r500regs) == %d, expected 278' % len(r500regs) +if len(r500regs) != 278: print 'len(r500regs) == %d, expected 282' % len(r500regs) # split out shared registers regs_both,regs_r300,regs_r500 = CompareRegs(r300regs, r500regs) |