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diff --git a/doc2xml/R5xx_Acceleration_v1.4.txt b/doc2xml/R5xx_Acceleration_v1.4.txt new file mode 100644 index 0000000..beb5524 --- /dev/null +++ b/doc2xml/R5xx_Acceleration_v1.4.txt @@ -0,0 +1,7988 @@ + Revision 1.4 October 13, 2009 + + + + + 11. Registers + +11.1 Command Processor Registers + + +CP:CP_CSQ2_STAT · [R] · 32 bits · Access: 8/16/32 · MMReg:0x7fc +DESCRIPTION: (RO) Command Stream Indirect Queue 2 Status +Field Name Bits Default Description +CSQ_WPTR_INDIRECT 9:0 none Current Write Pointer into the Indirect Queue. Default = + 0. +CSQ_RPTR_INDIRECT2 19:10 none Current Read Pointer into the Indirect Queue. Default = + 0. +CSQ_WPTR_INDIRECT2 29:20 none Current Write Pointer into the Indirect Queue. Default = + 0. + + + +CP:CP_CSQ_ADDR · [W] · 32 bits · Access: 8/16/32 · MMReg:0x7f0 +DESCRIPTION: (WO) Command Stream Queue Address +Field Name Bits Default Description +CSQ_ADDR 11:2 none Address into the Command Stream Queue which is to be + read from. Used for debug, to read the contents of the + Command Stream Queue. + + + +CP:CP_CSQ_APER_INDIRECT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x1300-0x13fc +DESCRIPTION: IB1 Aperture map in RBBM - PIO +Field Name Bits Default Description +CP_CSQ_APER_INDIRECT 31:0 none IB1 Aperture +(Access: W) + + + +CP:CP_CSQ_APER_INDIRECT2 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x1200-0x12fc +DESCRIPTION: IB2 Aperture map in RBBM - PIO +Field Name Bits Default Description +CP_CSQ_APER_INDIRECT2 31:0 none IB2 Aperture +(Access: W) + + + +CP:CP_CSQ_APER_PRIMARY · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x1000-0x11fc +DESCRIPTION: Primary Aperture map in RBBM - PIO +Field Name Bits Default Description + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 145 + Revision 1.4 October 13, 2009 + + + + +CP_CSQ_APER_PRIMARY 31:0 none Primary Aperture +(Access: W) + + + +CP:CP_CSQ_AVAIL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7b8 +DESCRIPTION: Command Stream Queue Available Counts +Field Name Bits Default Description +CSQ_CNT_PRIMARY 9:0 none Count of available dwords in the queue for the Primary +(Access: R) Stream. Read Only. +CSQ_CNT_INDIRECT 19:10 none Count of available dwords in the queue for the Indirect +(Access: R) Stream. Read Only. +CSQ_CNT_INDIRECT2 29:20 none Count of available dwords in the queue for the Indirect +(Access: R) Stream. Read Only. + + + +CP:CP_CSQ_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x740 +DESCRIPTION: Command Stream Queue Control +Field Name Bits Default Description +CSQ_MODE 31:28 0x0 Command Stream Queue Mode. Controls whether each + command stream is enabled, and whether it is in push + mode (Programmed I/O), or pull mode (Bus-Master). + Encodings are chosen to be compatible with Rage128. 0= + Primary Disabled, Indirect Disabled. 1= Primary PIO, + Indirect Disabled. 2= Primary BM, Indirect Disabled. + 3,5,7= Primary PIO, Indirect BM. 4,6,8= Primary BM, + Indirect BM. 9-14= Reserved. 15= Primary PIO, Indirect + PIO Default = 0 + + + +CP:CP_CSQ_DATA · [R] · 32 bits · Access: 8/16/32 · MMReg:0x7f4 +DESCRIPTION: (RO) Command Stream Queue Data +Field Name Bits Default Description +CSQ_DATA 31:0 none Data from the Command Stream Queue, from location + pointed to by the CP_CSQ_ADDR register. Used for + debug, to read the contents of the Command Stream + Queue. + + + +CP:CP_CSQ_MODE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x744 +DESCRIPTION: Alternate Command Stream Queue Control +Field Name Bits Default Description +INDIRECT2_START 6:0 none Start location of Indirect Queue #2 in the command + cache. This value also sets the size in double octwords of + the Indirect Queue #1 cache that will reside in locations + INDIRECT1_START to (INDIRECT2_START - 1). The + Indirect Queue #2 will reside in locations + +© 2008 Advanced Micro Devices, Inc. +Proprietary 146 + Revision 1.4 October 13, 2009 + + + + + INDIRECT2_START to 0x5f. The minimum size of the + Indirect Queues must be at least twice the MAX_FETCH + size as programmed in the CP_RB_CNTL register. +INDIRECT1_START 14:8 none Start location of Indirect Queue #1 in the command + cache. This value is also the size in double octwords of + the Primary Queue cache that will reside in locations 0 to + (INDIRECT1_START - 1). The minimum size of the + Primary Queue cache must be at least twice the + MAX_FETCH size as programmed in the + CP_RB_CNTL register. +CSQ_INDIRECT2_MODE 26 0x0 0=>PIO, 1=>BM +CSQ_INDIRECT2_ENABLE 27 0x0 Enables Indirect Buffer #2. If this bit is set, the + CP_CSQ_MODE register overrides the operation of the + CSQ_MODE variable in the CP_CSQ_CNTL register. +CSQ_INDIRECT1_MODE 28 0x0 0=>PIO, 1=>BM +CSQ_INDIRECT1_ENABLE 29 0x0 Enables Indirect Buffer #1. If this bit is set, the + CP_CSQ_MODE register overrides the operation of the + CSQ_MODE variable in the CP_CSQ_CNTL register. +CSQ_PRIMARY_MODE 30 0x0 0=>PIO, 1=>BM +CSQ_PRIMARY_ENABLE 31 0x0 Enables Primary Buffer. If this bit is set, the + CP_CSQ_MODE register overrides the operation of the + CSQ_MODE variable in the CP_CSQ_CNTL register. + + + +CP:CP_CSQ_STAT · [R] · 32 bits · Access: 8/16/32 · MMReg:0x7f8 +DESCRIPTION: (RO) Command Stream Queue Status +Field Name Bits Default Description +CSQ_RPTR_PRIMARY 9:0 none Current Read Pointer into the Primary Queue. Default = + 0. +CSQ_WPTR_PRIMARY 19:10 none Current Write Pointer into the Primary Queue. Default = + 0. +CSQ_RPTR_INDIRECT 29:20 none Current Read Pointer into the Indirect Queue. Default = + 0. + + + +CP:CP_GUI_COMMAND · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x728 +DESCRIPTION: Command for PIO GUI DMAs +Field Name Bits Default Description +CP_GUI_COMMAND 31:0 none Command for PIO DMAs to the GUI DMA. Only + DWORD access is allowed to this register. + + + +CP:CP_GUI_DST_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x724 +DESCRIPTION: Destination Address for PIO GUI DMAs +Field Name Bits Default Description + +© 2008 Advanced Micro Devices, Inc. +Proprietary 147 + Revision 1.4 October 13, 2009 + + + + +CP_GUI_DST_ADDR 31:0 none Destination address for PIO DMAs to the GUI DMA. + Only DWORD access is allowed to this register. + + + +CP:CP_GUI_SRC_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x720 +DESCRIPTION: Source Address for PIO GUI DMAs +Field Name Bits Default Description +CP_GUI_SRC_ADDR 31:0 none Source address for PIO DMAs to the GUI DMA. Only + DWORD access is allowed to this register. + + + +CP:CP_IB2_BASE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x730 +DESCRIPTION: Indirect Buffer 2 Base +Field Name Bits Default Description +IB2_BASE 31:2 none Indirect Buffer 2 Base. Address of the beginning of the + indirect buffer. Only DWORD access is allowed to this + register. + + + +CP:CP_IB2_BUFSZ · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x734 +DESCRIPTION: Indirect Buffer 2 Size +Field Name Bits Default Description +IB2_BUFSZ 22:0 0x0 Indirect Buffer 2 Size. This size is expressed in dwords. + This field is an initiator to begin fetching commands + from the Indirect Buffer. Only DWORD access is + allowed to this register. Default = 0 + + + +CP:CP_IB_BASE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x738 +DESCRIPTION: Indirect Buffer Base +Field Name Bits Default Description +IB_BASE 31:2 none Indirect Buffer Base. Address of the beginning of the + indirect buffer. Only DWORD access is allowed to this + register. + + + +CP:CP_IB_BUFSZ · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x73c +DESCRIPTION: Indirect Buffer Size +Field Name Bits Default Description +IB_BUFSZ 22:0 0x0 Indirect Buffer Size. This size is expressed in dwords. + This field is an initiator to begin fetching commands + from the Indirect Buffer. Only DWORD access is + allowed to this register. Default = 0 + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 148 + Revision 1.4 October 13, 2009 + + + + +CP:CP_ME_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7d0 +DESCRIPTION: Micro Engine Control +Field Name Bits Default Description +ME_STAT 15:0 none Status of MicroEngine internal registers. This value +(Access: R) depends on the current value of the ME_STATMUX + field. Read Only. +ME_STATMUX 20:16 0x0 Selects which status is to be returned on the ME_STAT + field. +ME_BUSY 29 none Busy indicator for the MicroEngine. 0 = MicroEngine +(Access: R) not busy. 1 = MicroEngine is active. Read Only. +ME_MODE 30 0x1 Run-Mode of MicroEngine. 0 = Single-Step Mode. 1 = + Free-running Mode. Default = 1 +ME_STEP 31 0x0 Step the MicroEngine by one instruction. Writing a `1` to +(Access: W) this field causes the MicroEngine to step by one + instruction, if and only if the ME_MODE bit is a `0`. + Write Only. + + + +CP:CP_ME_RAM_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7d4 +DESCRIPTION: MicroEngine RAM Address +Field Name Bits Default Description +ME_RAM_ADDR 7:0 none MicroEngine RAM Address (Write Mode) Writing this +(master with mirrors) register puts the RAM access circuitry into `Write Mode` + , which allows the address to auto-increment as data is + written into the RAM. + + + +CP:CP_ME_RAM_DATAH · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7dc +DESCRIPTION: MicroEngine RAM Data High +Field Name Bits Default Description +ME_RAM_DATAH 7:0 none MicroEngine RAM Data High Used to load the + MicroEngine RAM. + + + +CP:CP_ME_RAM_DATAL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7e0 +DESCRIPTION: MicroEngine RAM Data Low +Field Name Bits Default Description +ME_RAM_DATAL 31:0 none MicroEngine RAM Data Low Used to load the + MicroEngine RAM. + + + +CP:CP_ME_RAM_RADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7d8 +DESCRIPTION: MicroEngine RAM Read Address +Field Name Bits Default Description + +© 2008 Advanced Micro Devices, Inc. +Proprietary 149 + Revision 1.4 October 13, 2009 + + + + +ME_RAM_RADDR 7:0 none MicroEngine RAM Address (Read Mode) Writing +(mirror of this register puts the RAM access circuitry into `Read +CP_ME_RAM_ADDR:ME_RAM_ADDR) Mode` , which allows the address to auto-increment +(Access: W) as data is read from the RAM. Write Only. + + + +CP:CP_RB_BASE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x700 +DESCRIPTION: Ring Buffer Base +Field Name Bits Default Description +RB_BASE 31:2 none Ring Buffer Base. Address of the beginning of the ring + buffer. + + + +CP:CP_RB_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x704 +DESCRIPTION: Ring Buffer Control +Field Name Bits Default Description +RB_BUFSZ 5:0 0x0 Ring Buffer Size. This size is expressed in log2 of the + actual size. Values 0 and 1 are clamped to an 8 DWORD + ring buffer. A value of 2 to 22 will give a ring buffer: + 2^(RB_BUFSZ+1). Values greater than 22 will clamp to + 22. Default = 0 +RB_BLKSZ 13:8 0x0 Ring Buffer Block Size. This defines the number of + quadwords that the Command Processor will read + between updates to the host`s copy of the Read Pointer. + This size is expressed in log2 of the actual size (in 64-bit + quadwords). For example, for a block of 1024 + quadwords, you would program this field to 10(decimal). + Default = 0 +BUF_SWAP 17:16 0x0 Endian Swap Control for Ring Buffer and Indirect + Buffer. Only affects the chip behavior if the buffer + resides in system memory. 0 = No swap 1 = 16-bit swap: + 0xAABBCCDD becomes 0xBBAADDCC 2 = 32-bit + swap: 0xAABBCCDD becomes 0xDDCCBBAA 3 = + Half-dword swap: 0xAABBCCDD becomes + 0xCCDDAABB Default = 0 +MAX_FETCH 19:18 0x0 Maximum Fetch Size for any read request that the CP + makes to memory. 0 = 1 double octword. (32 bytes) 1 = + 2 double octwords. (64 bytes) 2 = 4 double octwords. + (128 bytes) 3 = 8 double octwords. (256 bytes). Default + =0 +RB_NO_UPDATE 27 0x0 Ring Buffer No Write to Read Pointer 0= Write to Host`s + copy of Read Pointer in system memory. 1= Do not write + to Host`s copy of Read pointer. The purpose of this + control bit is to have a fall-back position if the bus- + mastered write to system memory doesn`t work, in which + case the driver will have to read the Graphics + Controller`s copy of the Read Pointer directly, with some + performance penalty. Default = 0 + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 150 + Revision 1.4 October 13, 2009 + + + + +RB_RPTR_WR_ENA 31 0x0 Ring Buffer Read Pointer Write Transfer Enable. When + set the contents of the CP_RB_RPTR_WR register is + transferred to the active read pointer (CP_RB_RPTR) + whenever the CP_RB_WPTR register is written. Default + =0 + + + +CP:CP_RB_RPTR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x710 +DESCRIPTION: Ring Buffer Read Pointer Address (RO) +Field Name Bits Default Description +RB_RPTR 22:0 none Ring Buffer Read Pointer. This is an index (in dwords) +(Access: R) of the current element being read from the ring buffer. + + + +CP:CP_RB_RPTR_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x70c +DESCRIPTION: Ring Buffer Read Pointer Address +Field Name Bits Default Description +RB_RPTR_SWAP 1:0 0x0 Swap control of the reported read pointer address. See + CP_RB_CNTL.BUF_SWAP for the encoding. +RB_RPTR_ADDR 31:2 0x0 Ring Buffer Read Pointer Address. Address of the Host`s + copy of the Read Pointer. CP_RB_RPTR (RO) Ring + Buffer Read Pointer + + + +CP:CP_RB_RPTR_WR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x71c +DESCRIPTION: Writable Ring Buffer Read Pointer Address +Field Name Bits Default Description +RB_RPTR_WR 22:0 0x0 Writable Ring Buffer Read Pointer. Writable for + updating the RB_RPTR after an ACPI. + + + +CP:CP_RB_WPTR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x714 +DESCRIPTION: (RO) Ring Buffer Write Pointer +Field Name Bits Default Description +RB_WPTR 22:0 0x0 Ring Buffer Write Pointer. This is an index (in dwords) + of the last known element to be written to the ring buffer + (by the host). + + + +CP:CP_RB_WPTR_DELAY · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x718 +DESCRIPTION: Ring Buffer Write Pointer Delay +Field Name Bits Default Description +PRE_WRITE_TIMER 27:0 0x0 Pre-Write Timer. The number of clocks that a write to + the CP_RB_WPTR register will be delayed until actually + taking effect. Default = 0 +© 2008 Advanced Micro Devices, Inc. +Proprietary 151 + Revision 1.4 October 13, 2009 + + + + +PRE_WRITE_LIMIT 31:28 0x0 Pre-Write Limit. The number of times that the + CP_RB_WPTR register can be written (while the + PRE_WRITE_TIMER has not expired) before the + CP_RB_WPTR register is forced to be updated with the + most recently written value. Default = 0 + + + +CP:CP_RESYNC_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x778 +DESCRIPTION: Raster Engine Sync Address (WO) +Field Name Bits Default Description +RESYNC_ADDR 2:0 0x0 Scratch Register Offset Address. +(Access: W) + + + +CP:CP_RESYNC_DATA · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x77c +DESCRIPTION: Raster Engine Sync Data (WO) +Field Name Bits Default Description +RESYNC_DATA 31:0 none Data written to selected Scratch Register when a sync +(Access: W) pulse pair is received from the CBA and CBB. + + + +CP:CP_STAT · [R] · 32 bits · Access: 8/16/32 · MMReg:0x7c0 +DESCRIPTION: (RO) Busy Status Signals +Field Name Bits Default Description +MRU_BUSY 0 none Memory Read Unit Busy. +MWU_BUSY 1 none Memory Write Unit Busy. +RSIU_BUSY 2 none Register Backbone Input Interface Busy. +RCIU_BUSY 3 none RBBM Output Interface Busy. +CSF_PRIMARY_BUSY 9 none Primary Command Stream Fetcher Busy. +CSF_INDIRECT_BUSY 10 none Indirect #1 Command Stream Fetcher Busy. +CSQ_PRIMARY_BUSY 11 none Data in Command Queue for Primary Stream. +CSQ_INDIRECT_BUSY 12 none Data in Command Queue for Indirect #1 Stream. +CSI_BUSY 13 none Command Stream Interpreter Busy. +CSF_INDIRECT2_BUSY 14 none Indirect #2 Command Stream Fetcher Busy. +CSQ_INDIRECT2_BUSY 15 none Data in Command Queue for Indirect #2 Stream. +GUIDMA_BUSY 28 none GUI DMA Engine Busy. +VIDDMA_BUSY 29 none VID DMA Engine Busy. +CMDSTRM_BUSY 30 none Command Stream Busy. +CP_BUSY 31 none CP Busy. + + + +CP:CP_VID_COMMAND · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7cc + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 152 + Revision 1.4 October 13, 2009 + + + + +DESCRIPTION: Command for PIO VID DMAs +Field Name Bits Default Description +CP_VID_COMMAND 31:0 none Command for PIO DMAs to the VID DMA. Only + DWORD access is allowed to this register. + + + +CP:CP_VID_DST_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7c8 +DESCRIPTION: Destination Address for PIO VID DMAs +Field Name Bits Default Description +CP_VID_DST_ADDR 31:0 none Destination address for PIO DMAs to the VID DMA. + Only DWORD access is allowed to this register. + + + +CP:CP_VID_SRC_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7c4 +DESCRIPTION: Source Address for PIO VID DMAs +Field Name Bits Default Description +CP_VID_SRC_ADDR 31:0 none Source address for PIO DMAs to the VID DMA. Only + DWORD access is allowed to this register. + + + +CP:CP_VP_ADDR_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7e8 +DESCRIPTION: Virtual vs Physical Address Control - Selects whether the address corresponds to a physical or +virtual address in memory. +Field Name Bits Default Description +SCRATCH_ALT_VP_WR 0 0x0 0=Physical (Default), 1=Virtual +SCRATCH_VP_WR 1 0x0 0=Physical (Default), 1=Virtual +RPTR_VP_UPDATE 2 0x0 0=Physical (Default), 1=Virtual +VIDDMA_VP_WR 3 0x0 0=Physical (Default), 1=Virtual +VIDDMA_VP_RD 4 0x0 0=Physical (Default), 1=Virtual +GUIDMA_VP_WR 5 0x0 0=Physical (Default), 1=Virtual +GUIDMA_VP_RD 6 0x0 0=Physical (Default), 1=Virtual +INDR2_VP_FETCH 7 0x0 0=Physical (Default), 1=Virtual +INDR1_VP_FETCH 8 0x0 0=Physical (Default), 1=Virtual +RING_VP_FETCH 9 0x0 0=Physical (Default), 1=Virtual + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 153 + Revision 1.4 October 13, 2009 + + + + +11.2 Color Buffer Registers + +CB:RB3D_AARESOLVE_CTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e88 +DESCRIPTION: Resolve Buffer Control. Unpipelined +Field Name Bits Default Description +AARESOLVE_MODE 0 0x0 Specifies if the color buffer is in resolve mode. The + cache must be empty before changing this register. + + POSSIBLE VALUES: + 00 - Normal operation. + 01 - Resolve operation. +AARESOLVE_GAMMA 1 none Specifies the gamma and degamma to be applied to the + samples before and after filtering, respectively. + + POSSIBLE VALUES: + 00 - 1.0 + 01 - 2.2 +AARESOLVE_ALPHA 2 0x0 Controls whether alpha is averaged in the resolve. 0 => + the resolved alpha value is selected from the sample 0 + value. 1=> the resolved alpha value is a filtered (average) + result of of the samples. + + POSSIBLE VALUES: + 00 - Resolved alpha value is taken from sample 0. + 01 - Resolved alpha value is the average of the + samples. The average is not gamma corrected. + + + +CB:RB3D_AARESOLVE_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e80 +DESCRIPTION: Resolve buffer destination address. The cache must be empty before changing this register if the +cb is in resolve mode. Unpipelined +Field Name Bits Default Description +AARESOLVE_OFFSET 31:5 none 256-bit aligned 3D resolve destination offset. + + + +CB:RB3D_AARESOLVE_PITCH · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e84 +DESCRIPTION: Resolve Buffer Pitch and Tiling Control. The cache must be empty before changing this register if +the cb is in resolve mode. Unpipelined +Field Name Bits Default Description +AARESOLVE_PITCH 13:1 none 3D destination pitch in multiples of 2-pixels. + + + +CB:RB3D_ABLENDCNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e08 +DESCRIPTION: Alpha Blend Control for Alpha Channel. Pipelined through the blender. +Field Name Bits Default Description + +© 2008 Advanced Micro Devices, Inc. +Proprietary 154 + Revision 1.4 October 13, 2009 + + + + +COMB_FCN 14:12 none Combine Function , Allows modification of how the + SRCBLEND and DESTBLEND are combined. + + POSSIBLE VALUES: + 00 - Add and Clamp + 01 - Add but no Clamp + 02 - Subtract Dst from Src, and Clamp + 03 - Subtract Dst from Src, and don`t Clamp + 04 - Minimum of Src, Dst (the src and dst blend + functions are forced to D3D_ONE) + 05 - Maximum of Src, Dst (the src and dst blend + functions are forced to D3D_ONE) + 06 - Subtract Src from Dst, and Clamp + 07 - Subtract Src from Dst, and don`t Clamp +SRCBLEND 21:16 none Source Blend Function , Alpha blending function (SRC). + + POSSIBLE VALUES: + 00 - RESERVED + 01 - D3D_ZERO + 02 - D3D_ONE + 03 - D3D_SRCCOLOR + 04 - D3D_INVSRCCOLOR + 05 - D3D_SRCALPHA + 06 - D3D_INVSRCALPHA + 07 - D3D_DESTALPHA + 08 - D3D_INVDESTALPHA + 09 - D3D_DESTCOLOR + 10 - D3D_INVDESTCOLOR + 11 - D3D_SRCALPHASAT + 12 - D3D_BOTHSRCALPHA + 13 - D3D_BOTHINVSRCALPHA + 14 - RESERVED + 15 - RESERVED + 16 - RESERVED + 17 - RESERVED + 18 - RESERVED + 19 - RESERVED + 20 - RESERVED + 21 - RESERVED + 22 - RESERVED + 23 - RESERVED + 24 - RESERVED + 25 - RESERVED + 26 - RESERVED + 27 - RESERVED + 28 - RESERVED + 29 - RESERVED + 30 - RESERVED + 31 - RESERVED + 32 - GL_ZERO + 33 - GL_ONE + 34 - GL_SRC_COLOR + +© 2008 Advanced Micro Devices, Inc. +Proprietary 155 + Revision 1.4 October 13, 2009 + + + + + 35 - GL_ONE_MINUS_SRC_COLOR + 36 - GL_DST_COLOR + 37 - GL_ONE_MINUS_DST_COLOR + 38 - GL_SRC_ALPHA + 39 - GL_ONE_MINUS_SRC_ALPHA + 40 - GL_DST_ALPHA + 41 - GL_ONE_MINUS_DST_ALPHA + 42 - GL_SRC_ALPHA_SATURATE + 43 - GL_CONSTANT_COLOR + 44 - GL_ONE_MINUS_CONSTANT_COLOR + 45 - GL_CONSTANT_ALPHA + 46 - GL_ONE_MINUS_CONSTANT_ALPHA + 47 - RESERVED + 48 - RESERVED + 49 - RESERVED + 50 - RESERVED + 51 - RESERVED + 52 - RESERVED + 53 - RESERVED + 54 - RESERVED + 55 - RESERVED + 56 - RESERVED + 57 - RESERVED + 58 - RESERVED + 59 - RESERVED + 60 - RESERVED + 61 - RESERVED + 62 - RESERVED + 63 - RESERVED +DESTBLEND 29:24 none Destination Blend Function , Alpha blending function + (DST). + + POSSIBLE VALUES: + 00 - RESERVED + 01 - D3D_ZERO + 02 - D3D_ONE + 03 - D3D_SRCCOLOR + 04 - D3D_INVSRCCOLOR + 05 - D3D_SRCALPHA + 06 - D3D_INVSRCALPHA + 07 - D3D_DESTALPHA + 08 - D3D_INVDESTALPHA + 09 - D3D_DESTCOLOR + 10 - D3D_INVDESTCOLOR + 11 - RESERVED + 12 - RESERVED + 13 - RESERVED + 14 - RESERVED + 15 - RESERVED + 16 - RESERVED + 17 - RESERVED + 18 - RESERVED + 19 - RESERVED + +© 2008 Advanced Micro Devices, Inc. +Proprietary 156 + Revision 1.4 October 13, 2009 + + + + + 20 - RESERVED + 21 - RESERVED + 22 - RESERVED + 23 - RESERVED + 24 - RESERVED + 25 - RESERVED + 26 - RESERVED + 27 - RESERVED + 28 - RESERVED + 29 - RESERVED + 30 - RESERVED + 31 - RESERVED + 32 - GL_ZERO + 33 - GL_ONE + 34 - GL_SRC_COLOR + 35 - GL_ONE_MINUS_SRC_COLOR + 36 - GL_DST_COLOR + 37 - GL_ONE_MINUS_DST_COLOR + 38 - GL_SRC_ALPHA + 39 - GL_ONE_MINUS_SRC_ALPHA + 40 - GL_DST_ALPHA + 41 - GL_ONE_MINUS_DST_ALPHA + 42 - RESERVED + 43 - GL_CONSTANT_COLOR + 44 - GL_ONE_MINUS_CONSTANT_COLOR + 45 - GL_CONSTANT_ALPHA + 46 - GL_ONE_MINUS_CONSTANT_ALPHA + 47 - RESERVED + 48 - RESERVED + 49 - RESERVED + 50 - RESERVED + 51 - RESERVED + 52 - RESERVED + 53 - RESERVED + 54 - RESERVED + 55 - RESERVED + 56 - RESERVED + 57 - RESERVED + 58 - RESERVED + 59 - RESERVED + 60 - RESERVED + 61 - RESERVED + 62 - RESERVED + 63 - RESERVED + + + +CB:RB3D_BLENDCNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e04 +DESCRIPTION: Alpha Blend Control for Color Channels. Pipelined through the blender. +Field Name Bits Default Description +ALPHA_BLEND_ENABLE 0 0x0 Allow alpha blending with the destination. + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 157 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable +SEPARATE_ALPHA_ENABLE 1 0x0 Enables use of RB3D_ABLENDCNTL + + POSSIBLE VALUES: + 00 - Disabled (Use RB3D_BLENDCNTL) + 01 - Enabled (Use RB3D_ABLENDCNTL) +READ_ENABLE 2 0x1 When blending is enabled, this enables memory reads. + Memory reads will still occur when this is disabled if + they are for reasons not related to blending. + + POSSIBLE VALUES: + 00 - Disable reads + 01 - Enable reads +DISCARD_SRC_PIXELS 5:3 0x0 Discard pixels when blending is enabled based on the src + color. + + POSSIBLE VALUES: + 00 - Disable + 01 - Discard pixels if src alpha <= + RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD + 02 - Discard pixels if src color <= + RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD + 03 - Discard pixels if src argb <= + RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD + 04 - Discard pixels if src alpha >= + RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD + 05 - Discard pixels if src color >= + RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD + 06 - Discard pixels if src argb >= + RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD + 07 - (reserved) +COMB_FCN 14:12 none Combine Function , Allows modification of how the + SRCBLEND and DESTBLEND are combined. + + POSSIBLE VALUES: + 00 - Add and Clamp + 01 - Add but no Clamp + 02 - Subtract Dst from Src, and Clamp + 03 - Subtract Dst from Src, and don`t Clamp + 04 - Minimum of Src, Dst (the src and dst blend + functions are forced to D3D_ONE) + 05 - Maximum of Src, Dst (the src and dst blend + functions are forced to D3D_ONE) + 06 - Subtract Src from Dst, and Clamp + 07 - Subtract Src from Dst, and don`t Clamp +SRCBLEND 21:16 none Source Blend Function , Alpha blending function (SRC). + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 158 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - RESERVED + 01 - D3D_ZERO + 02 - D3D_ONE + 03 - D3D_SRCCOLOR + 04 - D3D_INVSRCCOLOR + 05 - D3D_SRCALPHA + 06 - D3D_INVSRCALPHA + 07 - D3D_DESTALPHA + 08 - D3D_INVDESTALPHA + 09 - D3D_DESTCOLOR + 10 - D3D_INVDESTCOLOR + 11 - D3D_SRCALPHASAT + 12 - D3D_BOTHSRCALPHA + 13 - D3D_BOTHINVSRCALPHA + 14 - RESERVED + 15 - RESERVED + 16 - RESERVED + 17 - RESERVED + 18 - RESERVED + 19 - RESERVED + 20 - RESERVED + 21 - RESERVED + 22 - RESERVED + 23 - RESERVED + 24 - RESERVED + 25 - RESERVED + 26 - RESERVED + 27 - RESERVED + 28 - RESERVED + 29 - RESERVED + 30 - RESERVED + 31 - RESERVED + 32 - GL_ZERO + 33 - GL_ONE + 34 - GL_SRC_COLOR + 35 - GL_ONE_MINUS_SRC_COLOR + 36 - GL_DST_COLOR + 37 - GL_ONE_MINUS_DST_COLOR + 38 - GL_SRC_ALPHA + 39 - GL_ONE_MINUS_SRC_ALPHA + 40 - GL_DST_ALPHA + 41 - GL_ONE_MINUS_DST_ALPHA + 42 - GL_SRC_ALPHA_SATURATE + 43 - GL_CONSTANT_COLOR + 44 - GL_ONE_MINUS_CONSTANT_COLOR + 45 - GL_CONSTANT_ALPHA + 46 - GL_ONE_MINUS_CONSTANT_ALPHA + 47 - RESERVED + 48 - RESERVED + 49 - RESERVED + 50 - RESERVED + +© 2008 Advanced Micro Devices, Inc. +Proprietary 159 + Revision 1.4 October 13, 2009 + + + + + 51 - RESERVED + 52 - RESERVED + 53 - RESERVED + 54 - RESERVED + 55 - RESERVED + 56 - RESERVED + 57 - RESERVED + 58 - RESERVED + 59 - RESERVED + 60 - RESERVED + 61 - RESERVED + 62 - RESERVED + 63 - RESERVED +DESTBLEND 29:24 none Destination Blend Function , Alpha blending function + (DST). + + POSSIBLE VALUES: + 00 - RESERVED + 01 - D3D_ZERO + 02 - D3D_ONE + 03 - D3D_SRCCOLOR + 04 - D3D_INVSRCCOLOR + 05 - D3D_SRCALPHA + 06 - D3D_INVSRCALPHA + 07 - D3D_DESTALPHA + 08 - D3D_INVDESTALPHA + 09 - D3D_DESTCOLOR + 10 - D3D_INVDESTCOLOR + 11 - RESERVED + 12 - RESERVED + 13 - RESERVED + 14 - RESERVED + 15 - RESERVED + 16 - RESERVED + 17 - RESERVED + 18 - RESERVED + 19 - RESERVED + 20 - RESERVED + 21 - RESERVED + 22 - RESERVED + 23 - RESERVED + 24 - RESERVED + 25 - RESERVED + 26 - RESERVED + 27 - RESERVED + 28 - RESERVED + 29 - RESERVED + 30 - RESERVED + 31 - RESERVED + 32 - GL_ZERO + 33 - GL_ONE + 34 - GL_SRC_COLOR + 35 - GL_ONE_MINUS_SRC_COLOR + +© 2008 Advanced Micro Devices, Inc. +Proprietary 160 + Revision 1.4 October 13, 2009 + + + + + 36 - GL_DST_COLOR + 37 - GL_ONE_MINUS_DST_COLOR + 38 - GL_SRC_ALPHA + 39 - GL_ONE_MINUS_SRC_ALPHA + 40 - GL_DST_ALPHA + 41 - GL_ONE_MINUS_DST_ALPHA + 42 - RESERVED + 43 - GL_CONSTANT_COLOR + 44 - GL_ONE_MINUS_CONSTANT_COLOR + 45 - GL_CONSTANT_ALPHA + 46 - GL_ONE_MINUS_CONSTANT_ALPHA + 47 - RESERVED + 48 - RESERVED + 49 - RESERVED + 50 - RESERVED + 51 - RESERVED + 52 - RESERVED + 53 - RESERVED + 54 - RESERVED + 55 - RESERVED + 56 - RESERVED + 57 - RESERVED + 58 - RESERVED + 59 - RESERVED + 60 - RESERVED + 61 - RESERVED + 62 - RESERVED + 63 - RESERVED +SRC_ALPHA_0_NO_READ 30 0x0 Enables source alpha zero performance optimization to + skip reads. + + POSSIBLE VALUES: + 00 - Disable source alpha zero performance + optimization to skip reads + 01 - Enable source alpha zero performance + optimization to skip reads +SRC_ALPHA_1_NO_READ 31 0x0 Enables source alpha one performance optimization to + skip reads. + + POSSIBLE VALUES: + 00 - Disable source alpha one performance + optimization to skip reads + 01 - Enable source alpha one performance + optimization to skip reads + + + +CB:RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD · [R/W] · 32 bits · Access: 8/16/32 · +MMReg:0x4ea4 +DESCRIPTION: Discard src pixels greater than or equal to threshold. +Field Name Bits Default Description + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 161 + Revision 1.4 October 13, 2009 + + + + +BLUE 7:0 0xFF Blue +GREEN 15:8 0xFF Green +RED 23:16 0xFF Red +ALPHA 31:24 0xFF Alpha + + + +CB:RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD · [R/W] · 32 bits · Access: 8/16/32 · +MMReg:0x4ea0 +DESCRIPTION: Discard src pixels less than or equal to threshold. +Field Name Bits Default Description +BLUE 7:0 0x0 Blue +GREEN 15:8 0x0 Green +RED 23:16 0x0 Red +ALPHA 31:24 0x0 Alpha + + + +CB:RB3D_CCTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e00 +DESCRIPTION: Unpipelined. +Field Name Bits Default Description +NUM_MULTIWRITES 6:5 0x0 A quad is replicated and written to this + many buffers. + + POSSIBLE VALUES: + 00 - 1 buffer. This is the only mode + where the cb processes the end of packet + command. + 01 - 2 buffers + 02 - 3 buffers + 03 - 4 buffers +CLRCMP_FLIPE_ENABLE 7 0x0 Enables equivalent of rage128 + CMP_EQ_FLIP color compare mode. + This is used to ensure 3D data does not + get chromakeyed away by logic in the + backend. + + POSSIBLE VALUES: + 00 - Disable color compare. + 01 - Enable color compare. +AA_COMPRESSION_ENABLE 9 none Enables AA color compression. Cmask + must also be enabled when aa + compression is enabled. The cache must + be empty before this is changed. + + POSSIBLE VALUES: + 00 - Disable AA compression + 01 - Enable AA compression + +© 2008 Advanced Micro Devices, Inc. +Proprietary 162 + Revision 1.4 October 13, 2009 + + + + +CMASK_ENABLE 10 none Enables use of the cmask ram. The cache + must be empty before this is changed. + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable +Reserved 11 0x0 Set to 0 +INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE 12 0x0 Enables indepedent color channel masks + for the MRTs. Disabling this feature will + cause all the MRTs to use color channel + mask 0. + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable +WRITE_COMPRESSION_DISABLE 13 none Disables write compression. + + POSSIBLE VALUES: + 00 - Enable write compression + 01 - Disable write compression +INDEPENDENT_COLORFORMAT_ENABLE 14 0x0 Enables independent color format for the + MRTs. Disabling this feature will cause + all the MRTs to use color format 0. + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable + + + +CB:RB3D_CLRCMP_CLR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e20 +DESCRIPTION: Color Compare Color. Stalls the 2d/3d datapath until it is idle. +Field Name Bits Default Description +CLRCMP_CLR 31:0 none Like RB2D_CLRCMP_CLR, but a separate register is + provided to keep 2D and 3D state separate. + + + +CB:RB3D_CLRCMP_FLIPE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e1c +DESCRIPTION: Color Compare Flip. Stalls the 2d/3d datapath until it is idle. +Field Name Bits Default Description +CLRCMP_FLIPE 31:0 none Like RB2D_CLRCMP_FLIPE, but a separate register is + provided to keep 2D and 3D state separate. + + + +CB:RB3D_CLRCMP_MSK · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e24 +DESCRIPTION: Color Compare Mask. Stalls the 2d/3d datapath until it is idle. +Field Name Bits Default Description + +© 2008 Advanced Micro Devices, Inc. +Proprietary 163 + Revision 1.4 October 13, 2009 + + + + +CLRCMP_MSK 31:0 none Like RB2D_CLRCMP_CLR, but separate registers + provided to keep 2D and 3D state separate. + + + +CB:RB3D_COLOROFFSET[0-3] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e28-0x4e34 +DESCRIPTION: Color Buffer Address Offset of multibuffer 0. Unpipelined. +Field Name Bits Default Description +COLOROFFSET 31:5 none 256-bit aligned 3D destination offset address. The cache + must be empty before this is changed. + + + +CB:RB3D_COLORPITCH[0-3] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e38-0x4e44 +DESCRIPTION: Color buffer format and tiling control for all the multibuffers and the pitch of multibuffer 0. +Unpipelined. The cache must be empty before any of the registers are changed. +Field Name Bits Default Description +COLORPITCH 13:1 none 3D destination pitch in multiples of 2-pixels. +COLORTILE 16 none Denotes whether the 3D destination is in macrotiled + format. + + POSSIBLE VALUES: + 00 - 3D destination is not macrotiled + 01 - 3D destination is macrotiled +COLORMICROTILE 18:17 none Denotes whether the 3D destination is in microtiled + format. + + POSSIBLE VALUES: + 00 - 3D destination is no microtiled + 01 - 3D destination is microtiled + 02 - 3D destination is square microtiled. Only + available in 16-bit + 03 - (reserved) +COLORENDIAN 20:19 none Specifies endian control for the color buffer. + + POSSIBLE VALUES: + 00 - No swap + 01 - Word swap (2 bytes in 16-bit) + 02 - Dword swap (4 bytes in a 32-bit) + 03 - Half-Dword swap (2 16-bit in a 32-bit) +COLORFORMAT 24:21 0x6 3D destination color format. + + POSSIBLE VALUES: + 00 - ARGB10101010 + 01 - UV1010 + 02 - CI8 (2D ONLY) + 03 - ARGB1555 + 04 - RGB565 + 05 - ARGB2101010 + 06 - ARGB8888 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 164 + Revision 1.4 October 13, 2009 + + + + + 07 - ARGB32323232 + 08 - (Reserved) + 09 - I8 + 10 - ARGB16161616 + 11 - YUV422 packed (VYUY) + 12 - YUV422 packed (YVYU) + 13 - UV88 + 14 - I10 + 15 - ARGB4444 + + + +CB:RB3D_COLOR_CHANNEL_MASK · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e0c +DESCRIPTION: 3D Color Channel Mask. If all the channels used in the current color format are disabled, then +the cb will discard all the incoming quads. Pipelined through the blender. +Field Name Bits Default Description +BLUE_MASK 0 0x1 mask bit for the blue channel + + POSSIBLE VALUES: + 00 - disable + 01 - enable +GREEN_MASK 1 0x1 mask bit for the green channel + + POSSIBLE VALUES: + 00 - disable + 01 - enable +RED_MASK 2 0x1 mask bit for the red channel + + POSSIBLE VALUES: + 00 - disable + 01 - enable +ALPHA_MASK 3 0x1 mask bit for the alpha channel + + POSSIBLE VALUES: + 00 - disable + 01 - enable +BLUE_MASK1 4 0x1 mask bit for the blue channel of MRT 1 + + POSSIBLE VALUES: + 00 - disable + 01 - enable +GREEN_MASK1 5 0x1 mask bit for the green channel of MRT 1 + + POSSIBLE VALUES: + 00 - disable + 01 - enable +RED_MASK1 6 0x1 mask bit for the red channel of MRT 1 + + POSSIBLE VALUES: + +© 2008 Advanced Micro Devices, Inc. +Proprietary 165 + Revision 1.4 October 13, 2009 + + + + + 00 - disable + 01 - enable +ALPHA_MASK1 7 0x1 mask bit for the alpha channel of MRT 1 + + POSSIBLE VALUES: + 00 - disable + 01 - enable +BLUE_MASK2 8 0x1 mask bit for the blue channel of MRT 2 + + POSSIBLE VALUES: + 00 - disable + 01 - enable +GREEN_MASK2 9 0x1 mask bit for the green channel of MRT 2 + + POSSIBLE VALUES: + 00 - disable + 01 - enable +RED_MASK2 10 0x1 mask bit for the red channel of MRT 2 + + POSSIBLE VALUES: + 00 - disable + 01 - enable +ALPHA_MASK2 11 0x1 mask bit for the alpha channel of MRT 2 + + POSSIBLE VALUES: + 00 - disable + 01 - enable +BLUE_MASK3 12 0x1 mask bit for the blue channel of MRT 3 + + POSSIBLE VALUES: + 00 - disable + 01 - enable +GREEN_MASK3 13 0x1 mask bit for the green channel of MRT 3 + + POSSIBLE VALUES: + 00 - disable + 01 - enable +RED_MASK3 14 0x1 mask bit for the red channel of MRT 3 + + POSSIBLE VALUES: + 00 - disable + 01 - enable +ALPHA_MASK3 15 0x1 mask bit for the alpha channel of MRT 3 + + POSSIBLE VALUES: + 00 - disable + 01 - enable + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 166 + Revision 1.4 October 13, 2009 + + + + +CB:RB3D_COLOR_CLEAR_VALUE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e14 +DESCRIPTION: Clear color that is used when the color mask is set to 00. Unpipelined. Program this register with +a 32-bit value in ARGB8888 or ARGB2101010 formats, ignoring the fields. +Field Name Bits Default Description +BLUE 7:0 none blue clear color +GREEN 15:8 none green clear color +RED 23:16 none red clear color +ALPHA 31:24 none alpha clear color + + + +CB:RB3D_COLOR_CLEAR_VALUE_AR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x46c0 +DESCRIPTION: Alpha and red clear color values that are used when the color mask is set to 00 in FP16 per +component mode. Unpipelined. +Field Name Bits Default Description +RED 15:0 none red clear color +ALPHA 31:16 none alpha clear color + + + +CB:RB3D_COLOR_CLEAR_VALUE_GB · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x46c4 +DESCRIPTION: Green and blue clear color values that are used when the color mask is set to 00 in FP16 per +component mode. Unpipelined. +Field Name Bits Default Description +BLUE 15:0 none blue clear color +GREEN 31:16 none green clear color + + + +CB:RB3D_CONSTANT_COLOR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e10 +DESCRIPTION: Constant color used by the blender. Pipelined through the blender. +Field Name Bits Default Description +BLUE 7:0 none blue constant color (For R520, this field is ignored, use + RB3D_CONSTANT_COLOR_GB__BLUE instead) +GREEN 15:8 none green constant color (For R520, this field is ignored, use + RB3D_CONSTANT_COLOR_GB__GREEN instead) +RED 23:16 none red constant color (For R520, this field is ignored, use + RB3D_CONSTANT_COLOR_AR__RED instead) +ALPHA 31:24 none alpha constant color (For R520, this field is ignored, use + RB3D_CONSTANT_COLOR_AR__ALPHA instead) + + + +CB:RB3D_CONSTANT_COLOR_AR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4ef8 +DESCRIPTION: Constant color used by the blender. Pipelined through the blender. +Field Name Bits Default Description +RED 15:0 none red constant color in 0.10 fixed or FP16 format + +© 2008 Advanced Micro Devices, Inc. +Proprietary 167 + Revision 1.4 October 13, 2009 + + + + +ALPHA 31:16 none alpha constant color in 0.10 fixed or FP16 format + + + +CB:RB3D_CONSTANT_COLOR_GB · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4efc +DESCRIPTION: Constant color used by the blender. Pipelined through the blender. +Field Name Bits Default Description +BLUE 15:0 none blue constant color in 0.10 fixed or FP16 format +GREEN 31:16 none green constant color in 0.10 fixed or FP16 format + + + +CB:RB3D_DITHER_CTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e50 +DESCRIPTION: Dithering control register. Pipelined through the blender. +Field Name Bits Default Description +DITHER_MODE 1:0 0x0 Dither mode + + POSSIBLE VALUES: + 00 - Truncate + 01 - Round + 02 - LUT dither + 03 - (reserved) +ALPHA_DITHER_MODE 3:2 0x0 POSSIBLE VALUES: + 00 - Truncate + 01 - Round + 02 - LUT dither + 03 - (reserved) + + + +CB:RB3D_DSTCACHE_CTLSTAT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e4c +DESCRIPTION: Destination Color Buffer Cache Control/Status. If the cb is in e2 mode, then a flush or free will +not occur upon a write to this register, but a sync will be immediately sent if one is requested. If both DC_FLUSH +and DC_FREE are zero but DC_FINISH is one, then a sync will be sent immediately -- the cb will not wait for all +the previous operations to complete before sending the sync. Unpipelined except when DC_FINISH and DC_FREE +are both set to zero. +Field Name Bits Default Description +DC_FLUSH 1:0 0x0 Setting this bit flushes dirty data from the 3D Dst Cache. + Unless the DC_FREE bits are also set, the tags in the + cache remain valid. A purge is achieved by setting both + DC_FLUSH and DC_FREE. + + POSSIBLE VALUES: + 00 - No effect + 01 - No effect + 02 - Flushes dirty 3D data + 03 - Flushes dirty 3D data +DC_FREE 3:2 0x0 Setting this bit invalidates the 3D Dst Cache tags. Unless + the DC_FLUSH bit is also set, the cache lines are not + written to memory. A purge is achieved by setting both + +© 2008 Advanced Micro Devices, Inc. +Proprietary 168 + Revision 1.4 October 13, 2009 + + + + + DC_FLUSH and DC_FREE. + + POSSIBLE VALUES: + 00 - No effect + 01 - No effect + 02 - Free 3D tags + 03 - Free 3D tags +DC_FINISH 4 0x0 POSSIBLE VALUES: + 00 - do not send a finish signal to the CP + 01 - send a finish signal to the CP after the end of + operation + + + +CB:RB3D_FIFO_SIZE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4ef4 +DESCRIPTION: Sets the fifo sizes +Field Name Bits Default Description +OP_FIFO_SIZE 1:0 0x0 Determines the size of the op fifo + + POSSIBLE VALUES: + 00 - Full size + 01 - 1/2 size + 02 - 1/4 size + 03 - 1/8 size + + + +CB:RB3D_ROPCNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e18 +DESCRIPTION: 3D ROP Control. Stalls the 2d/3d datapath until it is idle. +Field Name Bits Default Description +ROP_ENABLE 2 0x0 POSSIBLE VALUES: + 00 - Disable ROP. (Forces ROP2 to be 0xC). + 01 - Enabled +ROP 11:8 none ROP2 code for 3D fragments. This value is replicated + into 2 nibbles to form the equivalent ROP3 code to + control the ROP3 logic. These are the GDI ROP2 codes. + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 169 + Revision 1.4 October 13, 2009 + + + + +11.3 Fog Registers + +FG:FG_ALPHA_FUNC · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bd4 +DESCRIPTION: Alpha Function +Field Name Bits Default Description +AF_VAL 7:0 0x0 Specifies the 8-bit alpha compare value when + AF_EN_8BIT is enabled +AF_FUNC 10:8 0x0 Specifies the alpha compare function. + + POSSIBLE VALUES: + 00 - AF_NEVER + 01 - AF_LESS + 02 - AF_EQUAL + 03 - AF_LE + 04 - AF_GREATER + 05 - AF_NOTEQUAL + 06 - AF_GE + 07 - AF_ALWAYS +AF_EN 11 0x0 Enables/Disables alpha compare function. + + POSSIBLE VALUES: + 00 - Disable alpha function. + 01 - Enable alpha function. +AF_EN_8BIT 12 0x0 Enable 8-bit alpha compare function. + + POSSIBLE VALUES: + 00 - Default 10-bit alpha compare. + 01 - Enable 8-bit alpha compare. +AM_EN 16 0x0 Enables/Disables alpha-to-mask function. + + POSSIBLE VALUES: + 00 - Disable alpha to mask function. + 01 - Enable alpha to mask function. +AM_CFG 17 0x0 Specfies number of sub-pixel samples for alpha-to-mask + function. + + POSSIBLE VALUES: + 00 - 2/4 sub-pixel samples. + 01 - 3/6 sub-pixel samples. +DITH_EN 20 0x0 Enables/Disables RGB Dithering (Not supported in + R520) + + POSSIBLE VALUES: + 00 - Disable Dithering + 01 - Enable Dithering. +ALP_OFF_EN 24 0x0 Alpha offset enable/disable (Not supported in R520) + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 170 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Disables alpha offset of 2 (default r300 & rv350 + behavior) + 01 - Enables offset of 2 on alpha coming in from the + US +DISCARD_ZERO_MASK_QUAD 25 0x0 Enable/Disable discard zero mask coverage quad to ZB + + POSSIBLE VALUES: + 00 - No discard of zero coverage mask quads + 01 - Discard zero coverage mask quads +FP16_ENABLE 28 0x0 Enables/Disables FP16 alpha function + + POSSIBLE VALUES: + 00 - Default 10-bit alpha compare and alpha-to-mask + function + 01 - Enable FP16 alpha compare and alpha-to-mask + function + + + +FG:FG_ALPHA_VALUE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4be0 +DESCRIPTION: Alpha Compare Value +Field Name Bits Default Description +AF_VAL 15:0 0x0 Specifies the alpha compare value, 0.10 fixed or FP16 + format + + + +FG:FG_DEPTH_SRC · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bd8 +DESCRIPTION: Where does depth come from? +Field Name Bits Default Description +DEPTH_SRC 0 0x0 POSSIBLE VALUES: + 00 - Depth comes from scan converter as plane + equation. + 01 - Depth comes from shader as four discrete values. + + + +FG:FG_FOG_BLEND · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bc0 +DESCRIPTION: Fog Blending Enable +Field Name Bits Default Description +ENABLE 0 0x0 Enable for fog blending + + POSSIBLE VALUES: + 00 - Disables fog (output matches input color). + 01 - Enables fog. +FN 2:1 0x0 Fog generation function + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 171 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Fog function is linear + 01 - Fog function is exponential + 02 - Fog function is exponential squared + 03 - Fog is derived from constant fog factor + + + +FG:FG_FOG_COLOR_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bd0 +DESCRIPTION: Blue Component of Fog Color +Field Name Bits Default Description +BLUE 9:0 0x0 Blue component of fog color; (0.10) fixed format. + + + +FG:FG_FOG_COLOR_G · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bcc +DESCRIPTION: Green Component of Fog Color +Field Name Bits Default Description +GREEN 9:0 0x0 Green component of fog color; (0.10) fixed format. + + + +FG:FG_FOG_COLOR_R · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bc8 +DESCRIPTION: Red Component of Fog Color +Field Name Bits Default Description +RED 9:0 0x0 Red component of fog color; (0.10) fixed format. + + + +FG:FG_FOG_FACTOR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bc4 +DESCRIPTION: Constant Factor for Fog Blending +Field Name Bits Default Description +FACTOR 9:0 0x0 Constant fog factor; fixed (0.10) format. + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 172 + Revision 1.4 October 13, 2009 + + + + +11.4 Geometry Assembly Registers + +GA:GA_COLOR_CONTROL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4278 +DESCRIPTION: Specifies per RGB or Alpha shading method. +Field Name Bits Default Description +RGB0_SHADING 1:0 0x0 Specifies solid, flat or Gouraud shading. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +ALPHA0_SHADING 3:2 0x0 Specifies solid, flat or Gouraud shading. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +RGB1_SHADING 5:4 0x0 Specifies solid, flat or Gouraud shading. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +ALPHA1_SHADING 7:6 0x0 Specifies solid, flat or Gouraud shading. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +RGB2_SHADING 9:8 0x0 Specifies solid, flat or Gouraud shading. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +ALPHA2_SHADING 11:10 0x0 Specifies solid, flat or Gouraud shading. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +RGB3_SHADING 13:12 0x0 Specifies solid, flat or Gouraud shading. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading + +© 2008 Advanced Micro Devices, Inc. +Proprietary 173 + Revision 1.4 October 13, 2009 + + + + +ALPHA3_SHADING 15:14 0x0 Specifies solid, flat or Gouraud shading. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +PROVOKING_VERTEX 17:16 0x0 Specifies, for flat shaded polygons, which vertex holds + the polygon color. + + POSSIBLE VALUES: + 00 - Provoking is first vertex + 01 - Provoking is second vertex + 02 - Provoking is third vertex + 03 - Provoking is always last vertex + + + +GA:GA_COLOR_CONTROL_PS3 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4258 +DESCRIPTION: Specifies color properties and mappings of textures. +Field Name Bits Default Description +TEX0_SHADING_PS3 1:0 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +TEX1_SHADING_PS3 3:2 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +TEX2_SHADING_PS3 5:4 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +TEX3_SHADING_PS3 7:6 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +TEX4_SHADING_PS3 9:8 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture. +© 2008 Advanced Micro Devices, Inc. +Proprietary 174 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +TEX5_SHADING_PS3 11:10 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +TEX6_SHADING_PS3 13:12 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +TEX7_SHADING_PS3 15:14 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +TEX8_SHADING_PS3 17:16 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +TEX9_SHADING_PS3 19:18 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +TEX10_SHADING_PS3 21:20 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for tex10 components. + + POSSIBLE VALUES: + 00 - Solid fill color + 01 - Flat shading + 02 - Gouraud shading +COLOR0_TEX_OVERRIDE 25:22 0x0 Specifies if each color should come from a texture and + which one. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 175 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - No override + 01 - Stuff texture 0 + 02 - Stuff texture 1 + 03 - Stuff texture 2 + 04 - Stuff texture 3 + 05 - Stuff texture 4 + 06 - Stuff texture 5 + 07 - Stuff texture 6 + 08 - Stuff texture 7 + 09 - Stuff texture 8/C2 + 10 - Stuff texture 9/C3 +COLOR1_TEX_OVERRIDE 29:26 0x0 Specifies if each color should come from a texture and + which one. + + POSSIBLE VALUES: + 00 - No override + 01 - Stuff texture 0 + 02 - Stuff texture 1 + 03 - Stuff texture 2 + 04 - Stuff texture 3 + 05 - Stuff texture 4 + 06 - Stuff texture 5 + 07 - Stuff texture 6 + 08 - Stuff texture 7 + 09 - Stuff texture 8/C2 + 10 - Stuff texture 9/C3 + + + +GA:GA_ENHANCE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4274 +DESCRIPTION: GA Enhancement Register +Field Name Bits Default Description +DEADLOCK_CNTL 0 0x0 TCL/GA Deadlock control. + + POSSIBLE VALUES: + 00 - No effect. + 01 - Prevents TCL interface from deadlocking on GA + side. +FASTSYNC_CNTL 1 0x1 Enables Fast register/primitive switching + + POSSIBLE VALUES: + 00 - No effect. + 01 - Enables high-performance register/primitive + switching. +REG_READWRITE 2 0x0 R520+: When set, GA supports simultaneous register + reads & writes + + POSSIBLE VALUES: + +© 2008 Advanced Micro Devices, Inc. +Proprietary 176 + Revision 1.4 October 13, 2009 + + + + + 00 - No effect. + 01 - Enables GA support of simultaneous register + reads and writes. +REG_NOSTALL 3 0x0 POSSIBLE VALUES: + 00 - No effect. + 01 - Enables GA support of no-stall reads for register + read back. + + + +GA:GA_FIFO_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4270 +DESCRIPTION: GA Input fifo high water marks +Field Name Bits Default Description +VERTEX_FIFO 2:0 0x0 Number of words remaining in input vertex fifo before + asserting nearly full +INDEX_FIFO 5:3 0x0 Number of words remaining in input primitive fifo + before asserting nearly full +REG_FIFO 13:6 0x0 Number of words remaining in input register fifo before + asserting nearly full + + + +GA:GA_FILL_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x422c +DESCRIPTION: Alpha fill color +Field Name Bits Default Description +COLOR_ALPHA 31:0 0x0 FP20 format for alpha fill. + + + +GA:GA_FILL_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4228 +DESCRIPTION: Blue fill color +Field Name Bits Default Description +COLOR_BLUE 31:0 0x0 FP20 format for blue fill. + + + +GA:GA_FILL_G · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4224 +DESCRIPTION: Green fill color +Field Name Bits Default Description +COLOR_GREEN 31:0 0x0 FP20 format for green fill. + + + +GA:GA_FILL_R · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4220 +DESCRIPTION: Red fill color +Field Name Bits Default Description +COLOR_RED 31:0 0x0 FP20 format for red fill. + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 177 + Revision 1.4 October 13, 2009 + + + + +GA:GA_FOG_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4298 +DESCRIPTION: Specifies the offset to apply to fog. +Field Name Bits Default Description +VALUE 31:0 0x0 32b SPFP scale value. + + + +GA:GA_FOG_SCALE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4294 +DESCRIPTION: Specifies the scale to apply to fog. +Field Name Bits Default Description +VALUE 31:0 0x0 32b SPFP scale value. + + + +GA:GA_IDLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x425c +DESCRIPTION: Returns idle status of various G3D block, captured when GA_IDLE written or when hard or soft +reset asserted. +Field Name Bits Default Description +PIPE3_Z_IDLE 0 0x0 Idle status of physical pipe 3 Z unit +PIPE2_Z_IDLE 1 0x0 Idle status of physical pipe 2 Z unit +PIPE3_CB_IDLE 2 0x0 Idle status of physical pipe 3 CB unit +PIPE2_CB_IDLE 3 0x0 Idle status of physical pipe 2 CB unit +PIPE3_FG_IDLE 4 0x0 Idle status of physical pipe 3 FG unit +PIPE2_FG_IDLE 5 0x0 Idle status of physical pipe 2 FG unit +PIPE3_US_IDLE 6 0x0 Idle status of physical pipe 3 US unit +PIPE2_US_IDLE 7 0x0 Idle status of physical pipe 2 US unit +PIPE3_SC_IDLE 8 0x0 Idle status of physical pipe 3 SC unit +PIPE2_SC_IDLE 9 0x0 Idle status of physical pipe 2 SC unit +PIPE3_RS_IDLE 10 0x0 Idle status of physical pipe 3 RS unit +PIPE2_RS_IDLE 11 0x0 Idle status of physical pipe 2 RS unit +PIPE1_Z_IDLE 12 0x0 Idle status of physical pipe 1 Z unit +PIPE0_Z_IDLE 13 0x0 Idle status of physical pipe 0 Z unit +PIPE1_CB_IDLE 14 0x0 Idle status of physical pipe 1 CB unit +PIPE0_CB_IDLE 15 0x0 Idle status of physical pipe 0 CB unit +PIPE1_FG_IDLE 16 0x0 Idle status of physical pipe 1 FG unit +PIPE0_FG_IDLE 17 0x0 Idle status of physical pipe 0 FG unit +PIPE1_US_IDLE 18 0x0 Idle status of physical pipe 1 US unit +PIPE0_US_IDLE 19 0x0 Idle status of physical pipe 0 US unit +PIPE1_SC_IDLE 20 0x0 Idle status of physical pipe 1 SC unit +PIPE0_SC_IDLE 21 0x0 Idle status of physical pipe 0 SC unit +PIPE1_RS_IDLE 22 0x0 Idle status of physical pipe 1 RS unit +PIPE0_RS_IDLE 23 0x0 Idle status of physical pipe 0 RS unit + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 178 + Revision 1.4 October 13, 2009 + + + + +SU_IDLE 24 0x0 Idle status of SU unit +GA_IDLE 25 0x0 Idle status of GA unit +GA_UNIT2_IDLE 26 0x0 Idle status of GA unit2 + + + +GA:GA_LINE_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4234 +DESCRIPTION: Line control +Field Name Bits Default Description +WIDTH 15:0 0x0 1/2 width of line, in subpixels (1/12 or 1/16 only, even in + 8b subprecision); (16.0) fixed format. +END_TYPE 17:16 0x0 Specifies how ends of lines should be drawn. + + POSSIBLE VALUES: + 00 - Horizontal + 01 - Vertical + 02 - Square (horizontal or vertical depending upon + slope) + 03 - Computed (perpendicular to slope) +SORT 18 0x0 R520+: When enabled, all lines are sorted so that V0 is + vertex with smallest X, or if X equal, smallest Y. + + POSSIBLE VALUES: + 00 - No sorting (default) + 01 - Sort on minX than MinY + + + +GA:GA_LINE_S0 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4264 +DESCRIPTION: S Texture Coordinate Value for Vertex 0 of Line (stuff textures -- i.e. AA) +Field Name Bits Default Description +S0 31:0 0x0 S texture coordinate value generated for vertex 0 of an + antialiased line; 32-bit IEEE float format. Typical 0.0. + + + +GA:GA_LINE_S1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4268 +DESCRIPTION: S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) +Field Name Bits Default Description +S1 31:0 0x0 S texture coordinate value generated for vertex 1 of an + antialiased line; 32-bit IEEE float format. Typical 1.0. + + + +GA:GA_LINE_STIPPLE_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4238 +DESCRIPTION: Line Stipple configuration information. +Field Name Bits Default Description +LINE_RESET 1:0 0x0 Specify type of reset to use for stipple accumulation. + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 179 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - No reseting + 01 - Reset per line + 02 - Reset per packet +STIPPLE_SCALE 31:2 0x0 Specifies, in truncated (30b) floating point, scale to apply + to generated texture coordinates. + + + +GA:GA_LINE_STIPPLE_VALUE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4260 +DESCRIPTION: Current value of stipple accumulator. +Field Name Bits Default Description +STIPPLE_VALUE 31:0 0x0 24b Integer, measuring stipple accumulation in subpixels + (1/12 or 1/16, even in 8b precision). (note: field is 32b, + but only lower 24b used) + + + +GA:GA_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4290 +DESCRIPTION: Specifies x & y offsets for vertex data after conversion to FP. +Field Name Bits Default Description +X_OFFSET 15:0 0x0 Specifies X offset in S15 format (subpixels -- 1/12 or + 1/16, even in 8b subprecision). +Y_OFFSET 31:16 0x0 Specifies Y offset in S15 format (subpixels -- 1/12 or + 1/16, even in 8b subprecision). + + + +GA:GA_POINT_MINMAX · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4230 +DESCRIPTION: Specifies maximum and minimum point & sprite sizes for per vertex size specification. +Field Name Bits Default Description +MIN_SIZE 15:0 0x0 Minimum point & sprite radius (in subsamples) size to + allow. +MAX_SIZE 31:16 0x0 Maximum point & sprite radius (in subsamples) size to + allow. + + + +GA:GA_POINT_S0 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4200 +DESCRIPTION: S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) +Field Name Bits Default Description +S0 31:0 0x0 S texture coordinate of vertex 0 for point; 32-bit IEEE + float format. + + + +GA:GA_POINT_S1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4208 +DESCRIPTION: S Texture Coordinate of Vertex 2 for Point texture stuffing (URC) + +© 2008 Advanced Micro Devices, Inc. +Proprietary 180 + Revision 1.4 October 13, 2009 + + + + +Field Name Bits Default Description +S1 31:0 0x0 S texture coordinate of vertex 2 for point; 32-bit IEEE + float format. + + + +GA:GA_POINT_SIZE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x421c +DESCRIPTION: Dimensions for Points +Field Name Bits Default Description +HEIGHT 15:0 0x0 1/2 Height of point; fixed (16.0), subpixel format (1/12 + or 1/16, even if in 8b precision). +WIDTH 31:16 0x0 1/2 Width of point; fixed (16.0), subpixel format (1/12 or + 1/16, even if in 8b precision) + + + +GA:GA_POINT_T0 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4204 +DESCRIPTION: T Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) +Field Name Bits Default Description +T0 31:0 0x0 T texture coordinate of vertex 0 for point; 32-bit IEEE + float format. + + + +GA:GA_POINT_T1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x420c +DESCRIPTION: T Texture Coordinate of Vertex 2 for Point texture stuffing (URC) +Field Name Bits Default Description +T1 31:0 0x0 T texture coordinate of vertex 2 for point; 32-bit IEEE + float format. + + + +GA:GA_POLY_MODE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4288 +DESCRIPTION: Polygon Mode +Field Name Bits Default Description +POLY_MODE 1:0 0x0 Polygon mode enable. + + POSSIBLE VALUES: + 00 - Disable poly mode (render triangles). + 01 - Dual mode (send 2 sets of 3 polys with specified + poly type). + 02 - Reserved +FRONT_PTYPE 6:4 0x0 Specifies how to render front-facing polygons. + + POSSIBLE VALUES: + 00 - Draw points. + 01 - Draw lines. + 02 - Draw triangles. + 03 - Reserved 3 - 7. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 181 + Revision 1.4 October 13, 2009 + + + + +BACK_PTYPE 9:7 0x0 Specifies how to render back-facing polygons. + + POSSIBLE VALUES: + 00 - Draw points. + 01 - Draw lines. + 02 - Draw triangles. + 03 - Reserved 3 - 7. + + + +GA:GA_ROUND_MODE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x428c +DESCRIPTION: Specifies the rouding mode for geometry & color SPFP to FP conversions. +Field Name Bits Default Description +GEOMETRY_ROUND 1:0 0x0 Trunc (0) or round to nearest (1) for geometry (XY). + + POSSIBLE VALUES: + 00 - Round to trunc + 01 - Round to nearest +COLOR_ROUND 3:2 0x0 When set, FP32 to FP20 using round to nearest; + otherwise trunc + + POSSIBLE VALUES: + 00 - Round to trunc + 01 - Round to nearest +RGB_CLAMP 4 0x0 Specifies SPFP color clamp range of [0,1] or FP20 for + RGB. + + POSSIBLE VALUES: + 00 - Clamp to [0,1.0] for RGB + 01 - RGB is FP20 +ALPHA_CLAMP 5 0x0 Specifies SPFP alpha clamp range of [0,1] or FP20. + + POSSIBLE VALUES: + 00 - Clamp to [0,1.0] for Alpha + 01 - Alpha is FP20 +GEOMETRY_MASK 9:6 0x0 4b negative polarity mask for subpixel precision. + Inverted version gets ANDed with subpixel X, Y masks. + + + +GA:GA_SOLID_BA · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4280 +DESCRIPTION: Specifies blue & alpha components of fill color -- S312 format -- Backwards comp. +Field Name Bits Default Description +COLOR_ALPHA 15:0 0x0 Component alpha value. (S3.12) +COLOR_BLUE 31:16 0x0 Component blue value. (S3.12) + + + +GA:GA_SOLID_RG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x427c + +© 2008 Advanced Micro Devices, Inc. +Proprietary 182 + Revision 1.4 October 13, 2009 + + + + +DESCRIPTION: Specifies red & green components of fill color -- S312 format -- Backwards comp. +Field Name Bits Default Description +COLOR_GREEN 15:0 0x0 Component green value (S3.12). +COLOR_RED 31:16 0x0 Component red value (S3.12). + + + +GA:GA_TRIANGLE_STIPPLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4214 +DESCRIPTION: Specifies amount to shift integer position of vertex (screen space) before converting to float for +triangle stipple. +Field Name Bits Default Description +X_SHIFT 3:0 0x0 Amount to shift x position before conversion to SPFP. +Y_SHIFT 19:16 0x0 Amount to shift y position before conversion to SPFP. + + + +GA:GA_US_VECTOR_DATA · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4254 +DESCRIPTION: Data register for loading US instructions and constants +Field Name Bits Default Description +DATA 31:0 0x0 32 bit dword + + + +GA:GA_US_VECTOR_INDEX · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4250 +DESCRIPTION: Used to load US instructions and constants +Field Name Bits Default Description +INDEX 8:0 0x0 Instruction (TYPE == GA_US_VECTOR_INST) or + constant (TYPE == GA_US_VECTOR_CONST) + number at which to start loading. The GA will then + expect n*6 (instructions) or n*4 (constants) writes to + GA_US_VECTOR_DATA. The GA will self-increment + until this register is written again. For instructions, the + GA expects the dwords in the following order: + US_CMN_INST, US_ALU_RGB_ADDR, + US_ALU_ALPHA_ADDR, US_ALU_ALPHA, + US_RGB_INST, US_ALPHA_INST, US_RGBA_INST. + For constants, the GA expects the dwords in RGBA + order. +TYPE 16 0x0 Specifies if the GA should load instructions or constants. + + POSSIBLE VALUES: + 00 - Load instructions - INDEX is an instruction + index + 01 - Load constants - INDEX is a constant index +CLAMP 17 0x0 POSSIBLE VALUES: + 00 - No clamping of data - Default + 01 - Clamp to [-1.0,1.0] constant data + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 183 + Revision 1.4 October 13, 2009 + + + + +11.5 Graphics Backend Registers + +GB:GB_AA_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4020 +DESCRIPTION: Specifies the graphics pipeline configuration for antialiasing. +Field Name Bits Default Description +AA_ENABLE 0 0x0 Enables antialiasing. + + POSSIBLE VALUES: + 00 - Antialiasing disabled(def) + 01 - Antialiasing enabled +NUM_AA_SUBSAMPLES 2:1 0x0 Specifies the number of subsamples to use while + antialiasing. + + POSSIBLE VALUES: + 00 - 2 subsamples + 01 - 3 subsamples + 02 - 4 subsamples + 03 - 6 subsamples + + + +GB:GB_ENABLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4008 +DESCRIPTION: Specifies top of Raster pipe specific enable controls. +Field Name Bits Default Description +POINT_STUFF_ENABLE 0 0x0 Specifies if points will have stuffed texture coordinates. + + POSSIBLE VALUES: + 00 - Disable point texture stuffing. + 01 - Enable point texture stuffing. +LINE_STUFF_ENABLE 1 0x0 Specifies if lines will have stuffed texture coordinates. + + POSSIBLE VALUES: + 00 - Disable line texture stuffing. + 01 - Enable line texture stuffing. +TRIANGLE_STUFF_ENABLE 2 0x0 Specifies if triangles will have stuffed texture + coordinates. + + POSSIBLE VALUES: + 00 - Disable triangle texture stuffing. + 01 - Enable triangle texture stuffing. +STENCIL_AUTO 5:4 0x0 Specifies if the auto dec/inc stencil mode should be + enabled, and how. + + POSSIBLE VALUES: + 00 - Disable stencil auto inc/dec (def). + 01 - Enable stencil auto inc/dec based on triangle + cw/ccw, force into dzy low bit. + 02 - Force 0 into dzy low bit. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 184 + Revision 1.4 October 13, 2009 + + + + +TEX0_SOURCE 17:16 0x0 Specifies the sources of the texture coordinates for each + texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX1_SOURCE 19:18 0x0 Specifies the sources of the texture coordinates for each + texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX2_SOURCE 21:20 0x0 Specifies the sources of the texture coordinates for each + texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX3_SOURCE 23:22 0x0 Specifies the sources of the texture coordinates for each + texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX4_SOURCE 25:24 0x0 Specifies the sources of the texture coordinates for each + texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX5_SOURCE 27:26 0x0 Specifies the sources of the texture coordinates for each + texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX6_SOURCE 29:28 0x0 Specifies the sources of the texture coordinates for each + texture. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 185 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX7_SOURCE 31:30 0x0 Specifies the sources of the texture coordinates for each + texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). + + + +GB:GB_FIFO_SIZE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4024 +DESCRIPTION: Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written +Field Name Bits Default Description +SC_IFIFO_SIZE 1:0 0x0 Size of scan converter input FIFO (XYZ) + + POSSIBLE VALUES: + 00 - 32 words + 01 - 64 words + 02 - 128 words + 03 - 256 words +SC_TZFIFO_SIZE 3:2 0x0 Size of scan converter top-of-pipe Z FIFO + + POSSIBLE VALUES: + 00 - 16 words + 01 - 32 words + 02 - 64 words + 03 - 128 words +SC_BFIFO_SIZE 5:4 0x0 Size of scan converter input FIFO (B) + + POSSIBLE VALUES: + 00 - 32 words + 01 - 64 words + 02 - 128 words + 03 - 256 words +RS_TFIFO_SIZE 7:6 0x0 Size of ras input FIFO (Texture) + + POSSIBLE VALUES: + 00 - 64 words + 01 - 128 words + 02 - 256 words + 03 - 512 words +RS_CFIFO_SIZE 9:8 0x0 Size of ras input FIFO (Color) + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 186 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - 64 words + 01 - 128 words + 02 - 256 words + 03 - 512 words +US_RAM_SIZE 11:10 0x0 Size of us RAM + + POSSIBLE VALUES: + 00 - 64 words + 01 - 128 words + 02 - 256 words + 03 - 512 words +US_OFIFO_SIZE 13:12 0x0 Size of us output FIFO (RGBA) + + POSSIBLE VALUES: + 00 - 16 words + 01 - 32 words + 02 - 64 words + 03 - 128 words +US_WFIFO_SIZE 15:14 0x0 Size of us output FIFO (W) + + POSSIBLE VALUES: + 00 - 16 words + 01 - 32 words + 02 - 64 words + 03 - 128 words +RS_HIGHWATER_COL 18:16 0x0 High water mark for RS colors` fifo -- NOT USED +RS_HIGHWATER_TEX 21:19 0x0 High water mark for RS textures` fifo -- NOT USED +US_OFIFO_HIGHWATER 23:22 0x0 High water mark for US output fifo + + POSSIBLE VALUES: + 00 - 0 words + 01 - 4 words + 02 - 8 words + 03 - 12 words +US_CUBE_FIFO_HIGHWATER 28:24 0x0 High water mark for US cube map fifo + + + +GB:GB_FIFO_SIZE1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4070 +DESCRIPTION: Specifies the sizes of the various FIFO`s in the sc/rs. +Field Name Bits Default Description +SC_HIGHWATER_IFIFO 5:0 0x0 High water mark for SC input fifo +SC_HIGHWATER_BFIFO 11:6 0x0 High water mark for SC input fifo (B) +RS_HIGHWATER_COL 17:12 0x0 High water mark for RS colors` fifo +RS_HIGHWATER_TEX 23:18 0x0 High water mark for RS textures` fifo + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 187 + Revision 1.4 October 13, 2009 + + + + +GB:GB_MSPOS0 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4010 +DESCRIPTION: Specifies the position of multisamples 0 through 2 +Field Name Bits Default Description +MS_X0 3:0 0x0 Specifies the x and y position (in subpixels) of + multisample 0 +MS_Y0 7:4 0x0 Specifies the x and y position (in subpixels) of + multisample 0 +MS_X1 11:8 0x0 Specifies the x and y position (in subpixels) of + multisample 1 +MS_Y1 15:12 0x0 Specifies the x and y position (in subpixels) of + multisample 1 +MS_X2 19:16 0x0 Specifies the x and y position (in subpixels) of + multisample 2 +MS_Y2 23:20 0x0 Specifies the x and y position (in subpixels) of + multisample 2 +MSBD0_Y 27:24 0x0 Specifies the minimum x and y distance (in subpixels) + between the pixel edge and the multisamples. These + values are used in the first (coarse) scan converter +MSBD0_X 31:28 0x0 Specifies the minimum x and y distance (in subpixels) + between the pixel edge and the multisamples. These + values are used in the first (coarse) scan converter + + + +GB:GB_MSPOS1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4014 +DESCRIPTION: Specifies the position of multisamples 3 through 5 +Field Name Bits Default Description +MS_X3 3:0 0x0 Specifies the x and y position (in subpixels) of + multisample 3 +MS_Y3 7:4 0x0 Specifies the x and y position (in subpixels) of + multisample 3 +MS_X4 11:8 0x0 Specifies the x and y position (in subpixels) of + multisample 4 +MS_Y4 15:12 0x0 Specifies the x and y position (in subpixels) of + multisample 4 +MS_X5 19:16 0x0 Specifies the x and y position (in subpixels) of + multisample 5 +MS_Y5 23:20 0x0 Specifies the x and y position (in subpixels) of + multisample 5 +MSBD1 27:24 0x0 Specifies the minimum distance (in subpixels) between + the pixel edge and the multisamples. This value is used + in the second (quad) scan converter + + + +GB:GB_PIPE_SELECT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x402c +DESCRIPTION: Selects which of 4 pipes are active. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 188 + Revision 1.4 October 13, 2009 + + + + +Field Name Bits Default Description +PIPE0_ID 1:0 0x0 Maps physical pipe 0 to logical pipe ID (def 0). +PIPE1_ID 3:2 0x1 Maps physical pipe 1 to logical pipe ID (def 1). +PIPE2_ID 5:4 0x2 Maps physical pipe 2 to logical pipe ID (def 2). +PIPE3_ID 7:6 0x3 Maps physical pipe 3 to logical pipe ID (def 3). +PIPE_MASK 11:8 0x0 4b mask, indicates which physical pipes are enabled (def + none=0x0) -- B3=P3, B2=P2, B1=P1, B0=P0. -- 1: + enabled, 0: disabled +MAX_PIPE 13:12 0x3 2b, indicates, by the fuses, the max number of allowed + pipes. 0 = 1 pipe ... 3 = 4 pipes -- Read Only +BAD_PIPES 17:14 0xF 4b, indicates, by the fuses, the bad pipes: B3=P3, B2=P2, + B1=P1, B0=P0 -- 1: bad, 0: good -- Read Only +CONFIG_PIPES 18 0x0 If this bit is set when writing this register, the logical + pipe ID values are assigned automatically based on the + values that are read back in the MAX_PIPE and + BAD_PIPES fields. This field is always read back as 0. + + POSSIBLE VALUES: + 00 - Do nothing + 01 - Force self-configuration + + + +GB:GB_SELECT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x401c +DESCRIPTION: Specifies various polygon specific selects (fog, depth, perspective). +Field Name Bits Default Description +FOG_SELECT 2:0 0x0 Specifies source for outgoing (GA to SU) fog value. + + POSSIBLE VALUES: + 00 - Select C0A + 01 - Select C1A + 02 - Select C2A + 03 - Select C3A + 04 - Select 1/(1/W) + 05 - Select Z +DEPTH_SELECT 3 0x0 Specifies source for outgoing (GA/SU & SU/RAS) depth + value. + + POSSIBLE VALUES: + 00 - Select Z + 01 - Select 1/(1/W) +W_SELECT 4 0x0 Specifies source for outgoing (1/W) value, used to + disable perspective correct colors/textures. + + POSSIBLE VALUES: + 00 - Select (1/W) + 01 - Select 1.0 +FOG_STUFF_ENABLE 5 0x0 Controls enabling of fog stuffing into texture coordinate. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 189 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Disable fog texture stuffing + 01 - Enable fog texture stuffing +FOG_STUFF_TEX 9:6 0x0 Controls which texture gets fog value +FOG_STUFF_COMP 11:10 0x0 Controls which component of texture gets fog value + + + +GB:GB_TILE_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4018 +DESCRIPTION: Specifies the graphics pipeline configuration for rasterization +Field Name Bits Default Description +ENABLE 0 0x1 Enables tiling, otherwise all tiles receive all polygons. + + POSSIBLE VALUES: + 00 - Tiling disabled. + 01 - Tiling enabled (def). +PIPE_COUNT 3:1 0x0 Specifies the number of active pipes and contexts (up to + 4 pipes, 1 ctx). When this field is written, it is + automatically reduced by hardware so as not to use more + pipes than the number indicated in + GB_PIPE_SELECT.MAX_PIPES or the number of + pipes left unmasked GB_PIPE_SELECT.BAD_PIPES. + The potentially altered value is read back, rather than the + original value written by software. + + POSSIBLE VALUES: + 00 - RV350 (1 pipe, 1 ctx) + 03 - R300 (2 pipes, 1 ctx) + 06 – R420-3P (3 pipes, 1 ctx) + 07 – R420 (4 pipes, 1 ctx) +TILE_SIZE 5:4 0x1 Specifies width & height (square), in pixels (only 16, 32 + available). + + POSSIBLE VALUES: + 00 - 8 pixels. + 01 - 16 pixels. + 02 - 32 pixels. +SUPER_SIZE 8:6 0x0 Specifies number of tiles and config in super chip + configuration. + + POSSIBLE VALUES: + 00 - 1x1 tile (one 1x1). + 01 - 2 tiles (two 1x1 : ST-A,B). + 02 - 4 tiles (one 2x2). + 03 - 8 tiles (two 2x2 : ST-A,B). + 04 - 16 tiles (one 4x4). + 05 - 32 tiles (two 4x4 : ST-A,B). + 06 - 64 tiles (one 8x8). + 07 - 128 tiles (two 8x8 : ST-A,B). + +© 2008 Advanced Micro Devices, Inc. +Proprietary 190 + Revision 1.4 October 13, 2009 + + + + +SUPER_X 11:9 0x0 X Location of chip within super tile. +SUPER_Y 14:12 0x0 Y Location of chip within super tile. +SUPER_TILE 15 0x0 Tile location of chip in a multi super tile config (Super + size of 2,8,32 or 128). + + POSSIBLE VALUES: + 00 - ST-A tile. + 01 - ST-B tile. +SUBPIXEL 16 0x0 Specifies the precision of subpixels wrt pixels (12 or 16). + + POSSIBLE VALUES: + 00 - Select 1/12 subpixel precision. + 01 - Select 1/16 subpixel precision. +QUADS_PER_RAS 18:17 0x0 Specifies the number of quads to be sent to each + rasterizer in turn when in RV300B or R300B mode + + POSSIBLE VALUES: + 00 - 4 Quads + 01 - 8 Quads + 02 - 16 Quads + 03 - 32 Quads +BB_SCAN 19 0x0 Specifies whether to use an intercept or bounding box + based calculation for the first (coarse) scan converter + + POSSIBLE VALUES: + 00 - Use intercept based scan converter + 01 - Use bounding box based scan converter +ALT_SCAN_EN 20 0x0 Specifies whether to use an altenate scan pattern for the + coarse scan converter + + POSSIBLE VALUES: + 00 - Use normal left-right scan + 01 - Use alternate left-right-left scan +ALT_OFFSET 21 0x0 Not used -- should be 0 + + POSSIBLE VALUES: + 00 - Not used + 01 - Not used +SUBPRECISION 22 0x0 Set to 0 +ALT_TILING 23 0x0 Support for 3x2 tiling in 3P mode + + POSSIBLE VALUES: + 00 - Use default tiling in all tiling modes + 01 - Use alternative 3x2 tiling in 3P mode +Z_EXTENDED 24 0x0 Support for extended setup Z range from [0,1] to [-2,2] + with per pixel clamping + + POSSIBLE VALUES: + +© 2008 Advanced Micro Devices, Inc. +Proprietary 191 + Revision 1.4 October 13, 2009 + + + + + 00 - Use (24.1) Z format, with vertex clamp to + [1.0,0.0] + 01 - Use (S25.1) format, with vertex clamp to [2.0,- + 2.0] and per pixel [1.0,0.0] + + + +GB:GB_Z_PEQ_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4028 +DESCRIPTION: Specifies the z plane equation configuration. +Field Name Bits Default Description +Z_PEQ_SIZE 0 0x0 Specifies the z plane equation size. + + POSSIBLE VALUES: + 00 - 4x4 z plane equations (point-sampled or aa) + 01 - 8x8 z plane equations (point-sampled only) + + + +GB:PS3_ENABLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4118 +DESCRIPTION: PS3 mode enable register +Field Name Bits Default Description +PS3_MODE 0 0x0 When reset (default), follows R300/PS2 mode; when set, + allows for new ps3 mode. + + POSSIBLE VALUES: + 00 - Default PS2 mode + 01 - New PS3 mode + + +GB:PS3_TEX_SOURCE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4120 +DESCRIPTION: Specifies source for texture components in PS3 mode +Field Name Bits Default Description +TEX0_SOURCE 1:0 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX1_SOURCE 3:2 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + +© 2008 Advanced Micro Devices, Inc. +Proprietary 192 + Revision 1.4 October 13, 2009 + + + + + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX2_SOURCE 5:4 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX3_SOURCE 7:6 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX4_SOURCE 9:8 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX5_SOURCE 11:10 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX6_SOURCE 13:12 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX7_SOURCE 15:14 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 193 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX8_SOURCE 17:16 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). +TEX9_SOURCE 19:18 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing + for each texture. + + POSSIBLE VALUES: + 00 - Replicate VAP source texture coordinates + (S,T,[R,Q]). + 01 - Stuff with source texture coordinates (S,T). + 02 - Stuff with source texture coordinates (S,T,R). + + +GB:PS3_VTX_FMT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x411c +DESCRIPTION: PS3 vertex format register +Field Name Bits Default Description +TEX_0_COMP_CNT 2:0 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_1_COMP_CNT 5:3 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 194 + Revision 1.4 October 13, 2009 + + + + + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_2_COMP_CNT 8:6 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_3_COMP_CNT 11:9 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_4_COMP_CNT 14:12 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_5_COMP_CNT 17:15 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_6_COMP_CNT 20:18 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 195 + Revision 1.4 October 13, 2009 + + + + + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_7_COMP_CNT 23:21 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_8_COMP_CNT 26:24 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_9_COMP_CNT 29:27 0x0 How many active components (0,1,2,3,4) are in each + texture. + + POSSIBLE VALUES: + 00 - Not active + 01 - 1 component (VAP/GA), 2 component (GA/SU) + 02 - 2 component (VAP/GA), 2 component (GA/SU) + 03 - 3 component (VAP/GA), 3 component (GA/SU) + 04 - 4 component (VAP/GA), 4 component (GA/SU) +TEX_10_COMP_CNT 31:30 0x0 How many active components (0,2,3,4) are in texture 10. + + POSSIBLE VALUES: + 00 - Not active + 01 - 2 component (GA/SU) + 02 - 3 component (GA/SU) + 03 - 4 component (GA/SU) + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 196 + Revision 1.4 October 13, 2009 + + + + +11.6 Rasterizer Registers + +RS:RS_COUNT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4300 +DESCRIPTION: This register specifies the rasterizer input packet configuration +Field Name Bits Default Description +IT_COUNT 6:0 0x0 Specifies the total number of texture address components + contained in the rasterizer input packet (0:32). +IC_COUNT 10:7 0x0 Specifies the total number of colors contained in the + rasterizer input packet (0:4). +W_ADDR 17:12 0x0 Specifies the relative rasterizer input packet location of w + (if w_count==1) +HIRES_EN 18 0x0 Enable high resolution texture coordinate output when q + is equal to 1 + + + +RS:RS_INST_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4320-0x435c +DESCRIPTION: This table specifies what happens during each rasterizer instruction +Field Name Bits Default Description +TEX_ID 3:0 0x0 Specifies the index (into the RS_IP table) of the texture + address output during this rasterizer instruction +TEX_CN 4 0x0 Write enable for texture address + + POSSIBLE VALUES: + 00 - No write - texture coordinate not valid + 01 - write - texture valid +TEX_ADDR 11:5 0x0 Specifies the destination address (within the current pixel + stack frame) of the texture address output during this + rasterizer instruction +COL_ID 15:12 0x0 Specifies the index (into the RS_IP table) of the color + output during this rasterizer instruction +COL_CN 17:16 0x0 Write enable for color + + POSSIBLE VALUES: + 00 - No write - color not valid + 01 - write - color valid + 02 - write fbuffer - XY00->RGBA + 03 - write backface - B000->RGBA +COL_ADDR 24:18 0x0 Specifies the destination address (within the current pixel + stack frame) of the color output during this rasterizer + instruction +TEX_ADJ 25 0x0 Specifies whether to sample texture coordinates at the + real or adjusted pixel centers + + POSSIBLE VALUES: + 00 - Sample texture coordinates at real pixel centers + +© 2008 Advanced Micro Devices, Inc. +Proprietary 197 + Revision 1.4 October 13, 2009 + + + + + 01 - Sample texture coordinates at adjusted pixel + centers +W_CN 26 0x0 Specifies that the rasterizer should output w + + POSSIBLE VALUES: + 00 - No write - w not valid + 01 - write - w valid + + + +RS:RS_INST_COUNT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4304 +DESCRIPTION: This register specifies the number of rasterizer instructions +Field Name Bits Default Description +INST_COUNT 3:0 0x0 Number of rasterizer instructions (1:16) +TX_OFFSET 7:5 0x0 Indicates range of texture offset to minimize peroidic + errors on texels sampled right on their edges + + + +RS:RS_IP_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4074-0x40b0 +DESCRIPTION: This table specifies the source location and format for up to 16 texture addresses (i[0]:i[15]) and +four colors (c[0]:c[3]) +Field Name Bits Default Description +TEX_PTR_S 5:0 0x0 Specifies the relative rasterizer input packet location of + each component (S, T, R, and Q) of texture address (i[i]). + The values 62 and 63 select constant inputs for the + component: 62 selects K0 (0.0), and 63 selects K1 (1.0). +TEX_PTR_T 11:6 0x0 Specifies the relative rasterizer input packet location of + each component (S, T, R, and Q) of texture address (i[i]). + The values 62 and 63 select constant inputs for the + component: 62 selects K0 (0.0), and 63 selects K1 (1.0). +TEX_PTR_R 17:12 0x0 Specifies the relative rasterizer input packet location of + each component (S, T, R, and Q) of texture address (i[i]). + The values 62 and 63 select constant inputs for the + component: 62 selects K0 (0.0), and 63 selects K1 (1.0). +TEX_PTR_Q 23:18 0x0 Specifies the relative rasterizer input packet location of + each component (S, T, R, and Q) of texture address (i[i]). + The values 62 and 63 select constant inputs for the + component: 62 selects K0 (0.0), and 63 selects K1 (1.0). +COL_PTR 26:24 0x0 Specifies the relative rasterizer input packet location of + the color (c[i]). +COL_FMT 30:27 0x0 Specifies the format of the color (c[i]). + + POSSIBLE VALUES: + 00 - Four components (R,G,B,A) + 01 - Three components (R,G,B,0) + 02 - Three components (R,G,B,1) + 04 - One component (0,0,0,A) + 05 - Zero components (0,0,0,0) + +© 2008 Advanced Micro Devices, Inc. +Proprietary 198 + Revision 1.4 October 13, 2009 + + + + + 06 - Zero components (0,0,0,1) + 08 - One component (1,1,1,A) + 09 - Zero components (1,1,1,0) + 10 - Zero components (1,1,1,1) +OFFSET_EN 31 0x0 Enable application of the TX_OFFSET in + RS_INST_COUNT + + POSSIBLE VALUES: + 00 - Do not apply the TX_OFFSET in + RS_INST_COUNT + 01 - Apply the TX_OFFSET specified by + RS_INST_COUNT + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 199 + Revision 1.4 October 13, 2009 + + + + +11.7 Clipping Registers +SC:SC_CLIP_0_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43b0 +DESCRIPTION: OpenGL Clip rectangles +Field Name Bits Default Description +XS0 12:0 0x0 Left hand edge of clip rectangle +YS0 25:13 0x0 Upper edge of clip rectangle + + + +SC:SC_CLIP_0_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43b4 +DESCRIPTION: OpenGL Clip rectangles +Field Name Bits Default Description +XS1 12:0 0x0 Right hand edge of clip rectangle +YS1 25:13 0x0 Lower edge of clip rectangle + + + +SC:SC_CLIP_1_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43b8 +Field Name Bits Default Description +XS0 12:0 0x0 +YS0 25:13 0x0 + + + +SC:SC_CLIP_1_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43bc +Field Name Bits Default Description +XS1 12:0 0x0 +YS1 25:13 0x0 + + + +SC:SC_CLIP_2_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43c0 +Field Name Bits Default Description +XS0 12:0 0x0 +YS0 25:13 0x0 + + + +SC:SC_CLIP_2_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43c4 +Field Name Bits Default Description +XS1 12:0 0x0 +YS1 25:13 0x0 + + + +SC:SC_CLIP_3_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43c8 +Field Name Bits Default Description + +© 2008 Advanced Micro Devices, Inc. +Proprietary 200 + Revision 1.4 October 13, 2009 + + + + +XS0 12:0 0x0 +YS0 25:13 0x0 + + + +SC:SC_CLIP_3_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43cc +Field Name Bits Default Description +XS1 12:0 0x0 +YS1 25:13 0x0 + + + +SC:SC_CLIP_RULE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43d0 +DESCRIPTION: OpenGL Clip boolean function +Field Name Bits Default Description +CLIP_RULE 15:0 0x0 OpenGL Clip boolean function. The `inside` flags for + each of the four clip rectangles form a 4-bit binary + number. The corresponding bit in this 16-bit number + specifies whether the pixel is visible. + + + +SC:SC_EDGERULE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43a8 +DESCRIPTION: Edge rules - what happens when an edge falls exactly on a sample point +Field Name Bits Default Description +ER_TRI 4:0 0x0 Edge rules for triangles, points, left-right lines, right-left + lines, upper-bottom lines, bottom-upper lines. For values + 0 to 15, bit 0 specifies whether a sample on a horizontal- + bottom edge is in, bit 1 specifies whether a sample on a + horizontal-top edge is in, bit 2 species whether a sample + on a right edge is in, bit 3 specifies whether a sample on + a left edge is in. For values 16 to 31, bit 0 specifies + whether a sample on a vertical-right edge is in, bit 1 + specifies whether a sample on a vertical-left edge is in, + bit 2 species whether a sample on a bottom edge is in, bit + 3 specifies whether a sample on a top edge is in + + POSSIBLE VALUES: + 00 - L-in,R-in,HT-in,HB-in + 01 - L-in,R-in,HT-in,HB-out + 02 - L-in,R-in,HT-out,HB-in + 03 - L-in,R-in,HT-out,HB-out + 04 - L-in,R-out,HT-in,HB-in + 05 - L-in,R-out,HT-in,HB-out + 06 - L-in,R-out,HT-out,HB-in + 07 - L-in,R-out,HT-out,HB-out + 08 - L-out,R-in,HT-in,HB-in + 09 - L-out,R-in,HT-in,HB-out + 10 - L-out,R-in,HT-out,HB-in + 11 - L-out,R-in,HT-out,HB-out + 12 - L-out,R-out,HT-in,HB-in + +© 2008 Advanced Micro Devices, Inc. +Proprietary 201 + Revision 1.4 October 13, 2009 + + + + + 13 - L-out,R-out,HT-in,HB-out + 14 - L-out,R-out,HT-out,HB-in + 15 - L-out,R-out,HT-out,HB-out + 16 - T-in,B-in,VL-in,VR-in + 17 - T-in,B-in,VL-in,VR-out + 18 - T-in,B-in,VL,VR-in + 19 - T-in,B-in,VL-out,VR-out + 20 - T-out,B-in,VL-in,VR-in + 21 - T-out,B-in,VL-in,VR-out + 22 - T-out,B-in,VL-out,VR-in + 23 - T-out,B-in,VL-out,VR-out + 24 - T-in,B-out,VL-in,VR-in + 25 - T-in,B-out,VL-in,VR-out + 26 - T-in,B-out,VL-out,VR-in + 27 - T-in,B-out,VL-out,VR-out + 28 - T-out,B-out,VL-in,VR-in + 29 - T-out,B-out,VL-in,VR-out + 30 - T-out,B-out,VL-out,VR-in + 31 - T-out,B-out,VL-out,VR-out +ER_POINT 9:5 0x0 Edge rules for triangles, points, left-right lines, right-left + lines, upper-bottom lines, bottom-upper lines. For values + 0 to 15, bit 0 specifies whether a sample on a horizontal- + bottom edge is in, bit 1 specifies whether a sample on a + horizontal-top edge is in, bit 2 species whether a sample + on a right edge is in, bit 3 specifies whether a sample on + a left edge is in. For values 16 to 31, bit 0 specifies + whether a sample on a vertical-right edge is in, bit 1 + specifies whether a sample on a vertical-left edge is in, + bit 2 species whether a sample on a bottom edge is in, bit + 3 specifies whether a sample on a top edge is in + + POSSIBLE VALUES: + 00 - L-in,R-in,HT-in,HB-in + 01 - L-in,R-in,HT-in,HB-out + 02 - L-in,R-in,HT-out,HB-in + 03 - L-in,R-in,HT-out,HB-out + 04 - L-in,R-out,HT-in,HB-in + 05 - L-in,R-out,HT-in,HB-out + 06 - L-in,R-out,HT-out,HB-in + 07 - L-in,R-out,HT-out,HB-out + 08 - L-out,R-in,HT-in,HB-in + 09 - L-out,R-in,HT-in,HB-out + 10 - L-out,R-in,HT-out,HB-in + 11 - L-out,R-in,HT-out,HB-out + 12 - L-out,R-out,HT-in,HB-in + 13 - L-out,R-out,HT-in,HB-out + 14 - L-out,R-out,HT-out,HB-in + 15 - L-out,R-out,HT-out,HB-out + 16 - T-in,B-in,VL-in,VR-in + 17 - T-in,B-in,VL-in,VR-out + 18 - T-in,B-in,VL,VR-in + 19 - T-in,B-in,VL-out,VR-out + 20 - T-out,B-in,VL-in,VR-in + +© 2008 Advanced Micro Devices, Inc. +Proprietary 202 + Revision 1.4 October 13, 2009 + + + + + 21 - T-out,B-in,VL-in,VR-out + 22 - T-out,B-in,VL-out,VR-in + 23 - T-out,B-in,VL-out,VR-out + 24 - T-in,B-out,VL-in,VR-in + 25 - T-in,B-out,VL-in,VR-out + 26 - T-in,B-out,VL-out,VR-in + 27 - T-in,B-out,VL-out,VR-out + 28 - T-out,B-out,VL-in,VR-in + 29 - T-out,B-out,VL-in,VR-out + 30 - T-out,B-out,VL-out,VR-in + 31 - T-out,B-out,VL-out,VR-out +ER_LINE_LR 14:10 0x0 Edge rules for triangles, points, left-right lines, right-left + lines, upper-bottom lines, bottom-upper lines. For values + 0 to 15, bit 0 specifies whether a sample on a horizontal- + bottom edge is in, bit 1 specifies whether a sample on a + horizontal-top edge is in, bit 2 species whether a sample + on a right edge is in, bit 3 specifies whether a sample on + a left edge is in. For values 16 to 31, bit 0 specifies + whether a sample on a vertical-right edge is in, bit 1 + specifies whether a sample on a vertical-left edge is in, + bit 2 species whether a sample on a bottom edge is in, bit + 3 specifies whether a sample on a top edge is in + + POSSIBLE VALUES: + 00 - L-in,R-in,HT-in,HB-in + 01 - L-in,R-in,HT-in,HB-out + 02 - L-in,R-in,HT-out,HB-in + 03 - L-in,R-in,HT-out,HB-out + 04 - L-in,R-out,HT-in,HB-in + 05 - L-in,R-out,HT-in,HB-out + 06 - L-in,R-out,HT-out,HB-in + 07 - L-in,R-out,HT-out,HB-out + 08 - L-out,R-in,HT-in,HB-in + 09 - L-out,R-in,HT-in,HB-out + 10 - L-out,R-in,HT-out,HB-in + 11 - L-out,R-in,HT-out,HB-out + 12 - L-out,R-out,HT-in,HB-in + 13 - L-out,R-out,HT-in,HB-out + 14 - L-out,R-out,HT-out,HB-in + 15 - L-out,R-out,HT-out,HB-out + 16 - T-in,B-in,VL-in,VR-in + 17 - T-in,B-in,VL-in,VR-out + 18 - T-in,B-in,VL,VR-in + 19 - T-in,B-in,VL-out,VR-out + 20 - T-out,B-in,VL-in,VR-in + 21 - T-out,B-in,VL-in,VR-out + 22 - T-out,B-in,VL-out,VR-in + 23 - T-out,B-in,VL-out,VR-out + 24 - T-in,B-out,VL-in,VR-in + 25 - T-in,B-out,VL-in,VR-out + 26 - T-in,B-out,VL-out,VR-in + 27 - T-in,B-out,VL-out,VR-out + 28 - T-out,B-out,VL-in,VR-in + +© 2008 Advanced Micro Devices, Inc. +Proprietary 203 + Revision 1.4 October 13, 2009 + + + + + 29 - T-out,B-out,VL-in,VR-out + 30 - T-out,B-out,VL-out,VR-in + 31 - T-out,B-out,VL-out,VR-out +ER_LINE_RL 19:15 0x0 Edge rules for triangles, points, left-right lines, right-left + lines, upper-bottom lines, bottom-upper lines. For values + 0 to 15, bit 0 specifies whether a sample on a horizontal- + bottom edge is in, bit 1 specifies whether a sample on a + horizontal-top edge is in, bit 2 species whether a sample + on a right edge is in, bit 3 specifies whether a sample on + a left edge is in. For values 16 to 31, bit 0 specifies + whether a sample on a vertical-right edge is in, bit 1 + specifies whether a sample on a vertical-left edge is in, + bit 2 species whether a sample on a bottom edge is in, bit + 3 specifies whether a sample on a top edge is in + + POSSIBLE VALUES: + 00 - L-in,R-in,HT-in,HB-in + 01 - L-in,R-in,HT-in,HB-out + 02 - L-in,R-in,HT-out,HB-in + 03 - L-in,R-in,HT-out,HB-out + 04 - L-in,R-out,HT-in,HB-in + 05 - L-in,R-out,HT-in,HB-out + 06 - L-in,R-out,HT-out,HB-in + 07 - L-in,R-out,HT-out,HB-out + 08 - L-out,R-in,HT-in,HB-in + 09 - L-out,R-in,HT-in,HB-out + 10 - L-out,R-in,HT-out,HB-in + 11 - L-out,R-in,HT-out,HB-out + 12 - L-out,R-out,HT-in,HB-in + 13 - L-out,R-out,HT-in,HB-out + 14 - L-out,R-out,HT-out,HB-in + 15 - L-out,R-out,HT-out,HB-out + 16 - T-in,B-in,VL-in,VR-in + 17 - T-in,B-in,VL-in,VR-out + 18 - T-in,B-in,VL,VR-in + 19 - T-in,B-in,VL-out,VR-out + 20 - T-out,B-in,VL-in,VR-in + 21 - T-out,B-in,VL-in,VR-out + 22 - T-out,B-in,VL-out,VR-in + 23 - T-out,B-in,VL-out,VR-out + 24 - T-in,B-out,VL-in,VR-in + 25 - T-in,B-out,VL-in,VR-out + 26 - T-in,B-out,VL-out,VR-in + 27 - T-in,B-out,VL-out,VR-out + 28 - T-out,B-out,VL-in,VR-in + 29 - T-out,B-out,VL-in,VR-out + 30 - T-out,B-out,VL-out,VR-in + 31 - T-out,B-out,VL-out,VR-out +ER_LINE_TB 24:20 0x0 Edge rules for triangles, points, left-right lines, right-left + lines, upper-bottom lines, bottom-upper lines. For values + 0 to 15, bit 0 specifies whether a sample on a horizontal- + bottom edge is in, bit 1 specifies whether a sample on a + +© 2008 Advanced Micro Devices, Inc. +Proprietary 204 + Revision 1.4 October 13, 2009 + + + + + horizontal-top edge is in, bit 2 species whether a sample + on a right edge is in, bit 3 specifies whether a sample on + a left edge is in. For values 16 to 31, bit 0 specifies + whether a sample on a vertical-right edge is in, bit 1 + specifies whether a sample on a vertical-left edge is in, + bit 2 species whether a sample on a bottom edge is in, bit + 3 specifies whether a sample on a top edge is in + + POSSIBLE VALUES: + 00 - L-in,R-in,HT-in,HB-in + 01 - L-in,R-in,HT-in,HB-out + 02 - L-in,R-in,HT-out,HB-in + 03 - L-in,R-in,HT-out,HB-out + 04 - L-in,R-out,HT-in,HB-in + 05 - L-in,R-out,HT-in,HB-out + 06 - L-in,R-out,HT-out,HB-in + 07 - L-in,R-out,HT-out,HB-out + 08 - L-out,R-in,HT-in,HB-in + 09 - L-out,R-in,HT-in,HB-out + 10 - L-out,R-in,HT-out,HB-in + 11 - L-out,R-in,HT-out,HB-out + 12 - L-out,R-out,HT-in,HB-in + 13 - L-out,R-out,HT-in,HB-out + 14 - L-out,R-out,HT-out,HB-in + 15 - L-out,R-out,HT-out,HB-out + 16 - T-in,B-in,VL-in,VR-in + 17 - T-in,B-in,VL-in,VR-out + 18 - T-in,B-in,VL,VR-in + 19 - T-in,B-in,VL-out,VR-out + 20 - T-out,B-in,VL-in,VR-in + 21 - T-out,B-in,VL-in,VR-out + 22 - T-out,B-in,VL-out,VR-in + 23 - T-out,B-in,VL-out,VR-out + 24 - T-in,B-out,VL-in,VR-in + 25 - T-in,B-out,VL-in,VR-out + 26 - T-in,B-out,VL-out,VR-in + 27 - T-in,B-out,VL-out,VR-out + 28 - T-out,B-out,VL-in,VR-in + 29 - T-out,B-out,VL-in,VR-out + 30 - T-out,B-out,VL-out,VR-in + 31 - T-out,B-out,VL-out,VR-out +ER_LINE_BT 29:25 0x0 Edge rules for triangles, points, left-right lines, right-left + lines, upper-bottom lines, bottom-upper lines. For values + 0 to 15, bit 0 specifies whether a sample on a horizontal- + bottom edge is in, bit 1 specifies whether a sample on a + horizontal-top edge is in, bit 2 species whether a sample + on a right edge is in, bit 3 specifies whether a sample on + a left edge is in. For values 16 to 31, bit 0 specifies + whether a sample on a vertical-right edge is in, bit 1 + specifies whether a sample on a vertical-left edge is in, + bit 2 species whether a sample on a bottom edge is in, bit + 3 specifies whether a sample on a top edge is in + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 205 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - L-in,R-in,HT-in,HB-in + 01 - L-in,R-in,HT-in,HB-out + 02 - L-in,R-in,HT-out,HB-in + 03 - L-in,R-in,HT-out,HB-out + 04 - L-in,R-out,HT-in,HB-in + 05 - L-in,R-out,HT-in,HB-out + 06 - L-in,R-out,HT-out,HB-in + 07 - L-in,R-out,HT-out,HB-out + 08 - L-out,R-in,HT-in,HB-in + 09 - L-out,R-in,HT-in,HB-out + 10 - L-out,R-in,HT-out,HB-in + 11 - L-out,R-in,HT-out,HB-out + 12 - L-out,R-out,HT-in,HB-in + 13 - L-out,R-out,HT-in,HB-out + 14 - L-out,R-out,HT-out,HB-in + 15 - L-out,R-out,HT-out,HB-out + 16 - T-in,B-in,VL-in,VR-in + 17 - T-in,B-in,VL-in,VR-out + 18 - T-in,B-in,VL,VR-in + 19 - T-in,B-in,VL-out,VR-out + 20 - T-out,B-in,VL-in,VR-in + 21 - T-out,B-in,VL-in,VR-out + 22 - T-out,B-in,VL-out,VR-in + 23 - T-out,B-in,VL-out,VR-out + 24 - T-in,B-out,VL-in,VR-in + 25 - T-in,B-out,VL-in,VR-out + 26 - T-in,B-out,VL-out,VR-in + 27 - T-in,B-out,VL-out,VR-out + 28 - T-out,B-out,VL-in,VR-in + 29 - T-out,B-out,VL-in,VR-out + 30 - T-out,B-out,VL-out,VR-in + 31 - T-out,B-out,VL-out,VR-out + + + +SC:SC_HYPERZ_EN · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43a4 +DESCRIPTION: Hierarchical Z Enable +Field Name Bits Default Description +HZ_EN 0 0x0 Enable for hierarchical Z. + + POSSIBLE VALUES: + 00 - Disables Hyper-Z. + 01 - Enables Hyper-Z. +HZ_MAX 1 0x0 Specifies whether to compute min or max z value + + POSSIBLE VALUES: + 00 - HZ block computes minimum z value + 01 - HZ block computes maximum z value +HZ_ADJ 4:2 0x0 Specifies adjustment to get added or subtracted from + +© 2008 Advanced Micro Devices, Inc. +Proprietary 206 + Revision 1.4 October 13, 2009 + + + + + computed z value + + POSSIBLE VALUES: + 00 - Add or Subtract 1/256 << ze + 01 - Add or Subtract 1/128 << ze + 02 - Add or Subtract 1/64 << ze + 03 - Add or Subtract 1/32 << ze + 04 - Add or Subtract 1/16 << ze + 05 - Add or Subtract 1/8 << ze + 06 - Add or Subtract 1/4 << ze + 07 - Add or Subtract 1/2 << ze +HZ_Z0MIN 5 0x0 Specifies whether vertex 0 z contains minimum z value + + POSSIBLE VALUES: + 00 - Vertex 0 does not contain minimum z value + 01 - Vertex 0 does contain minimum z value +HZ_Z0MAX 6 0x0 Specifies whether vertex 0 z contains maximum z value + + POSSIBLE VALUES: + 00 - Vertex 0 does not contain maximum z value + 01 - Vertex 0 does contain maximum z value + + + +SC:SC_SCISSOR0 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43e0 +DESCRIPTION: Scissor rectangle specification +Field Name Bits Default Description +XS0 12:0 0x0 Left hand edge of scissor rectangle +YS0 25:13 0x0 Upper edge of scissor rectangle + + + +SC:SC_SCISSOR1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43e4 +DESCRIPTION: Scissor rectangle specification +Field Name Bits Default Description +XS1 12:0 0x0 Right hand edge of scissor rectangle +YS1 25:13 0x0 Lower edge of scissor rectangle + + + +SC:SC_SCREENDOOR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43e8 +DESCRIPTION: Screen door sample mask +Field Name Bits Default Description +SCREENDOOR 23:0 0x0 Screen door sample mask - 1 means sample may be + covered, 0 means sample is not covered + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 207 + Revision 1.4 October 13, 2009 + + + + +11.8 Setup Unit Registers + +SU:SU_CULL_MODE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42b8 +DESCRIPTION: Culling Enables +Field Name Bits Default Description +CULL_FRONT 0 0x0 Enable for front-face culling. + + POSSIBLE VALUES: + 00 - Do not cull front-facing triangles. + 01 - Cull front-facing triangles. +CULL_BACK 1 0x0 Enable for back-face culling. + + POSSIBLE VALUES: + 00 - Do not cull back-facing triangles. + 01 - Cull back-facing triangles. +FACE 2 0x0 X-Ored with cross product sign to determine positive + facing + + POSSIBLE VALUES: + 00 - Positive cross product is front (CCW). + 01 - Negative cross product is front (CW). + + + +SU:SU_DEPTH_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42c4 +DESCRIPTION: SU Depth Offset value +Field Name Bits Default Description +OFFSET 31:0 0x0 SPFP Floating point applied to depth before conversion + to FXP. + + + +SU:SU_DEPTH_SCALE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42c0 +DESCRIPTION: SU Depth Scale value +Field Name Bits Default Description +SCALE 31:0 0x3F800000 SPFP Floating point applied to depth before conversion + to FXP. + + + +SU:SU_POLY_OFFSET_BACK_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42b0 +DESCRIPTION: Back-Facing Polygon Offset Offset +Field Name Bits Default Description +OFFSET 31:0 0x0 Specifies polygon offset offset for back-facing polygons; + 32b IEEE float format; applied after Z scale & offset (0 + to 2^24-1 range) + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 208 + Revision 1.4 October 13, 2009 + + + + +SU:SU_POLY_OFFSET_BACK_SCALE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42ac +DESCRIPTION: Back-Facing Polygon Offset Scale +Field Name Bits Default Description +SCALE 31:0 0x0 Specifies polygon offset scale for back-facing polygons; + 32-bit IEEE float format; applied after Z scale & offset + (0 to 2^24-1 range); slope computed in subpixels (1/12 or + 1/16) + + + +SU:SU_POLY_OFFSET_ENABLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42b4 +DESCRIPTION: Enables for polygon offset +Field Name Bits Default Description +FRONT_ENABLE 0 0x0 Enables front facing polygon`s offset. + + POSSIBLE VALUES: + 00 - Disable front offset. + 01 - Enable front offset. +BACK_ENABLE 1 0x0 Enables back facing polygon`s offset. + + POSSIBLE VALUES: + 00 - Disable back offset. + 01 - Enable back offset. +PARA_ENABLE 2 0x0 Forces all parallelograms to have FRONT_FACING for + poly offset -- Need to have FRONT_ENABLE also set to + have Z offset for parallelograms. + + POSSIBLE VALUES: + 00 - Disable front offset for parallelograms. + 01 - Enable front offset for parallelograms. + + + +SU:SU_POLY_OFFSET_FRONT_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42a8 +DESCRIPTION: Front-Facing Polygon Offset Offset +Field Name Bits Default Description +OFFSET 31:0 0x0 Specifies polygon offset offset for front-facing polygons; + 32b IEEE float format; applied after Z scale & offset (0 + to 2^24-1 range) + + + +SU:SU_POLY_OFFSET_FRONT_SCALE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42a4 +DESCRIPTION: Front-Facing Polygon Offset Scale +Field Name Bits Default Description +SCALE 31:0 0x0 Specifies polygon offset scale for front-facing polygons; + 32b IEEE float format; applied after Z scale & offset (0 + to 2^24-1 range); slope computed in subpixels (1/12 or + 1/16) + +© 2008 Advanced Micro Devices, Inc. +Proprietary 209 + Revision 1.4 October 13, 2009 + + + + +SU:SU_REG_DEST · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42c8 +DESCRIPTION: SU Raster pipe destination select for registers +Field Name Bits Default Description +SELECT 3:0 0xF Register read/write destination select: b0: logical pipe0, + b1: logical pipe1, b2: logical pipe2 and b3: logical pipe3 + + + +SU:SU_TEX_WRAP · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42a0 +DESCRIPTION: Enables for Cylindrical Wrapping +Field Name Bits Default Description +T0C0 0 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T0C1 1 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T0C2 2 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T0C3 3 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T1C0 4 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T1C1 5 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 210 + Revision 1.4 October 13, 2009 + + + + + 01 - Enable cylindrical wrapping. +T1C2 6 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T1C3 7 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T2C0 8 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T2C1 9 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T2C2 10 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T2C3 11 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T3C0 12 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T3C1 13 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 211 + Revision 1.4 October 13, 2009 + + + + +T3C2 14 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T3C3 15 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T4C0 16 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T4C1 17 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T4C2 18 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T4C3 19 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T5C0 20 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T5C1 21 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T5C2 22 0x0 tNcM -- Enable texture wrapping on component M + +© 2008 Advanced Micro Devices, Inc. +Proprietary 212 + Revision 1.4 October 13, 2009 + + + + + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T5C3 23 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T6C0 24 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T6C1 25 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T6C2 26 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T6C3 27 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T7C0 28 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T7C1 29 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T7C2 30 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 213 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T7C3 31 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. + + + +SU:SU_TEX_WRAP_PS3 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4114 +DESCRIPTION: Specifies texture wrapping for new PS3 textures. +Field Name Bits Default Description +T9C0 0 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T9C1 1 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T9C2 2 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T9C3 3 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C0 4 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C1 5 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 214 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C2 6 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C3 7 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. + + + +SU:SU_TEX_WRAP_PS3 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4114 +DESCRIPTION: Specifies texture wrapping for new PS3 textures. +Field Name Bits Default Description +T9C0 0 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T9C1 1 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T9C2 2 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T9C3 3 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 215 + Revision 1.4 October 13, 2009 + + + + + 01 - Enable cylindrical wrapping. +T8C0 4 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C1 5 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C2 6 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. +T8C3 7 0x0 tNcM -- Enable texture wrapping on component M + (S,T,R,Q) of texture N. + + POSSIBLE VALUES: + 00 - Disable cylindrical wrapping. + 01 - Enable cylindrical wrapping. + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 216 + Revision 1.4 October 13, 2009 + + + + +11.9 Texture Registers + +TX:TX_BORDER_COLOR_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x45c0-0x45fc +DESCRIPTION: Border Color +Field Name Bits Default Description +BORDER_COLOR 31:0 none Color used for borders. Format is the same as the texture + being bordered. + + + +TX:TX_CHROMA_KEY_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4580-0x45bc +DESCRIPTION: Texture Chroma Key +Field Name Bits Default Description +CHROMA_KEY 31:0 none Color used for chroma key compare. Format is the same + as the texture being keyed. + + + +TX:TX_ENABLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4104 +DESCRIPTION: Texture Enables for Maps 0 to 15 +Field Name Bits Default Description +TEX_0_ENABLE 0 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_1_ENABLE 1 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_2_ENABLE 2 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_3_ENABLE 3 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_4_ENABLE 4 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_5_ENABLE 5 none Texture Map Enables. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 217 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_6_ENABLE 6 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_7_ENABLE 7 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_8_ENABLE 8 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_9_ENABLE 9 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_10_ENABLE 10 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_11_ENABLE 11 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_12_ENABLE 12 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_13_ENABLE 13 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable +TEX_14_ENABLE 14 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 218 + Revision 1.4 October 13, 2009 + + + + + 01 - Enable +TEX_15_ENABLE 15 none Texture Map Enables. + + POSSIBLE VALUES: + 00 - Disable, ARGB = 1,0,0,0 + 01 - Enable + + + +TX:TX_FILTER0_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4400-0x443c +DESCRIPTION: Texture Filter State +Field Name Bits Default Description +CLAMP_S 2:0 none Clamp mode for texture coordinates + + POSSIBLE VALUES: + 00 - Wrap (repeat) + 01 - Mirror + 02 - Clamp to last texel (0.0 to 1.0) + 03 - MirrorOnce to last texel (-1.0 to 1.0) + 04 - Clamp half way to border color (0.0 to 1.0) + 05 - MirrorOnce half way to border color (-1.0 to 1.0) + 06 - Clamp to border color (0.0 to 1.0) + 07 - MirrorOnce to border color (-1.0 to 1.0) +CLAMP_T 5:3 none Clamp mode for texture coordinates + + POSSIBLE VALUES: + 00 - Wrap (repeat) + 01 - Mirror + 02 - Clamp to last texel (0.0 to 1.0) + 03 - MirrorOnce to last texel (-1.0 to 1.0) + 04 - Clamp half way to border color (0.0 to 1.0) + 05 - MirrorOnce half way to border color (-1.0 to 1.0) + 06 - Clamp to border color (0.0 to 1.0) + 07 - MirrorOnce to border color (-1.0 to 1.0) +CLAMP_R 8:6 none Clamp mode for texture coordinates + + POSSIBLE VALUES: + 00 - Wrap (repeat) + 01 - Mirror + 02 - Clamp to last texel (0.0 to 1.0) + 03 - MirrorOnce to last texel (-1.0 to 1.0) + 04 - Clamp half way to border color (0.0 to 1.0) + 05 - MirrorOnce half way to border color (-1.0 to 1.0) + 06 - Clamp to border color (0.0 to 1.0) + 07 - MirrorOnce to border color (-1.0 to 1.0) +MAG_FILTER 10:9 none Filter used when texture is magnified + + POSSIBLE VALUES: + 00 - Filter4 + 01 - Point + +© 2008 Advanced Micro Devices, Inc. +Proprietary 219 + Revision 1.4 October 13, 2009 + + + + + 02 - Linear + 03 - Reserved +MIN_FILTER 12:11 none Filter used when texture is minified + + POSSIBLE VALUES: + 00 - Filter4 + 01 - Point + 02 - Linear + 03 - Reserved +MIP_FILTER 14:13 none Filter used between mipmap levels + + POSSIBLE VALUES: + 00 - None + 01 - Point + 02 - Linear + 03 - Reserved +VOL_FILTER 16:15 none Filter used between layers of a volume + + POSSIBLE VALUES: + 00 - None (no filter specifed, select from MIN/MAG + filters) + 01 - Point + 02 - Linear + 03 - Reserved +MAX_MIP_LEVEL 20:17 none LOD index of largest (finest) mipmap to use (0 is + largest). Ranges from 0 to NUM_LEVELS. +Reserved 23:21 none +ID 31:28 none Logical id for this physical texture + + + +TX:TX_FILTER1_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4440-0x447c +DESCRIPTION: Texture Filter State +Field Name Bits Default Description +CHROMA_KEY_MODE 1:0 none Chroma Key Mode + + POSSIBLE VALUES: + 00 - Disable + 01 - ChromaKey (kill pixel if any sample matches + chroma key) + 02 - ChromaKeyBlend (set sample to 0 if it matches + chroma key) +MC_ROUND 2 none Bilinear rounding mode + + POSSIBLE VALUES: + 00 - Normal rounding on all components (+0.5) + 01 - MPEG4 rounding on all components (+0.25) +LOD_BIAS 12:3 none (s4.5). Ranges from -16.0 to 15.99. Mipmap LOD bias + measured in mipmap levels. Added to the signed, + +© 2008 Advanced Micro Devices, Inc. +Proprietary 220 + Revision 1.4 October 13, 2009 + + + + + computed LOD before the LOD is clamped. +Reserved 13 none +MC_COORD_TRUNCATE 14 none MPEG coordinate truncation mode + + POSSIBLE VALUES: + 00 - Dont truncate coordinate fractions. + 01 - Truncate coordinate fractions to 0.0 and 0.5 for + MPEG +TRI_PERF 16:15 none Apply slope and bias to trilerp fraction to reduce the + number of 2-level fetches for trilinear. Should only be + used if MIP_FILTER is LINEAR. + + POSSIBLE VALUES: + 00 - Breakpoint=0/8. lfrac_out = lfrac_in + 01 - Breakpoint=1/8. lfrac_out = clamp(4/3*lfrac_in - + 1/6) + 02 - Breakpoint=1/4. lfrac_out = clamp(2*lfrac_in - + 1/2) + 03 - Breakpoint=3/8. lfrac_out = clamp(4*lfrac_in - + 3/2) +Reserved 19:17 none Set to 0 +Reserved 20 none Set to 0 +Reserved 21 none Set to 0 +MACRO_SWITCH 22 none If enabled, addressing switches to macro-linear when + image width is <= 8 micro-tiles. If disabled, functionality + is same as RV350, switch to macro-linear when image + width is < 8 micro-tiles. + + POSSIBLE VALUES: + 00 - RV350 mode + 01 - Switch from macro-tiled to macro-linear when + (width <= 8 micro-tiles) +Reserved 28:23 none +Reserved 29 none +Reserved 30 none +BORDER_FIX 31 none To fix issues when using non-square mipmaps, with + border_color, and extreme minification. + + POSSIBLE VALUES: + 00 - R3xx R4xx mode + 01 - Stop right shifting coord once mip size is pinned + to one + + + +TX:TX_FILTER4 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4110 +DESCRIPTION: Filter4 Kernel +Field Name Bits Default Description + +© 2008 Advanced Micro Devices, Inc. +Proprietary 221 + Revision 1.4 October 13, 2009 + + + + +WEIGHT_1 10:0 none (s1.9). Bottom or Right weight of pair. +WEIGHT_0 21:11 none (s1.9). Top or Left weight of pair. +WEIGHT_PAIR 22 none Indicates which pair of weights within phase to load. + + POSSIBLE VALUES: + 00 - Top or Left + 01 - Bottom or Right +PHASE 26:23 none Indicates which of 9 phases to load +DIRECTION 27 none Indicates whether to load the horizontal or vertical + weights + + POSSIBLE VALUES: + 00 - Horizontal + 01 - Vertical + + + +TX:TX_FORMAT0_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4480-0x44bc +DESCRIPTION: Texture Format State +Field Name Bits Default Description +TXWIDTH 10:0 none Image width - 1. The largest image is 4096 texels. When + wrapping or mirroring, must be a power of 2. When + mipmapping, must be a power of 2 or padded to a power + of 2 in memory. Can always be non-square, except for + cube maps which must be square. +TXHEIGHT 21:11 none Image height - 1. The largest image is 4096 texels. When + wrapping or mirroring, must be a power of 2. When + mipmapping, must be a power of 2 or padded to a power + of 2 in memory. Can always be non-square, except for + cube maps which must be square. +TXDEPTH 25:22 none LOG2(depth) of volume texture +NUM_LEVELS 29:26 none Number of mipmap levels minus 1. Ranges from 0 to 12. + Equivalent to LOD index of smallest (coarsest) mipmap + to use. +PROJECTED 30 none Specifies whether texture coords are projected. + + POSSIBLE VALUES: + 00 - Non-Projected + 01 - Projected +TXPITCH_EN 31 none Indicates when TXPITCH should be used instead of + TXWIDTH for image addressing + + POSSIBLE VALUES: + 00 - Use TXWIDTH for image addressing + 01 - Use TXPITCH for image addressing + + + +TX:TX_FORMAT1_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x44c0-0x44fc + +© 2008 Advanced Micro Devices, Inc. +Proprietary 222 + Revision 1.4 October 13, 2009 + + + + +DESCRIPTION: Texture Format State +Field Name Bits Default Description +TXFORMAT 4:0 none Texture Format. Components are numbered right to left. + Parenthesis indicate typical uses of each format. + + POSSIBLE VALUES: + 00 - TX_FMT_8 or TX_FMT_1 (if + TX_FORMAT2.TXFORMAT_MSB is set) + 01 - TX_FMT_16 or TX_FMT_1_REVERSE (if + TX_FORMAT2.TXFORMAT_MSB is set) + 02 - TX_FMT_4_4 or TX_FMT_10 (if + TX_FORMAT2.TXFORMAT_MSB is set) + 03 - TX_FMT_8_8 or TX_FMT_10_10 (if + TX_FORMAT2.TXFORMAT_MSB is set) + 04 - TX_FMT_16_16 or TX_FMT_10_10_10_10 (if + TX_FORMAT2.TXFORMAT_MSB is set) + 05 - TX_FMT_3_3_2 or TX_FMT_ATI1N (if + TX_FORMAT2.TXFORMAT_MSB is set) + 06 - TX_FMT_5_6_5 + 07 - TX_FMT_6_5_5 + 08 - TX_FMT_11_11_10 + 09 - TX_FMT_10_11_11 + 10 - TX_FMT_4_4_4_4 + 11 - TX_FMT_1_5_5_5 + 12 - TX_FMT_8_8_8_8 + 13 - TX_FMT_2_10_10_10 + 14 - TX_FMT_16_16_16_16 + 15 - Reserved + 16 - Reserved + 17 - Reserved + 18 - TX_FMT_Y8 + 19 - TX_FMT_AVYU444 + 20 - TX_FMT_VYUY422 + 21 - TX_FMT_YVYU422 + 22 - TX_FMT_16_MPEG + 23 - TX_FMT_16_16_MPEG + 24 - TX_FMT_16f + 25 - TX_FMT_16f_16f + 26 - TX_FMT_16f_16f_16f_16f + 27 - TX_FMT_32f + 28 - TX_FMT_32f_32f + 29 - TX_FMT_32f_32f_32f_32f + 30 - TX_FMT_W24_FP + 31 - TX_FMT_ATI2N +SIGNED_COMP0 5 none Component filter should interpret texel data as signed or + unsigned. (Ignored for Y/YUV formats.) + + POSSIBLE VALUES: + 00 - Component filter should interpret texel data as + unsigned + 01 - Component filter should interpret texel data as + signed + +© 2008 Advanced Micro Devices, Inc. +Proprietary 223 + Revision 1.4 October 13, 2009 + + + + +SIGNED_COMP1 6 none Component filter should interpret texel data as signed or + unsigned. (Ignored for Y/YUV formats.) + + POSSIBLE VALUES: + 00 - Component filter should interpret texel data as + unsigned + 01 - Component filter should interpret texel data as + signed +SIGNED_COMP2 7 none Component filter should interpret texel data as signed or + unsigned. (Ignored for Y/YUV formats.) + + POSSIBLE VALUES: + 00 - Component filter should interpret texel data as + unsigned + 01 - Component filter should interpret texel data as + signed +SIGNED_COMP3 8 none Component filter should interpret texel data as signed or + unsigned. (Ignored for Y/YUV formats.) + + POSSIBLE VALUES: + 00 - Component filter should interpret texel data as + unsigned + 01 - Component filter should interpret texel data as + signed +SEL_ALPHA 11:9 none Specifies swizzling for each channel at the input of the + pixel shader. (Ignored for Y/YUV formats.) + + POSSIBLE VALUES: + 00 - Select Texture Component0. + 01 - Select Texture Component1. + 02 - Select Texture Component2. + 03 - Select Texture Component3. + 04 - Select the value 0. + 05 - Select the value 1. +SEL_RED 14:12 none Specifies swizzling for each channel at the input of the + pixel shader. (Ignored for Y/YUV formats.) + + POSSIBLE VALUES: + 00 - Select Texture Component0. + 01 - Select Texture Component1. + 02 - Select Texture Component2. + 03 - Select Texture Component3. + 04 - Select the value 0. + 05 - Select the value 1. +SEL_GREEN 17:15 none Specifies swizzling for each channel at the input of the + pixel shader. (Ignored for Y/YUV formats.) + + POSSIBLE VALUES: + 00 - Select Texture Component0. + 01 - Select Texture Component1. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 224 + Revision 1.4 October 13, 2009 + + + + + 02 - Select Texture Component2. + 03 - Select Texture Component3. + 04 - Select the value 0. + 05 - Select the value 1. +SEL_BLUE 20:18 none Specifies swizzling for each channel at the input of the + pixel shader. (Ignored for Y/YUV formats.) + + POSSIBLE VALUES: + 00 - Select Texture Component0. + 01 - Select Texture Component1. + 02 - Select Texture Component2. + 03 - Select Texture Component3. + 04 - Select the value 0. + 05 - Select the value 1. +GAMMA 21 none Optionally remove gamma from texture before passing to + shader. Only apply to 8bit or less components. + + POSSIBLE VALUES: + 00 - Disable gamma removal + 01 - Enable gamma removal +YUV_TO_RGB 23:22 none YUV to RGB conversion mode + + POSSIBLE VALUES: + 00 - Disable YUV to RGB conversion + 01 - Enable YUV to RGB conversion (with clamp) + 02 - Enable YUV to RGB conversion (without + clamp) +SWAP_YUV 24 none POSSIBLE VALUES: + 00 - Disable swap YUV mode + 01 - Enable swap YUV mode (hw inverts upper bit of + U and V) +TEX_COORD_TYPE 26:25 none Specifies coordinate type. + + POSSIBLE VALUES: + 00 - 2D + 01 - 3D + 02 - Cube + 03 - Reserved +CACHE 31:27 none This field is ignored on R520 and RV510. + + POSSIBLE VALUES: + 00 - WHOLE + 01 - Reserved + 02 - HALF_REGION_0 + 03 - HALF_REGION_1 + 04 - FOURTH_REGION_0 + 05 - FOURTH_REGION_1 + 06 - FOURTH_REGION_2 + 07 - FOURTH_REGION_3 + 08 - EIGHTH_REGION_0 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 225 + Revision 1.4 October 13, 2009 + + + + + 09 - EIGHTH_REGION_1 + 10 - EIGHTH_REGION_2 + 11 - EIGHTH_REGION_3 + 12 - EIGHTH_REGION_4 + 13 - EIGHTH_REGION_5 + 14 - EIGHTH_REGION_6 + 15 - EIGHTH_REGION_7 + 16 - SIXTEENTH_REGION_0 + 17 - SIXTEENTH_REGION_1 + 18 - SIXTEENTH_REGION_2 + 19 - SIXTEENTH_REGION_3 + 20 - SIXTEENTH_REGION_4 + 21 - SIXTEENTH_REGION_5 + 22 - SIXTEENTH_REGION_6 + 23 - SIXTEENTH_REGION_7 + 24 - SIXTEENTH_REGION_8 + 25 - SIXTEENTH_REGION_9 + 26 - SIXTEENTH_REGION_A + 27 - SIXTEENTH_REGION_B + 28 - SIXTEENTH_REGION_C + 29 - SIXTEENTH_REGION_D + 30 - SIXTEENTH_REGION_E + 31 - SIXTEENTH_REGION_F + + + +TX:TX_FORMAT2_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4500-0x453c +DESCRIPTION: Texture Format State +Field Name Bits Default Description +TXPITCH 13:0 none Used instead of TXWIDTH for image addressing when + TXPITCH_EN is asserted. Pitch is given as number of + texels minus one. Maximum pitch is 16K texels. +TXFORMAT_MSB 14 none Specifies the MSB of the texture format to extend the + number of formats to 64. +TXWIDTH_11 15 none Specifies bit 11 of TXWIDTH to extend the largest + image to 4096 texels. +TXHEIGHT_11 16 none Specifies bit 11 of TXHEIGHT to extend the largest + image to 4096 texels. +POW2FIX2FLT 17 none Optionally divide by 256 instead of 255 during fix2float. + Can only be asserted for 8-bit components. + + POSSIBLE VALUES: + 00 - Divide by pow2-1 for fix2float (default) + 01 - Divide by pow2 for fix2float +SEL_FILTER4 19:18 none If filter4 is enabled, specifies which texture component + to apply filter4 to. + + POSSIBLE VALUES: + 00 - Select Texture Component0. + 01 - Select Texture Component1. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 226 + Revision 1.4 October 13, 2009 + + + + + 02 - Select Texture Component2. + 03 - Select Texture Component3. + + + +TX:TX_INVALTAGS · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4100 +DESCRIPTION: Invalidate texture cache tags +Field Name Bits Default Description +RESERVED 31:0 none Unused + + + +TX:TX_OFFSET_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4540-0x457c +DESCRIPTION: Texture Offset State +Field Name Bits Default Description +ENDIAN_SWAP 1:0 none Endian Control + + POSSIBLE VALUES: + 00 - No swap + 01 - 16 bit swap + 02 - 32 bit swap + 03 - Half-DWORD swap +MACRO_TILE 2 none Macro Tile Control + + POSSIBLE VALUES: + 00 - 2KB page is linear + 01 - 2KB page is tiled +MICRO_TILE 4:3 none Micro Tile Control + + POSSIBLE VALUES: + 00 - 32 byte cache line is linear + 01 - 32 byte cache line is tiled + 02 - 32 byte cache line is tiled square (only applies to + 16-bit texel) + 03 - Reserved +TXOFFSET 31:5 none 32-byte aligned pointer to base map + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 227 + Revision 1.4 October 13, 2009 + + + + +11.10 Fragment Shader Registers + +US:US_ALU_ALPHA_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xa800-0xaffc +DESCRIPTION: ALU Alpha Instruction +Field Name Bits Default Description +ALPHA_OP 3:0 0x0 Specifies the opcode for this instruction. + + POSSIBLE VALUES: + 00 - OP_MAD: Result = A*B + C + 01 - OP_DP: Result = dot product from RGB ALU + 02 - OP_MIN: Result = min(A,B) + 03 - OP_MAX: Result = max(A,B) + 04 - reserved + 05 - OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B + 06 - OP_CMP: Result = cmp(A,B,C) = + (C>=0.0)?A:B + 07 - OP_FRC: Result = A-floor(A) + 08 - OP_EX2: Result = 2^^A + 09 - OP_LN2: Result = log2(A) + 10 - OP_RCP: Result = 1/A + 11 - OP_RSQ: Result = 1/sqrt(A) + 12 - OP_SIN: Result = sin(A*2pi) + 13 - OP_COS: Result = cos(A*2pi) + 14 - OP_MDH: Result = A*B + C; A is always + topleft.src0, C is always topright.src0 (source select and + swizzles ignored). Input modifiers are respected for all + inputs. + 15 - OP_MDV: Result = A*B + C; A is always + topleft.src0, C is always bottomleft.src0 (source select + and swizzles ignored). Input modifiers are respected for + all inputs. +ALPHA_ADDRD 10:4 0x0 Specifies the address of the pixel stack frame register to + which the Alpha result of this instruction is to be written. +ALPHA_ADDRD_REL 11 0x0 Specifies whether the loop register is added to the value + of ALPHA_ADDRD before it is used. This implements + relative addressing. + + POSSIBLE VALUES: + 00 - NONE: Do not modify destination address. + 01 - RELATIVE: Add aL to address before write. +ALPHA_SEL_A 13:12 0x0 Specifies the operands for Alpha inputs A and B. + + POSSIBLE VALUES: + 00 - src0 + 01 - src1 + 02 - src2 + 03 - srcp +ALPHA_SWIZ_A 16:14 0x0 Specifies the channel sources for Alpha inputs A and B. + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 228 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + 06 - One + 07 - Unused +ALPHA_MOD_A 18:17 0x0 Specifies the input modifiers for Alpha inputs A and B. + + POSSIBLE VALUES: + 00 - NOP: Do not modify input + 01 - NEG: Negate input + 02 - ABS: Take absolute value of input + 03 - NAB: Take negative absolute value of input +ALPHA_SEL_B 20:19 0x0 Specifies the operands for Alpha inputs A and B. + + POSSIBLE VALUES: + 00 - src0 + 01 - src1 + 02 - src2 + 03 - srcp +ALPHA_SWIZ_B 23:21 0x0 Specifies the channel sources for Alpha inputs A and B. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + 06 - One + 07 - Unused +ALPHA_MOD_B 25:24 0x0 Specifies the input modifiers for Alpha inputs A and B. + + POSSIBLE VALUES: + 00 - NOP: Do not modify input + 01 - NEG: Negate input + 02 - ABS: Take absolute value of input + 03 - NAB: Take negative absolute value of input +OMOD 28:26 0x0 Specifies the output modifier for this instruction. + + POSSIBLE VALUES: + 00 - Result * 1 + 01 - Result * 2 + 02 - Result * 4 + 03 - Result * 8 + 04 - Result / 2 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 229 + Revision 1.4 October 13, 2009 + + + + + 05 - Result / 4 + 06 - Result / 8 + 07 - Disable output modifier and clamping (result is + copied exactly; only valid for MIN/MAX/CMP/CND) +TARGET 30:29 0x0 This specifies which (cached) frame buffer target to write + to. For non-output ALU instructions, this specifies how + to compare the results against zero when setting the + predicate bits. + + POSSIBLE VALUES: + 00 - A: Output to render target A. Predicate == + (ALU) + 01 - B: Output to render target B. Predicate < (ALU) + 02 - C: Output to render target C. Predicate >= + (ALU) + 03 - D: Output to render target D. Predicate != (ALU) +W_OMASK 31 0x0 Specifies whether or not to write the Alpha component of + the result of this instuction to the depth output fifo. + + POSSIBLE VALUES: + 00 - NONE: Do not write output to w. + 01 - A: Write the alpha channel only to w. + + + +US:US_ALU_ALPHA_ADDR_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x9800-0x9ffc +DESCRIPTION: This table specifies the Alpha source addresses and pre-subtract operation for up to 512 ALU +instruction. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2). +The pre-subtract operation creates two more (rgbp and ap). +Field Name Bits Default Description +ADDR0 7:0 0x0 Specifies the identity of source operands a0, a1, and a2. + If the const field is set, this number ranges from 0 to 255 + and specifies a location within the constant register bank. + Otherwise: If the most significant bit is cleared, this field + specifies a location within the current pixel stack frame + (ranging from 0 to 127). If the most significant bit is set, + then the lower 7 bits specify an inline unsigned floating- + point constant with 4 bit exponent (bias 7) and 3 bit + mantissa, including denormals but excluding + infinite/NaN. +ADDR0_CONST 8 0x0 Specifies whether the associated address is a constant + register address or a temporary address / inline constant. + + POSSIBLE VALUES: + 00 - TEMPORARY: Address temporary register or + inline constant value. + 01 - CONSTANT: Address constant register. +ADDR0_REL 9 0x0 Specifies whether the loop register is added to the value + of the associated address before it is used. This + implements relative addressing. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 230 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - NONE: Do not modify source address. + 01 - RELATIVE: Add aL before lookup. +ADDR1 17:10 0x0 Specifies the identity of source operands a0, a1, and a2. + If the const field is set, this number ranges from 0 to 255 + and specifies a location within the constant register bank. + Otherwise: If the most significant bit is cleared, this field + specifies a location within the current pixel stack frame + (ranging from 0 to 127). If the most significant bit is set, + then the lower 7 bits specify an inline unsigned floating- + point constant with 4 bit exponent (bias 7) and 3 bit + mantissa, including denormals but excluding + infinite/NaN. +ADDR1_CONST 18 0x0 Specifies whether the associated address is a constant + register address or a temporary address / inline constant. + + POSSIBLE VALUES: + 00 - TEMPORARY: Address temporary register or + inline constant value. + 01 - CONSTANT: Address constant register. +ADDR1_REL 19 0x0 Specifies whether the loop register is added to the value + of the associated address before it is used. This + implements relative addressing. + + POSSIBLE VALUES: + 00 - NONE: Do not modify source address. + 01 - RELATIVE: Add aL before lookup. +ADDR2 27:20 0x0 Specifies the identity of source operands a0, a1, and a2. + If the const field is set, this number ranges from 0 to 255 + and specifies a location within the constant register bank. + Otherwise: If the most significant bit is cleared, this field + specifies a location within the current pixel stack frame + (ranging from 0 to 127). If the most significant bit is set, + then the lower 7 bits specify an inline unsigned floating- + point constant with 4 bit exponent (bias 7) and 3 bit + mantissa, including denormals but excluding + infinite/NaN. +ADDR2_CONST 28 0x0 Specifies whether the associated address is a constant + register address or a temporary address / inline constant. + + POSSIBLE VALUES: + 00 - TEMPORARY: Address temporary register or + inline constant value. + 01 - CONSTANT: Address constant register. +ADDR2_REL 29 0x0 Specifies whether the loop register is added to the value + of the associated address before it is used. This + implements relative addressing. + + POSSIBLE VALUES: + +© 2008 Advanced Micro Devices, Inc. +Proprietary 231 + Revision 1.4 October 13, 2009 + + + + + 00 - NONE: Do not modify source address. + 01 - RELATIVE: Add aL before lookup. +SRCP_OP 31:30 0x0 Specifies how the pre-subtract value (SRCP) is + computed. + + POSSIBLE VALUES: + 00 - 1.0-2.0*A0 + 01 - A1-A0 + 02 - A1+A0 + 03 - 1.0-A0 + + + +US:US_ALU_RGBA_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xb000-0xb7fc +DESCRIPTION: ALU Shared RGBA Instruction +Field Name Bits Default Description +RGB_OP 3:0 0x0 Specifies the opcode for this instruction. + + POSSIBLE VALUES: + 00 - OP_MAD: Result = A*B + C + 01 - OP_DP3: Result = A.r*B.r + A.g*B.g + A.b*B.b + 02 - OP_DP4: Result = A.r*B.r + A.g*B.g + A.b*B.b + + A.a*B.a + 03 - OP_D2A: Result = A.r*B.r + A.g*B.g + C.b + 04 - OP_MIN: Result = min(A,B) + 05 - OP_MAX: Result = max(A,B) + 06 - reserved + 07 - OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B + 08 - OP_CMP: Result = cmp(A,B,C) = + (C>=0.0)?A:B + 09 - OP_FRC: Result = A-floor(A) + 10 - OP_SOP: Result = ex2,ln2,rcp,rsq,sin,cos from + Alpha ALU + 11 - OP_MDH: Result = A*B + C; A is always + topleft.src0, C is always topright.src0 (source select and + swizzles ignored). Input modifiers are respected for all + inputs. + 12 - OP_MDV: Result = A*B + C; A is always + topleft.src0, C is always bottomleft.src0 (source select + and swizzles ignored). Input modifiers are respected for + all inputs. +RGB_ADDRD 10:4 0x0 Specifies the address of the pixel stack frame register to + which the RGB result of this instruction is to be written. +RGB_ADDRD_REL 11 0x0 Specifies whether the loop register is added to the value + of RGB_ADDRD before it is used. This implements + relative addressing. + + POSSIBLE VALUES: + 00 - NONE: Do not modify destination address. + 01 - RELATIVE: Add aL to address before write. + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 232 + Revision 1.4 October 13, 2009 + + + + +RGB_SEL_C 13:12 0x0 Specifies the operands for RGB and Alpha input C. + + POSSIBLE VALUES: + 00 - src0 + 01 - src1 + 02 - src2 + 03 - srcp +RED_SWIZ_C 16:14 0x0 Specifies, per channel, the sources for RGB and Alpha + input C. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + 06 - One + 07 - Unused +GREEN_SWIZ_C 19:17 0x0 Specifies, per channel, the sources for RGB and Alpha + input C. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + 06 - One + 07 - Unused +BLUE_SWIZ_C 22:20 0x0 Specifies, per channel, the sources for RGB and Alpha + input C. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + 06 - One + 07 - Unused +RGB_MOD_C 24:23 0x0 Specifies the input modifiers for RGB and Alpha input + C. + + POSSIBLE VALUES: + 00 - NOP: Do not modify input + 01 - NEG: Negate input + 02 - ABS: Take absolute value of input + 03 - NAB: Take negative absolute value of input + +© 2008 Advanced Micro Devices, Inc. +Proprietary 233 + Revision 1.4 October 13, 2009 + + + + +ALPHA_SEL_C 26:25 0x0 Specifies the operands for RGB and Alpha input C. + + POSSIBLE VALUES: + 00 - src0 + 01 - src1 + 02 - src2 + 03 - srcp +ALPHA_SWIZ_C 29:27 0x0 Specifies, per channel, the sources for RGB and Alpha + input C. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + 06 - One + 07 - Unused +ALPHA_MOD_C 31:30 0x0 Specifies the input modifiers for RGB and Alpha input + C. + + POSSIBLE VALUES: + 00 - NOP: Do not modify input + 01 - NEG: Negate input + 02 - ABS: Take absolute value of input + 03 - NAB: Take negative absolute value of input + + + +US:US_ALU_RGB_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xa000-0xa7fc +DESCRIPTION: ALU RGB Instruction +Field Name Bits Default Description +RGB_SEL_A 1:0 0x0 Specifies the operands for RGB inputs A and B. + + POSSIBLE VALUES: + 00 - src0 + 01 - src1 + 02 - src2 + 03 - srcp +RED_SWIZ_A 4:2 0x0 Specifies, per channel, the sources for RGB inputs A and + B. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + +© 2008 Advanced Micro Devices, Inc. +Proprietary 234 + Revision 1.4 October 13, 2009 + + + + + 06 - One + 07 - Unused +GREEN_SWIZ_A 7:5 0x0 Specifies, per channel, the sources for RGB inputs A and + B. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + 06 - One + 07 - Unused +BLUE_SWIZ_A 10:8 0x0 Specifies, per channel, the sources for RGB inputs A and + B. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + 06 - One + 07 - Unused +RGB_MOD_A 12:11 0x0 Specifies the input modifiers for RGB inputs A and B. + + POSSIBLE VALUES: + 00 - NOP: Do not modify input + 01 - NEG: Negate input + 02 - ABS: Take absolute value of input + 03 - NAB: Take negative absolute value of input +RGB_SEL_B 14:13 0x0 Specifies the operands for RGB inputs A and B. + + POSSIBLE VALUES: + 00 - src0 + 01 - src1 + 02 - src2 + 03 - srcp +RED_SWIZ_B 17:15 0x0 Specifies, per channel, the sources for RGB inputs A and + B. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + +© 2008 Advanced Micro Devices, Inc. +Proprietary 235 + Revision 1.4 October 13, 2009 + + + + + 06 - One + 07 - Unused +GREEN_SWIZ_B 20:18 0x0 Specifies, per channel, the sources for RGB inputs A and + B. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + 06 - One + 07 - Unused +BLUE_SWIZ_B 23:21 0x0 Specifies, per channel, the sources for RGB inputs A and + B. + + POSSIBLE VALUES: + 00 - Red + 01 - Green + 02 - Blue + 03 - Alpha + 04 - Zero + 05 - Half + 06 - One + 07 - Unused +RGB_MOD_B 25:24 0x0 Specifies the input modifiers for RGB inputs A and B. + + POSSIBLE VALUES: + 00 - NOP: Do not modify input + 01 - NEG: Negate input + 02 - ABS: Take absolute value of input + 03 - NAB: Take negative absolute value of input +OMOD 28:26 0x0 Specifies the output modifier for this instruction. + + POSSIBLE VALUES: + 00 - Result * 1 + 01 - Result * 2 + 02 - Result * 4 + 03 - Result * 8 + 04 - Result / 2 + 05 - Result / 4 + 06 - Result / 8 + 07 - Disable output modifier and clamping (result is + copied exactly; only valid for MIN/MAX/CMP/CND) +TARGET 30:29 0x0 This specifies which (cached) frame buffer target to write + to. For non-output ALU instructions, this specifies how + to compare the results against zero when setting the + predicate bits. + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 236 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - A: Output to render target A. Predicate == + (ALU) + 01 - B: Output to render target B. Predicate < (ALU) + 02 - C: Output to render target C. Predicate >= + (ALU) + 03 - D: Output to render target D. Predicate != (ALU) +ALU_WMASK 31 0x0 Specifies whether to update the current ALU result. + + POSSIBLE VALUES: + 00 - Do not modify the current ALU result. + 01 - Modify the current ALU result based on the + settings of ALU_RESULT_SEL and + ALU_RESULT_OP. + + + +US:US_ALU_RGB_ADDR_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x9000-0x97fc +DESCRIPTION: This table specifies the RGB source addresses and pre-subtract operation for up to 512 ALU +instructions. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, +a2). The pre-subtract operation creates two more (rgbp and ap). +Field Name Bits Default Description +ADDR0 7:0 0x0 Specifies the identity of source operands rgb0, rgb1, and + rgb2. If the const field is set, this number ranges from 0 + to 255 and specifies a location within the constant + register bank. Otherwise: If the most significant bit is + cleared, this field specifies a location within the current + pixel stack frame (ranging from 0 to 127). If the most + significant bit is set, then the lower 7 bits specify an + inline unsigned floating-point constant with 4 bit + exponent (bias 7) and 3 bit mantissa, including + denormals but excluding infinite/NaN. +ADDR0_CONST 8 0x0 Specifies whether the associated address is a constant + register address or a temporary address / inline constant. + + POSSIBLE VALUES: + 00 - TEMPORARY: Address temporary register or + inline constant value. + 01 - CONSTANT: Address constant register. +ADDR0_REL 9 0x0 Specifies whether the loop register is added to the value + of the associated address before it is used. This + implements relative addressing. + + POSSIBLE VALUES: + 00 - NONE: Do not modify source address. + 01 - RELATIVE: Add aL before lookup. +ADDR1 17:10 0x0 Specifies the identity of source operands rgb0, rgb1, and + rgb2. If the const field is set, this number ranges from 0 + to 255 and specifies a location within the constant + +© 2008 Advanced Micro Devices, Inc. +Proprietary 237 + Revision 1.4 October 13, 2009 + + + + + register bank. Otherwise: If the most significant bit is + cleared, this field specifies a location within the current + pixel stack frame (ranging from 0 to 127). If the most + significant bit is set, then the lower 7 bits specify an + inline unsigned floating-point constant with 4 bit + exponent (bias 7) and 3 bit mantissa, including + denormals but excluding infinite/NaN. +ADDR1_CONST 18 0x0 Specifies whether the associated address is a constant + register address or a temporary address / inline constant. + + POSSIBLE VALUES: + 00 - TEMPORARY: Address temporary register or + inline constant value. + 01 - CONSTANT: Address constant register. +ADDR1_REL 19 0x0 Specifies whether the loop register is added to the value + of the associated address before it is used. This + implements relative addressing. + + POSSIBLE VALUES: + 00 - NONE: Do not modify source address. + 01 - RELATIVE: Add aL before lookup. +ADDR2 27:20 0x0 Specifies the identity of source operands rgb0, rgb1, and + rgb2. If the const field is set, this number ranges from 0 + to 255 and specifies a location within the constant + register bank. Otherwise: If the most significant bit is + cleared, this field specifies a location within the current + pixel stack frame (ranging from 0 to 127). If the most + significant bit is set, then the lower 7 bits specify an + inline unsigned floating-point constant with 4 bit + exponent (bias 7) and 3 bit mantissa, including + denormals but excluding infinite/NaN. +ADDR2_CONST 28 0x0 Specifies whether the associated address is a constant + register address or a temporary address / inline constant. + + POSSIBLE VALUES: + 00 - TEMPORARY: Address temporary register or + inline constant value. + 01 - CONSTANT: Address constant register. +ADDR2_REL 29 0x0 Specifies whether the loop register is added to the value + of the associated address before it is used. This + implements relative addressing. + + POSSIBLE VALUES: + 00 - NONE: Do not modify source address. + 01 - RELATIVE: Add aL before lookup. +SRCP_OP 31:30 0x0 Specifies how the pre-subtract value (SRCP) is + computed. + + POSSIBLE VALUES: + 00 - 1.0-2.0*RGB0 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 238 + Revision 1.4 October 13, 2009 + + + + + 01 - RGB1-RGB0 + 02 - RGB1+RGB0 + 03 - 1.0-RGB0 + + + +US:US_CMN_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xb800-0xbffc +DESCRIPTION: Shared instruction fields for all instruction types +Field Name Bits Default Description +TYPE 1:0 0x0 Specifies the type of instruction. Note that output + instructions write to render targets. + + POSSIBLE VALUES: + 00 - US_INST_TYPE_ALU: This instruction is an + ALU instruction. + 01 - US_INST_TYPE_OUT: This instruction is an + output instruction. + 02 - US_INST_TYPE_FC: This instruction is a flow + control instruction. + 03 - US_INST_TYPE_TEX: This instruction is a + texture instruction. +TEX_SEM_WAIT 2 0x0 Specifies whether to wait for the texture semaphore. + + POSSIBLE VALUES: + 00 - This instruction may issue immediately. + 01 - This instruction will not issue until the texture + semaphore is available. +RGB_PRED_SEL 5:3 0x0 Specifies whether the instruction uses predication. For + ALU/TEX/Output this specifies predication for the RGB + channels only. For FC this specifies the predicate for the + entire instruction. + + POSSIBLE VALUES: + 00 - US_PRED_SEL_NONE: No predication + 01 - US_PRED_SEL_RGBA: Independent Channel + Predication + 02 - US_PRED_SEL_RRRR: R-Replicate + Predication + 03 - US_PRED_SEL_GGGG: G-Replicate + Predication + 04 - US_PRED_SEL_BBBB: B-Replicate + Predication + 05 - US_PRED_SEL_AAAA: A-Replicate + Predication +RGB_PRED_INV 6 0x0 Specifies whether the predicate should be inverted. For + ALU/TEX/Output this specifies predication for the RGB + channels only. For FC this specifies the predicate for the + entire instruction. + + POSSIBLE VALUES: + 00 - Normal predication +© 2008 Advanced Micro Devices, Inc. +Proprietary 239 + Revision 1.4 October 13, 2009 + + + + + 01 - Invert the value of the predicate +WRITE_INACTIVE 7 0x0 Specifies which pixels to write to. + + POSSIBLE VALUES: + 00 - Only write to channels of active pixels + 01 - Write to channels of all pixels, including inactive + pixels +LAST 8 0x0 Specifies whether this is the last instruction. + + POSSIBLE VALUES: + 00 - Do not terminate the shader after executing this + instruction (unless this instruction is at END_ADDR). + 01 - All active pixels are willing to terminate after + executing this instruction. There is no guarantee that the + shader will actually terminate here. This feature is + provided as a performance optimization for tests where + pixels can conditionally terminate early. +NOP 9 0x0 Specifies whether to insert a NOP instruction after this. + This would get specified in order to meet dependency + requirements for the pre-subtract inputs, and dependency + requirements for src0 of an MDH/MDV instruction. + + POSSIBLE VALUES: + 00 - Do not insert NOP instruction after this one. + 01 - Insert a NOP instruction after this one. +ALU_WAIT 10 0x0 Specifies whether to wait for pending ALU instructions + to complete before issuing this instruction. + + POSSIBLE VALUES: + 00 - Do not wait for pending ALU instructions to + complete before issuing the current instruction. + 01 - Wait for pending ALU instructions to complete + before issuing the current instruction. +RGB_WMASK 13:11 0x0 Specifies which components of the result of the RGB + instruction are written to the pixel stack frame. + + POSSIBLE VALUES: + 00 - NONE: Do not write any output. + 01 - R: Write the red channel only. + 02 - G: Write the green channel only. + 03 - RG: Write the red and green channels. + 04 - B: Write the blue channel only. + 05 - RB: Write the red and blue channels. + 06 - GB: Write the green and blue channels. + 07 - RGB: Write the red, green, and blue channels. +ALPHA_WMASK 14 0x0 Specifies whether the result of the Alpha instruction is + written to the pixel stack frame. + + POSSIBLE VALUES: + 00 - NONE: Do not write register. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 240 + Revision 1.4 October 13, 2009 + + + + + 01 - A: Write the alpha channel only. +RGB_OMASK 17:15 0x0 Specifies which components of the result of the RGB + instruction are written to the output fifo if this is an + output instruction, and which predicate bits should be + modified if this is an ALU instruction. + + POSSIBLE VALUES: + 00 - NONE: Do not write any output. + 01 - R: Write the red channel only. + 02 - G: Write the green channel only. + 03 - RG: Write the red and green channels. + 04 - B: Write the blue channel only. + 05 - RB: Write the red and blue channels. + 06 - GB: Write the green and blue channels. + 07 - RGB: Write the red, green, and blue channels. +ALPHA_OMASK 18 0x0 Specifies whether the result of the Alpha instruction is + written to the output fifo if this is an output instruction, + and whether the Alpha predicate bit should be modified + if this is an ALU instruction. + + POSSIBLE VALUES: + 00 - NONE: Do not write output. + 01 - A: Write the alpha channel only. +RGB_CLAMP 19 0x0 Specifies RGB and Alpha clamp mode for this + instruction. + + POSSIBLE VALUES: + 00 - Do not clamp output. + 01 - Clamp output to the range [0,1]. +ALPHA_CLAMP 20 0x0 Specifies RGB and Alpha clamp mode for this + instruction. + + POSSIBLE VALUES: + 00 - Do not clamp output. + 01 - Clamp output to the range [0,1]. +ALU_RESULT_SEL 21 0x0 Specifies which component of the result of this + instruction should be used as the `ALU result` by a + subsequent flow control instruction. + + POSSIBLE VALUES: + 00 - RED: Use red as ALU result for FC. + 01 - ALPHA: Use alpha as ALU result for FC. +ALPHA_PRED_INV 22 0x0 Specifies whether the predicate should be inverted. For + ALU/TEX/Output this specifies predication for the alpha + channel only. This field has no effect on FC instructions. + + POSSIBLE VALUES: + 00 - Normal predication + 01 - Invert the value of the predicate + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 241 + Revision 1.4 October 13, 2009 + + + + +ALU_RESULT_OP 24:23 0x0 Specifies how to compare the ALU result against zero + for the `alu_result` bit in a subsequent flow control + instruction. + + POSSIBLE VALUES: + 00 - Equal to + 01 - Less than + 02 - Greater than or equal to + 03 - Not equal +ALPHA_PRED_SEL 27:25 0x0 Specifies whether the instruction uses predication. For + ALU/TEX/Output this specifies predication for the alpha + channel only. This field has no effect on FC instructions. + + POSSIBLE VALUES: + 00 - US_PRED_SEL_NONE: No predication + 01 - US_PRED_SEL_RGBA: A predication + (identical to US_PRED_SEL_AAAA) + 02 - US_PRED_SEL_RRRR: R Predication + 03 - US_PRED_SEL_GGGG: G Predication + 04 - US_PRED_SEL_BBBB: B Predication + 05 - US_PRED_SEL_AAAA: A Predication +STAT_WE 31:28 0x0 Specifies which components (R,G,B,A) contribute to the + stat count + + + +US:US_CODE_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4630 +DESCRIPTION: Code start and end instruction addresses. +Field Name Bits Default Description +START_ADDR 8:0 0x0 Specifies the address of the first instruction to execute in + the shader program. This address is relative to the shader + program offset given in + US_CODE_OFFSET.OFFSET_ADDR. +END_ADDR 24:16 0x0 Specifies the address of the last instruction to execute in + the shader program. This address is relative to the shader + program offset given in + US_CODE_OFFSET.OFFSET_ADDR. Shader program + execution will always terminate after the instruction at + this address is executed. + + + +US:US_CODE_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4638 +DESCRIPTION: Offsets used for relative instruction addresses in the shader program, including START_ADDR, +END_ADDR, and any non-global flow control jump addresses. +Field Name Bits Default Description +OFFSET_ADDR 8:0 0x0 Specifies the offset to add to relative instruction + addresses, including START_ADDR, END_ADDR, and + some flow control jump addresses. + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 242 + Revision 1.4 October 13, 2009 + + + + +US:US_CODE_RANGE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4634 +DESCRIPTION: Range of instructions that contains the current shader program. +Field Name Bits Default Description +CODE_ADDR 8:0 0x0 Specifies the start address of the current code window. + This address is an absolute address. +CODE_SIZE 24:16 0x0 Specifies the size of the current code window, minus + one. The last instruction in the code window is given by + CODE_ADDR + CODE_SIZE. + + + +US:US_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4600 +DESCRIPTION: Shader Configuration +Field Name Bits Default Description +Reserved 0 0x0 Set to 0 +ZERO_TIMES_ANYTHING_EQUALS_ZERO 1 0x0 Control how ALU multiplier behaves when one + argument is zero. This affects the multiplier used in + MAD and dot product calculations. + + POSSIBLE VALUES: + 00 - Default behaviour (0*inf=nan,0*nan=nan) + 01 - Legacy behaviour for shader model 1 + (0*anything=0) + + + +US:US_FC_ADDR_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xa000-0xa7fc +DESCRIPTION: Flow Control Instruction Address Fields +Field Name Bits Default Description +BOOL_ADDR 4:0 0x0 The address of the static boolean register to use in the + jump function. +INT_ADDR 12:8 0x0 The address of the static integer register to use for + loop/rep and endloop/endrep. +JUMP_ADDR 24:16 0x0 The address to jump to if the jump function evaluates to + true. +JUMP_GLOBAL 31 0x0 Specifies whether to interpret JUMP_ADDR as a global + address. + + POSSIBLE VALUES: + 00 - Add the shader program offset in + US_CODE_OFFSET.OFFSET_ADDR when calculating + the destination address of a jump + 01 - Don`t use the shader program offset when + calculating the destination address jump + + + +US:US_FC_BOOL_CONST · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4620 +DESCRIPTION: Static Boolean Constants for Flow Control Branching Instructions. Quad-buffered. +© 2008 Advanced Micro Devices, Inc. +Proprietary 243 + Revision 1.4 October 13, 2009 + + + + +Field Name Bits Default Description +KBOOL 31:0 0x0 Specifies the boolean value for constants 0-31. + + + +US:US_FC_CTRL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4624 +DESCRIPTION: Flow Control Options. Quad-buffered. +Field Name Bits Default Description +TEST_EN 30 0x0 Specifies whether test mode is enabled. This flag + currently has no effect in hardware. + + POSSIBLE VALUES: + 00 - Normal mode + 01 - Test mode (currently unused) +FULL_FC_EN 31 0x0 Specifies whether full flow control functionality is + enabled. + + POSSIBLE VALUES: + 00 - Use partial flow-control (enables twice the + contexts). Loops and subroutines are not available in + partial flow-control mode, and the nesting depth of + branch statements is limited. + 01 - Use full pixel shader 3.0 flow control, including + loops and subroutines. + + + +US:US_FC_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x9800-0x9ffc +DESCRIPTION: Flow Control Instruction +Field Name Bits Default Description +OP 2:0 0x0 Specifies the type of flow control instruction. + + POSSIBLE VALUES: + 00 - US_FC_OP_JUMP: (if, endif, call, etc) + 01 - US_FC_OP_LOOP: same as jump except + always take the jump if the static counter is 0. If we don`t + take the jump, push initial loop counter and loop register + (aL) values onto the loop stack. + 02 - US_FC_OP_ENDLOOP: same as jump but + decrement the loop counter and increment the loop + register (aL), and don`t take the jump if the loop counter + becomes zero. + 03 - US_FC_OP_REP: same as loop but don`t push + the loop register aL. + 04 - US_FC_OP_ENDREP: same as endloop but + don`t update/pop the loop register aL. + 05 - US_FC_OP_BREAKLOOP: same as jump but + pops the loop stacks if a pixel stops being active. + 06 - US_FC_OP_BREAKREP: same as breakloop + but don`t pop the loop register if it jumps. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 244 + Revision 1.4 October 13, 2009 + + + + + 07 - US_FC_OP_CONTINUE: used to disable pixels + that are ready to jump to the ENDLOOP/ENDREP + instruction. +B_ELSE 4 0x0 Specifies whether to perform an else operation on the + active and branch-inactive pixels before executing the + instruction. + + POSSIBLE VALUES: + 00 - Don`t alter the branch state before executing the + instruction. + 01 - Perform an else operation on the branch state + before executing the instruction; pixels in the active state + are moved to the branch inactive state with zero counter, + and vice versa. +JUMP_ANY 5 0x0 If set, jump if any active pixels want to take the jump + (otherwise the instruction jumps only if all active pixels + want to). + + POSSIBLE VALUES: + 00 - Jump if ALL active pixels want to take the jump + (for if and else). If no pixels are active, jump. + 01 - Jump if ANY active pixels want to take the jump + (for call, loop/rep and endrep/endloop). If no pixels are + active, do not jump. +A_OP 7:6 0x0 The address stack operation to perform if we take the + jump. + + POSSIBLE VALUES: + 00 - US_FC_A_OP_NONE: Don`t change the + address stack + 01 - US_FC_A_OP_POP: If we jump, pop the + address stack and use that value for the jump target + 02 - US_FC_A_OP_PUSH: If we jump, push the + current address onto the address stack +JUMP_FUNC 15:8 0x0 A 2x2x2 table of boolean values indicating whether to + take the jump. The table index is indexed by {ALU + Compare Result, Predication Result, Boolean Value + (from the static boolean address in + US_FC_ADDR.BOOL)}. To determine whether to jump, + look at bit ((alu_result<<2) | (predicate<<1) | bool). +B_POP_CNT 20:16 0x0 The amount to decrement the branch counter by if + US_FC_B_OP_DECR operation is performed. +B_OP0 25:24 0x0 The branch state operation to perform if we don`t take + the jump. + + POSSIBLE VALUES: + 00 - US_FC_B_OP_NONE: If we don`t jump, don`t + alter the branch counter for any pixel. + 01 - US_FC_B_OP_DECR: If we don`t jump, + decrement branch counter by B_POP_CNT for inactive + +© 2008 Advanced Micro Devices, Inc. +Proprietary 245 + Revision 1.4 October 13, 2009 + + + + + pixels. Activate pixels with negative counters. + 02 - US_FC_B_OP_INCR: If we don`t jump, + increment branch counter by 1 for inactive pixels. + Deactivate pixels that decided to jump and set their + counter to zero. +B_OP1 27:26 0x0 The branch state operation to perform if we do take the + jump. + + POSSIBLE VALUES: + 00 - US_FC_B_OP_NONE: If we do jump, don`t + alter the branch counter for any pixel. + 01 - US_FC_B_OP_DECR: If we do jump, + decrement branch counter by B_POP_CNT for inactive + pixels. Activate pixels with negative counters. + 02 - US_FC_B_OP_INCR: If we do jump, increment + branch counter by 1 for inactive pixels. Deactivate pixels + that decided not to jump and set their counter to zero. +IGNORE_UNCOVERED 28 0x0 If set, uncovered pixels will not participate in flow + control decisions. + + POSSIBLE VALUES: + 00 - Include uncovered pixels in jump decisions + 01 - Ignore uncovered pixels in making jump + decisions + + + +US:US_FC_INT_CONST_[0-31] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4c00-0x4c7c +DESCRIPTION: Integer Constants used by Flow Control Loop Instructions. Single buffered. +Field Name Bits Default Description +KR 7:0 0x0 Specifies the number of iterations. Unsigned 8-bit integer + in [0, 255]. +KG 15:8 0x0 Specifies the initial value of the loop register (aL). + Unsigned 8-bit integer in [0, 255]. +KB 23:16 0x0 Specifies the increment used to change the loop register + (aL) on each iteration. Signed 7-bit integer in [-128, + 127]. + + + +US:US_FORMAT0_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4640-0x467c +Field Name Bits Default Description +TXWIDTH 10:0 0x0 +TXHEIGHT 21:11 0x0 +TXDEPTH 25:22 0x0 POSSIBLE VALUES: + 13 - width > 2048, height <= 2048 + 14 - width <= 2048, height > 2048 + 15 - width > 2048, height > 2048 + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 246 + Revision 1.4 October 13, 2009 + + + + +US:US_OUT_FMT_[0-3] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x46a4-0x46b0 +Field Name Bits Default Description +OUT_FMT 4:0 0x0 POSSIBLE VALUES: + 00 - C4_8 (S/U) + 01 - C4_10 (U) + 02 - C4_10_GAMMA - (U) + 03 - C_16 - (S/U) + 04 - C2_16 - (S/U) + 05 - C4_16 - (S/U) + 06 - C_16_MPEG - (S) + 07 - C2_16_MPEG - (S) + 08 - C2_4 - (U) + 09 - C_3_3_2 - (U) + 10 - C_6_5_6 - (S/U) + 11 - C_11_11_10 - (S/U) + 12 - C_10_11_11 - (S/U) + 13 - C_2_10_10_10 - (S/U) + 14 - reserved + 15 - UNUSED - Render target is not used + 16 - C_16_FP - (S10E5) + 17 - C2_16_FP - (S10E5) + 18 - C4_16_FP - (S10E5) + 19 - C_32_FP - (S23E8) + 20 - C2_32_FP - (S23E8) + 21 - C4_32_FP - (S23E8) +C0_SEL 9:8 0x0 POSSIBLE VALUES: + 00 - Alpha + 01 - Red + 02 - Green + 03 - Blue +C1_SEL 11:10 0x0 POSSIBLE VALUES: + 00 - Alpha + 01 - Red + 02 - Green + 03 - Blue +C2_SEL 13:12 0x0 POSSIBLE VALUES: + 00 - Alpha + 01 - Red + 02 - Green + 03 - Blue +C3_SEL 15:14 0x0 POSSIBLE VALUES: + 00 - Alpha + 01 - Red + 02 - Green + 03 - Blue +OUT_SIGN 19:16 0x0 +ROUND_ADJ 20 0x0 POSSIBLE VALUES: + 00 - Normal rounding + 01 - Modified rounding of fixed-point data + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 247 + Revision 1.4 October 13, 2009 + + + + +US:US_PIXSIZE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4604 +DESCRIPTION: Shader pixel size. This register specifies the size and partitioning of the current pixel stack frame +Field Name Bits Default Description +PIX_SIZE 6:0 0x0 Specifies the total size of the current pixel stack frame + (1:128) + + + +US:US_TEX_ADDR_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x9800-0x9ffc +DESCRIPTION: Texture addresses and swizzles +Field Name Bits Default Description +SRC_ADDR 6:0 0x0 Specifies the location (within the shader pixel stack + frame) of the texture address for this instruction +SRC_ADDR_REL 7 0x0 Specifies whether the loop register is added to the value + of the associated address before it is used. This + implements relative addressing. + + POSSIBLE VALUES: + 00 - NONE: Do not modify source address + 01 - RELATIVE: Add aL before lookup. +SRC_S_SWIZ 9:8 0x0 Specify which colour channel of src_addr to use for S + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as S coordinate + 01 - Use G channel as S coordinate + 02 - Use B channel as S coordinate + 03 - Use A channel as S coordinate +SRC_T_SWIZ 11:10 0x0 Specify which colour channel of src_addr to use for T + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as T coordinate + 01 - Use G channel as T coordinate + 02 - Use B channel as T coordinate + 03 - Use A channel as T coordinate +SRC_R_SWIZ 13:12 0x0 Specify which colour channel of src_addr to use for R + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as R coordinate + 01 - Use G channel as R coordinate + 02 - Use B channel as R coordinate + 03 - Use A channel as R coordinate +SRC_Q_SWIZ 15:14 0x0 Specify which colour channel of src_addr to use for Q + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as Q coordinate +© 2008 Advanced Micro Devices, Inc. +Proprietary 248 + Revision 1.4 October 13, 2009 + + + + + 01 - Use G channel as Q coordinate + 02 - Use B channel as Q coordinate + 03 - Use A channel as Q coordinate +DST_ADDR 22:16 0x0 Specifies the location (within the shader pixel stack + frame) of the returned texture data for this instruction +DST_ADDR_REL 23 0x0 Specifies whether the loop register is added to the value + of the associated address before it is used. This + implements relative addressing. + + POSSIBLE VALUES: + 00 - NONE: Do not modify destination address + 01 - RELATIVE: Add aL before lookup. +DST_R_SWIZ 25:24 0x0 Specify which colour channel of the returned texture data + to write to the red channel of dst_addr + + POSSIBLE VALUES: + 00 - Write R channel to R channel + 01 - Write G channel to R channel + 02 - Write B channel to R channel + 03 - Write A channel to R channel +DST_G_SWIZ 27:26 0x0 Specify which colour channel of the returned texture data + to write to the green channel of dst_addr + + POSSIBLE VALUES: + 00 - Write R channel to G channel + 01 - Write G channel to G channel + 02 - Write B channel to G channel + 03 - Write A channel to G channel +DST_B_SWIZ 29:28 0x0 Specify which colour channel of the returned texture data + to write to the blue channel of dst_addr + + POSSIBLE VALUES: + 00 - Write R channel to B channel + 01 - Write G channel to B channel + 02 - Write B channel to B channel + 03 - Write A channel to B channel +DST_A_SWIZ 31:30 0x0 Specify which colour channel of the returned texture data + to write to the alpha channel of dst_addr + + POSSIBLE VALUES: + 00 - Write R channel to A channel + 01 - Write G channel to A channel + 02 - Write B channel to A channel + 03 - Write A channel to A channel + + + +US:US_TEX_ADDR_DXDY_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xa000-0xa7fc +DESCRIPTION: Additional texture addresses and swizzles for DX/DY inputs +Field Name Bits Default Description + +© 2008 Advanced Micro Devices, Inc. +Proprietary 249 + Revision 1.4 October 13, 2009 + + + + +DX_ADDR 6:0 0x0 Specifies the location (within the shader pixel stack + frame) of the DX value for this instruction +DX_ADDR_REL 7 0x0 Specifies whether the loop register is added to the value + of the associated address before it is used. This + implements relative addressing. + + POSSIBLE VALUES: + 00 - NONE: Do not modify source address + 01 - RELATIVE: Add aL before lookup. +DX_S_SWIZ 9:8 0x0 Specify which colour channel of dx_addr to use for S + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as S coordinate + 01 - Use G channel as S coordinate + 02 - Use B channel as S coordinate + 03 - Use A channel as S coordinate +DX_T_SWIZ 11:10 0x0 Specify which colour channel of dx_addr to use for T + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as T coordinate + 01 - Use G channel as T coordinate + 02 - Use B channel as T coordinate + 03 - Use A channel as T coordinate +DX_R_SWIZ 13:12 0x0 Specify which colour channel of dx_addr to use for R + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as R coordinate + 01 - Use G channel as R coordinate + 02 - Use B channel as R coordinate + 03 - Use A channel as R coordinate +DX_Q_SWIZ 15:14 0x0 Specify which colour channel of dx_addr to use for Q + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as Q coordinate + 01 - Use G channel as Q coordinate + 02 - Use B channel as Q coordinate + 03 - Use A channel as Q coordinate +DY_ADDR 22:16 0x0 Specifies the location (within the shader pixel stack + frame) of the DY value for this instruction +DY_ADDR_REL 23 0x0 Specifies whether the loop register is added to the value + of the associated address before it is used. This + implements relative addressing. + + POSSIBLE VALUES: + 00 - NONE: Do not modify source address + +© 2008 Advanced Micro Devices, Inc. +Proprietary 250 + Revision 1.4 October 13, 2009 + + + + + 01 - RELATIVE: Add aL before lookup. +DY_S_SWIZ 25:24 0x0 Specify which colour channel of dy_addr to use for S + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as S coordinate + 01 - Use G channel as S coordinate + 02 - Use B channel as S coordinate + 03 - Use A channel as S coordinate +DY_T_SWIZ 27:26 0x0 Specify which colour channel of dy_addr to use for T + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as T coordinate + 01 - Use G channel as T coordinate + 02 - Use B channel as T coordinate + 03 - Use A channel as T coordinate +DY_R_SWIZ 29:28 0x0 Specify which colour channel of dy_addr to use for R + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as R coordinate + 01 - Use G channel as R coordinate + 02 - Use B channel as R coordinate + 03 - Use A channel as R coordinate +DY_Q_SWIZ 31:30 0x0 Specify which colour channel of dy_addr to use for Q + coordinate + + POSSIBLE VALUES: + 00 - Use R channel as Q coordinate + 01 - Use G channel as Q coordinate + 02 - Use B channel as Q coordinate + 03 - Use A channel as Q coordinate + + + +US:US_TEX_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x9000-0x97fc +DESCRIPTION: Texture Instruction +Field Name Bits Default Description +TEX_ID 19:16 0x0 Specifies the id of the texture map used for this + instruction +INST 24:22 0x0 Specifies the operation taking place for this instruction + + POSSIBLE VALUES: + 00 - NOP: Do nothing + 01 - LD: Do Texture Lookup (S,T,R) + 02 - TEXKILL: Kill pixel if any component is < 0 + 03 - PROJ: Do projected texture lookup + (S/Q,T/Q,R/Q) + 04 - LODBIAS: Do texture lookup with lod bias + +© 2008 Advanced Micro Devices, Inc. +Proprietary 251 + Revision 1.4 October 13, 2009 + + + + + 05 - LOD: Do texture lookup with explicit lod + 06 - DXDY: Do texture lookup with lod calculated + from DX and DY +TEX_SEM_ACQUIRE 25 0x0 Whether to hold the texture semaphore until the data is + written to the temporary register. + + POSSIBLE VALUES: + 00 - Don`t hold the texture semaphore + 01 - Hold the texture semaphore until the data is + written to the temporary register. +IGNORE_UNCOVERED 26 0x0 If set, US will not request data for pixels which are + uncovered. Clear this bit for indirect texture lookups. + + POSSIBLE VALUES: + 00 - Fetch texels for uncovered pixels + 01 - Don`t fetch texels for uncovered pixels +UNSCALED 27 0x0 Whether to scale texture coordinates when sending them + to the texture unit. + + POSSIBLE VALUES: + 00 - Scale the S, T, R texture coordinates from + [0.0,1.0] to the dimensions of the target texture + 01 - Use the unscaled S, T, R texture coordates. + + + +US:US_W_FMT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x46b4 +DESCRIPTION: Specifies the source and format for the Depth (W) value output by the shader +Field Name Bits Default Description +W_FMT 1:0 0x0 Format for W + + POSSIBLE VALUES: + 00 - W0 - W is always zero + 01 - W24 - 24-bit fixed point + 02 - W24_FP - 24-bit floating point. The floating + point values are a special format that preserve sorting + order when values are compared as integers, allowing + higher precision in W without additional logic in other + blocks. + 03 - Reserved +W_SRC 2 0x0 Source for W + + POSSIBLE VALUES: + 00 - WSRC_US - W comes from shader instruction + 01 - WSRC_RAS - W comes from rasterizer + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 252 + Revision 1.4 October 13, 2009 + + + + +11.11 Vertex Registers + +VAP:VAP_ALT_NUM_VERTICES · [R/W] · 32 bits · Access: 32 · MMReg:0x2088 +DESCRIPTION: Alternate Number of Vertices to allow > 16-bits of Vertex count +Field Name Bits Default Description +NUM_VERTICES 23:0 0x0 24-bit vertex count for command packet. Used instead of + bits 31:16 of VAP_VF_CNTL if + VAP_VF_CNTL.USE_ALT_NUM_VERTS is set. + + + +VAP:VAP_CLIP_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x221c +DESCRIPTION: Control Bits for User Clip Planes and Clipping +Field Name Bits Default Description +UCP_ENA_0 0 0x0 Enable User Clip Plane 0 +UCP_ENA_1 1 0x0 Enable User Clip Plane 1 +UCP_ENA_2 2 0x0 Enable User Clip Plane 2 +UCP_ENA_3 3 0x0 Enable User Clip Plane 3 +UCP_ENA_4 4 0x0 Enable User Clip Plane 4 +UCP_ENA_5 5 0x0 Enable User Clip Plane 5 +PS_UCP_MODE 15:14 0x0 0 = Cull using distance from center of point + 1 = Cull using radius-based distance from center of + point + 2 = Cull using radius-based distance from center of + point, Expand and Clip on intersection + 3 = Always expand and clip as trifan +CLIP_DISABLE 16 0x0 Disables clip code generation and clipping process for + TCL +UCP_CULL_ONLY_ENA 17 0x0 Cull Primitives against UCPS, but don`t clip +BOUNDARY_EDGE_FLAG_ENA 18 0x0 If set, boundary edges are highlighted, else they are not + highlighted +COLOR2_IS_TEXTURE 20 0x0 If set, color2 is used as texture8 by GA (PS3.0 + requirement) +COLOR3_IS_TEXTURE 21 0x0 If set, color3 is used as texture9 by GA (PS3.0 + requirement) + + + +VAP:VAP_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x2080 +DESCRIPTION: Vertex Assembler/Processor Control Register +Field Name Bits Default Description +PVS_NUM_SLOTS 3:0 0x0 Specifies the number of vertex slots to be used in the + VAP PVS process. A slot represents a single vertex + storage location1 across multiple engines (one vertex per + engine). By decreasing the number of slots, there is more + memory for each vertex, but less parallel processing. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 253 + Revision 1.4 October 13, 2009 + + + + + Similarly, by increasing the number of slots, there is less + memory per vertex but more vertices being processed in + parallel. +PVS_NUM_CNTLRS 7:4 0x0 Specifies the maximum number of controllers to be + processing in parallel. In general should be set to max + value of TBD. Can be changed for performance analysis. +PVS_NUM_FPUS 11:8 0x0 Specifies the number of Floating Point Units + (Vector/Math Engines) to use when processing vertices. +VAP_NO_RENDER 17 0x0 If set, VAP will not process any draw commands (i.e. + writes to VAP_VF_CNTL, the INDX and DATAPORT + and Immediate mode writes are ignored. +VF_MAX_VTX_NUM 21:18 0x9 This field controls the number of vertices that the vertex + fetcher manages for the TCL and Setup Vertex Storage + memories (and therefore the number of vertices that can + be re-used). This value should be set to 12 for most + operation, This number may be modified for + performance evaluation. The value is the maximum + vertex number used which is one less than the number of + vertices (i.e. a 12 means 13 vertices will be used) +DX_CLIP_SPACE_DEF 22 0x0 Clip space is defined as: + 0: -W < X < W, -W < Y < W, -W < Z < W (OpenGL + Definition) + 1: -W < X < W, -W < Y < W, 0 < Z < W (DirectX + Definition) +TCL_STATE_OPTIMIZATION 23 0x0 If set, enables the TCL state optimization, and the new + state is used only if there is a change in TCL state, + between VF_CNTL (triggers) + + + +VAP:VAP_CNTL_STATUS · [R/W] · 32 bits · Access: 32 · MMReg:0x2140 +DESCRIPTION: Vertex Assemblen/Processor Control Status +Field Name Bits Default Description +VC_SWAP 1:0 0x0 Endian-Swap Control. + 0 = No swap 1 = 16-bit swap: 0xAABBCCDD becomes + 0xBBAADDCC + 2 = 32-bit swap: 0xAABBCCDD becomes + 0xDDCCBBAA + 3 = Half-dword swap: 0xAABBCCDD becomes + 0xCCDDAABB + Default = 0 +PVS_BYPASS 8 0x0 The TCL engine is logically or physically removed from + the circuit. +PVS_BUSY 11 0x0 Transform/Clip/Light (TCL) Engine is Busy. Read-only. +(Access: R) +MAX_MPS 19:16 0x0 Maximum number of MPs fused for this chip. Read- +(Access: R) only. + For A11, fusemask is fixed to 1XXX. + For A12, + +© 2008 Advanced Micro Devices, Inc. +Proprietary 254 + Revision 1.4 October 13, 2009 + + + + + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 000 + => max_mps[3:0] = 1XXX => 8 MPs + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 001 + => max_mps[3:0] = 0110 => 6 MPs + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 010 + => max_mps[3:0] = 0101 => 5 MPs + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 011 + => max_mps[3:0] = 0100 => 4 MPs + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 100 + => max_mps[3:0] = 0011 => 3 MPs + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 101 + => max_mps[3:0] = 0010 => 2 MPs + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 110 + => max_mps[3:0] = 0001 => 1 MP + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 111 + => max_mps[3:0] = 0000 => 0 MP + Note that max_mps[3:0] = 0111 = 7 MPs is not available +VS_BUSY 24 0x0 Vertex Store is Busy. Read-only. +(Access: R) +RCP_BUSY 25 0x0 Reciprocal Engine is Busy. Read-only. +(Access: R) +VTE_BUSY 26 0x0 ViewPort Transform Engine is Busy. Read-only. +(Access: R) +MIU_BUSY 27 0x0 Memory Interface Unit is Busy. Read-only. +(Access: R) +VC_BUSY 28 0x0 Vertex Cache is Busy. Read-only. +(Access: R) +VF_BUSY 29 0x0 Vertex Fetcher is Busy. Read-only. +(Access: R) +REGPIPE_BUSY 30 0x0 Register Pipeline is Busy. Read-only. +(Access: R) +VAP_BUSY 31 0x0 VAP Engine is Busy. Read-only. +(Access: R) + + + +VAP:VAP_GB_HORZ_CLIP_ADJ · [R/W] · 32 bits · Access: 32 · MMReg:0x2228 +DESCRIPTION: Horizontal Guard Band Clip Adjust Register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 32-bit floating point value. Should be set to 1.0 for no + guard band. + + + +VAP:VAP_GB_HORZ_DISC_ADJ · [R/W] · 32 bits · Access: 32 · MMReg:0x222c +DESCRIPTION: Horizontal Guard Band Discard Adjust Register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 32-bit floating point value. Should be set to 1.0 for no + guard band. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 255 + Revision 1.4 October 13, 2009 + + + + +VAP:VAP_GB_VERT_CLIP_ADJ · [R/W] · 32 bits · Access: 32 · MMReg:0x2220 +DESCRIPTION: Vertical Guard Band Clip Adjust Register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 32-bit floating point value. Should be set to 1.0 for no + guard band. + + + +VAP:VAP_GB_VERT_DISC_ADJ · [R/W] · 32 bits · Access: 32 · MMReg:0x2224 +DESCRIPTION: Vertical Guard Band Discard Adjust Register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 32-bit floating point value. Should be set to 1.0 for no + guard band. + + + +VAP:VAP_INDEX_OFFSET · [R/W] · 32 bits · Access: 32 · MMReg:0x208c +DESCRIPTION: Offset Value added to index value in both Indexed and Auto-indexed modes. Disabled by setting +to 0 +Field Name Bits Default Description +INDEX_OFFSET 24:0 0x0 25-bit signed 2`s comp offset value + + + +VAP:VAP_OUT_VTX_FMT_0 · [R/W] · 32 bits · Access: 32 · MMReg:0x2090 +DESCRIPTION: VAP Out/GA Vertex Format Register 0 +Field Name Bits Default Description +VTX_POS_PRESENT 0 0x0 Output the Position Vector +VTX_COLOR_0_PRESENT 1 0x0 Output Color 0 Vector +VTX_COLOR_1_PRESENT 2 0x0 Output Color 1 Vector +VTX_COLOR_2_PRESENT 3 0x0 Output Color 2 Vector +VTX_COLOR_3_PRESENT 4 0x0 Output Color 3 Vector +VTX_PT_SIZE_PRESENT 16 0x0 Output Point Size Vector + + + +VAP:VAP_OUT_VTX_FMT_1 · [R/W] · 32 bits · Access: 32 · MMReg:0x2094 +DESCRIPTION: VAP Out/GA Vertex Format Register 1 +Field Name Bits Default Description +TEX_0_COMP_CNT 2:0 0x0 Number of words in texture + 0 = Not Present + 1 = 1 component + 2 = 2 components + 3 = 3 components + 4 = 4 components + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 256 + Revision 1.4 October 13, 2009 + + + + +TEX_1_COMP_CNT 5:3 0x0 Number of words in texture + 0 = Not Present + 1 = 1 component + 2 = 2 components + 3 = 3 components + 4 = 4 components +TEX_2_COMP_CNT 8:6 0x0 Number of words in texture + 0 = Not Present + 1 = 1 component + 2 = 2 components + 3 = 3 components + 4 = 4 components +TEX_3_COMP_CNT 11:9 0x0 Number of words in texture + 0 = Not Present + 1 = 1 component + 2 = 2 components + 3 = 3 components + 4 = 4 components +TEX_4_COMP_CNT 14:12 0x0 Number of words in texture + 0 = Not Present + 1 = 1 component + 2 = 2 components + 3 = 3 components + 4 = 4 components +TEX_5_COMP_CNT 17:15 0x0 Number of words in texture + 0 = Not Present + 1 = 1 component + 2 = 2 components + 3 = 3 components + 4 = 4 components +TEX_6_COMP_CNT 20:18 0x0 Number of words in texture + 0 = Not Present + 1 = 1 component + 2 = 2 components + 3 = 3 components + 4 = 4 components +TEX_7_COMP_CNT 23:21 0x0 Number of words in texture + 0 = Not Present + 1 = 1 component + 2 = 2 components + 3 = 3 components + 4 = 4 components + + + +VAP:VAP_PORT_DATA[0-15] · [W] · 32 bits · Access: 32 · MMReg:0x2000-0x203c +DESCRIPTION: Setup Engine Data Port 0 through 15. +Field Name Bits Default Description +DATAPORT0 31:0 0x0 1st of 16 consecutive dwords for writing vertex data +(master with mirrors) information. + +© 2008 Advanced Micro Devices, Inc. +Proprietary 257 + Revision 1.4 October 13, 2009 + + + + + Write-only. + + + +VAP:VAP_PORT_DATA_IDX_128 · [W] · 32 bits · Access: 32 · MMReg:0x20b8 +DESCRIPTION: 128-bit Data Port for Indexed Primitives. +Field Name Bits Default Description +DATA_IDX_PORT_128 31:0 0x0 128-bit Data Port for Indexed Primitives. + Write-only. + + + +VAP:VAP_PORT_IDX[0-15] · [W] · 32 bits · Access: 32 · MMReg:0x2040-0x207c +DESCRIPTION: Setup Engine Index Port 0 through 15. +Field Name Bits Default Description +IDXPORT0 31:0 0x0 1st of 16 consecutive dwords for writing vertex index +(master with mirrors) information, in the format of: + 15:0 Index 0 + 31:16 Index 1 + Write-only. + + + +VAP:VAP_PROG_STREAM_CNTL_[0-7] · [R/W] · 32 bits · Access: 32 · MMReg:0x2150-0x216c +DESCRIPTION: Programmable Stream Control Word 0 +Field Name Bits Default Description +DATA_TYPE_0 3:0 0x0 The data type for element 0 + 0 = FLOAT_1 (Single IEEE Float) + 1 = FLOAT_2 (2 IEEE floats) + 2 = FLOAT_3 (3 IEEE Floats) + 3 = FLOAT_4 (4 IEEE Floats) + 4 = BYTE * (1 DWORD w 4 8-bit fixed point values) + (X = [7:0], Y = [15:8], Z = [23:16], W = [31:24]) + 5 = D3DCOLOR * (Same as BYTE except has X->Z,Z- + >X swap for D3D color def) + (Z = [7:0], Y = [15:8], X = [23:16], W = [31:24]) + 6 = SHORT_2 * (1 DWORD with 2 16-bit fixed point + values) + (X = [15:0], Y = [31:16], Z = 0.0, W = 1.0) + 7 = SHORT_4 * (2 DWORDS with 4(2 per dword) 16- + bit fixed point values) + (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 [15:0], + W = DW1 [31:16]) + 8 = VECTOR_3_TTT * (1 DWORD with 3 10-bit fixed + point values) + (X = [9:0], Y = [19:10], Z = [29:20], W = 1.0) + 9 = VECTOR_3_EET * (1 DWORD with 2 11-bit and 1 + 10-bit fixed point values) + (X = [10:0], Y = [21:11], Z = [31:22], W = 1.0) + 10 = FLOAT_8 (8 IEEE Floats) + Sames as 2 FLOAT_4 but must use consecutive + +© 2008 Advanced Micro Devices, Inc. +Proprietary 258 + Revision 1.4 October 13, 2009 + + + + + DST_VEC_LOC. Used to allow > 16 PSC for OGL path. + 11 = FLT16_2 (1 DWORD with 2 16-bit floating point + values (SE5M10 exp bias of 15, supports denormalized + numbers)) + (X = [15:0], Y = [31:16], Z = 0.0, W = 1.0) + 12 = FLT16_4 (2 DWORDS with 4(2 per dword) 16-bit + floating point values (SE5M10 exp bias of 15, supports + denormalized numbers))) + (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 [15:0], + W = DW1 [31:16]) + * These data types use the SIGNED and NORMALIZE + flags described below. +SKIP_DWORDS_0 7:4 0x0 The number of DWORDS to skip (discard) after + processing the current element. +DST_VEC_LOC_0 12:8 0x0 The vector address in the input memory to write this + element +LAST_VEC_0 13 0x0 If set, indicates the last vector of the current vertex + stream +SIGNED_0 14 0x0 Determines whether fixed point data types are unsigned + (0) or 2`s complement signed (1) data types. See + NORMALIZE for complete description of affect +NORMALIZE_0 15 0x0 Determines whether the fixed to floating point + conversion will normalize the value (i.e. fixed point + value is all fractional bits) or not (i.e. fixed point value is + all integer bits). + This table describes the fixed to float conversion results + SIGNED NORMALIZE FLT RANGE + 0 0 0.0 - (2^n - 1) (i.e. 8-bit -> 0.0 - 255.0) + 0 1 0.0 - 1.0 + 1 0 -2^(n-1) - (2^(n-1) - 1) (i.e. 8-bit -> -128.0 - 127.0) + 1 1 -1.0 - 1.0 + where n is the number of bits in the associated fixed + point value + For signed, normalize conversion, since the fixed point + range is not evenly distributed around 0, there are 3 + different methods supported by R300. See the + VAP_PSC_SGN_NORM_CNTL description for details. +DATA_TYPE_1 19:16 0x0 Similar to DATA_TYPE_0 +SKIP_DWORDS_1 23:20 0x0 See SKIP_DWORDS_0 +DST_VEC_LOC_1 28:24 0x0 See DST_VEC_LOC_0 +LAST_VEC_1 29 0x0 See LAST_VEC_0 +SIGNED_1 30 0x0 See SIGNED_0 +NORMALIZE_1 31 0x0 See NORMALIZE_0 + + + +VAP:VAP_PROG_STREAM_CNTL_EXT_[0-7] · [R/W] · 32 bits · Access: 32 · MMReg:0x21e0-0x21fc +DESCRIPTION: Programmable Stream Control Extension Word 0 +Field Name Bits Default Description + +© 2008 Advanced Micro Devices, Inc. +Proprietary 259 + Revision 1.4 October 13, 2009 + + + + +SWIZZLE_SELECT_X_0 2:0 0x0 X-Component Swizzle Select + 0 = SELECT_X + 1 = SELECT_Y + 2 = SELECT_Z + 3 = SELECT_W + 4 = SELECT_FP_ZERO (Floating Point 0.0) + 5 = SELECT_FP_ONE (Floating Point 1.0) + 6,7 RESERVED +SWIZZLE_SELECT_Y_0 5:3 0x0 Y-Component Swizzle Select (See Above) +SWIZZLE_SELECT_Z_0 8:6 0x0 Z-Component Swizzle Select (See Above) +SWIZZLE_SELECT_W_0 11:9 0x0 W-Component Swizzle Select (See Above) +WRITE_ENA_0 15:12 0x0 4-bit write enable. + Bit 0 maps to X + Bit 1 maps to Y + Bit 2 maps to Z + Bit 3 maps to W +SWIZZLE_SELECT_X_1 18:16 0x0 See SWIZZLE_SELECT_X_0 +SWIZZLE_SELECT_Y_1 21:19 0x0 See SWIZZLE_SELECT_Y_0 +SWIZZLE_SELECT_Z_1 24:22 0x0 See SWIZZLE_SELECT_Z_0 +SWIZZLE_SELECT_W_1 27:25 0x0 See SWIZZLE_SELECT_W_0 +WRITE_ENA_1 31:28 0x0 See WRITE_ENA_0 + + + +VAP:VAP_PSC_SGN_NORM_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x21dc +DESCRIPTION: Programmable Stream Control Signed Normalize Control +Field Name Bits Default Description +SGN_NORM_METHOD_0 1:0 0x0 There are 3 methods of normalizing signed numbers: + 0: SGN_NORM_ZERO : value / (2^(n-1)-1), so - + 128/127 will be less that -1.0, -127/127 will yeild -1.0, + 0/127 will yield 0, and 127/127 will yield 1.0 for 8-bit + numbers. + 1: SGN_NORM_ZERO_CLAMP_MINUS_ONE: Same + as SGN_NORM_ZERO except -128/127 will yield -1.0 + for 8-bit numbers. + 2: SGN_NORM_NO_ZERO: (2 * value + 1)/2^n, so - + 128 will yield -255/255 = -1.0, 127 will yield 255/255 = + 1.0, but 0 will yield 1/255 != 0. +SGN_NORM_METHOD_1 3:2 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_2 5:4 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_3 7:6 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_4 9:8 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_5 11:10 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_6 13:12 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_7 15:14 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_8 17:16 0x0 See SGN_NORM_METHOD_0 + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 260 + Revision 1.4 October 13, 2009 + + + + +SGN_NORM_METHOD_9 19:18 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_10 21:20 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_11 23:22 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_12 25:24 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_13 27:26 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_14 29:28 0x0 See SGN_NORM_METHOD_0 +SGN_NORM_METHOD_15 31:30 0x0 See SGN_NORM_METHOD_0 + + + +VAP:VAP_PVS_CODE_CNTL_0 · [R/W] · 32 bits · Access: 32 · MMReg:0x22d0 +DESCRIPTION: Programmable Vertex Shader Code Control Register 0 +Field Name Bits Default Description +PVS_FIRST_INST 9:0 0x0 First Instruction to Execute in PVS. +PVS_XYZW_VALID_INST 19:10 0x0 The PVS Instruction which updates the clip coordinate + position for the last time. This value is used to lower the + processing priority while trivial clip and back-face + culling decisions are made. This field must be set to valid + instruction. +PVS_LAST_INST 29:20 0x0 Last Instruction (Inclusive) for the PVS to execute. + + + +VAP:VAP_PVS_CODE_CNTL_1 · [R/W] · 32 bits · Access: 32 · MMReg:0x22d8 +DESCRIPTION: Programmable Vertex Shader Code Control Register 1 +Field Name Bits Default Description +PVS_LAST_VTX_SRC_INST 9:0 0x0 The PVS Instruction which uses the Input Vertex + Memory for the last time. This value is used to free up + the Input Vertex Slots ASAP. This field must be set to a + valid instruction. + + + +VAP:VAP_PVS_CONST_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x22d4 +DESCRIPTION: Programmable Vertex Shader Constant Control Register +Field Name Bits Default Description +PVS_CONST_BASE_OFFSET 7:0 0x0 Vector Offset into PVS constant memory to the start of + the constants for the current shader +PVS_MAX_CONST_ADDR 23:16 0x0 The maximum constant address which should be + generated by the shader (Inst Const Addr + Addr + Register). If the address which is generated by the shader + is outside the range of 0 to PVS_MAX_CONST_ADDR, + then (0,0,0,0) is returned as the source operand data. + + + +VAP:VAP_PVS_FLOW_CNTL_ADDRS_[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x2230-0x226c +DESCRIPTION: Programmable Vertex Shader Flow Control Addresses Register 0 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 261 + Revision 1.4 October 13, 2009 + + + + +Field Name Bits Default Description +PVS_FC_ACT_ADRS_0 7:0 0x0 This field defines the last PVS instruction to execute + prior to the control flow redirection. + JUMP - The last instruction executed prior to the jump + LOOP - The last instruction executed prior to the loop + (init loop counter/inc) + JSR - The last instruction executed prior to the jump to + the subroutine. +PVS_FC_LOOP_CNT_JMP_INST_0 15:8 0x0 This field has multiple definitions as follows: + JUMP - The instruction address to jump to. + LOOP - The loop count. *Note loop count of 0 must be + replaced by a jump. + JSR - The instruction address to jump to (first inst of + subroutine). +PVS_FC_LAST_INST_0 23:16 0x0 This field has multiple definitions as follows: + JUMP - Not Applicable + LOOP - The last instruction of the loop. + JSR - The last instruction of the subroutine. +PVS_FC_RTN_INST_0 31:24 0x0 This field has multiple definitions as follows: + JUMP - Not Applicable + LOOP - First Instruction of Loop (Typically + ACT_ADRS + 1) + JSR - First Instruction After JSR (Typically + ACT_ADRS + 1) + + + +VAP:VAP_PVS_FLOW_CNTL_ADDRS_LW_[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x2500- +0x2578 +DESCRIPTION: For VS3.0 - To support more PVS instructions, increase the address range - Programmable +Vertex Shader Flow Control Lower Word Addresses Register 0 +Field Name Bits Default Description +PVS_FC_ACT_ADRS_0 15:0 0x0 This field defines the last PVS instruction to execute + prior to the control flow redirection. + JUMP - The last instruction executed prior to the jump + LOOP - The last instruction executed prior to the loop + (init loop counter/inc) + JSR - The last instruction executed prior to the jump to + the subroutine. + (Addrss_Range:1K=[9:0];512=[8:0];256=[7:0]) +PVS_FC_LOOP_CNT_JMP_INST_0 31:16 0x0 This field has multiple definitions as follows: + JUMP - The instruction address to jump to. + LOOP - The loop count. *Note loop count of 0 must be + replaced by a jump. + JSR - The instruction address to jump to (first inst of + subroutine). + (Addrss_Range:1K=[24:15];512=[23:15];256=[22:15]) + + + +VAP:VAP_PVS_FLOW_CNTL_ADDRS_UW_[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x2504- + +© 2008 Advanced Micro Devices, Inc. +Proprietary 262 + Revision 1.4 October 13, 2009 + + + + +0x257c +DESCRIPTION: For VS3.0 - To support more PVS instructions, increase the address range - Programmable +Vertex Shader Flow Control Upper Word Addresses Register 0 +Field Name Bits Default Description +PVS_FC_LAST_INST_0 15:0 0x0 This field has multiple definitions as follows: + JUMP - Not Applicable + LOOP - The last instruction of the loop. + JSR - The last instruction of the subroutine. + (Addrss_Range:1K=[9:0];512=[8:0];256=[7:0]) +PVS_FC_RTN_INST_0 31:16 0x0 This field has multiple definitions as follows: + JUMP - Not Applicable + LOOP - First Instruction of Loop (Typically + ACT_ADRS + 1) + JSR - First Instruction After JSR (Typically ACT_ADRS + + 1). + (Addrss_Range:1K=[24:15];512=[23:15];256=[22:15]) + + + +VAP:VAP_PVS_FLOW_CNTL_LOOP_INDEX_[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x2290- +0x22cc +DESCRIPTION: Programmable Vertex Shader Flow Control Loop Index Register 0 +Field Name Bits Default Description +PVS_FC_LOOP_INIT_VAL_0 7:0 0x0 This field stores the automatic loop index register init + value. This is an 8-bit unsigned value 0-255. This field + is only used if the corresponding control flow + instruction is a loop. +PVS_FC_LOOP_STEP_VAL_0 15:8 0x0 This field stores the automatic loop index register step + value. This is an 8-bit 2`s comp signed value -128-127. + This field is only used if the corresponding control + flow instruction is a loop. +PVS_FC_LOOP_REPEAT_NO_FLI_0 31 0x0 When this field is set, the automatic loop index register + init value is not used at loop activation. The intial loop + index is inherited from outer loop. The loop index + register step value is used at the end of each loop + iteration ; after loop completion, the outer loop index + register is restored + + + +VAP:VAP_PVS_FLOW_CNTL_OPC · [R/W] · 32 bits · Access: 32 · MMReg:0x22dc +DESCRIPTION: Programmable Vertex Shader Flow Control Opcode Register +Field Name Bits Default Description +PVS_FC_OPC_0 1:0 0x0 This opcode field determines what type of control flow + instruction to execute. + 0 = NO_OP + 1 = JUMP + 2 = LOOP + 3 = JSR (Jump to Subroutine) + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 263 + Revision 1.4 October 13, 2009 + + + + +PVS_FC_OPC_1 3:2 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_2 5:4 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_3 7:6 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_4 9:8 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_5 11:10 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_6 13:12 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_7 15:14 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_8 17:16 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_9 19:18 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_10 21:20 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_11 23:22 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_12 25:24 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_13 27:26 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_14 29:28 0x0 See PVS_FC_OPC_0. +PVS_FC_OPC_15 31:30 0x0 See PVS_FC_OPC_0. + + + +VAP:VAP_PVS_STATE_FLUSH_REG · [R/W] · 32 bits · Access: 32 · MMReg:0x2284 +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 This register is used to force a flush of the PVS block +(Access: W) when single-buffered updates are performed. The multi- + state control of PVS Code and Const memories by the + driver is primarily for more flexible PVS state control + and for performance testing. When this register address + is written, the State Block will force a flush of PVS + processing so that both versions of PVS state are + available before updates are processed. This register is + write only, and the data that is written is unused. + + + +VAP:VAP_PVS_VECTOR_DATA_REG · [R/W] · 32 bits · Access: 32 · MMReg:0x2204 +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 32-bit data to write to Vector Memory. Used for PVS + code and Constant updates. + + + +VAP:VAP_PVS_VECTOR_DATA_REG_128 · [W] · 32 bits · Access: 32 · MMReg:0x2208 +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 128-bit data path to write to Vector Memory. Used for + PVS code and Constant updates. + + + +VAP:VAP_PVS_VECTOR_INDX_REG · [R/W] · 32 bits · Access: 32 · MMReg:0x2200 + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 264 + Revision 1.4 October 13, 2009 + + + + +Field Name Bits Default Description +OCTWORD_OFFSET 10:0 0x0 Octword offset to begin writing. + + + +VAP:VAP_PVS_VTX_TIMEOUT_REG · [R/W] · 32 bits · Access: 32 · MMReg:0x2288 +Field Name Bits Default Description +CLK_COUNT 31:0 0xFFFFFFFF This register is used to define the number of core clocks + to wait for a vertex to be received by the VAP input + controller (while the primitive path is backed up) before + forcing any accumulated vertices to be submitted to the + vertex processing path. + + + +VAP:VAP_TEX_TO_COLOR_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x2218 +DESCRIPTION: For VS3.0 color2texture - flat shading on textures - limitation: only first 8 vectors can have +clipping with wrap shortest or point sprite generated textures +Field Name Bits Default Description +TEX_RGB_SHADE_FUNC_0 0 0x0 + Default = 0 +TEX_ALPHA_SHADE_FUNC_0 1 0x0 + Default = 0 +TEX_RGBA_CLAMP_0 2 0x0 + Default = 0 +TEX_RGB_SHADE_FUNC_1 4 0x0 + Default = 0 +TEX_ALPHA_SHADE_FUNC_1 5 0x0 + Default = 0 +TEX_RGBA_CLAMP_1 6 0x0 + Default = 0 +TEX_RGB_SHADE_FUNC_2 8 0x0 + Default = 0 +TEX_ALPHA_SHADE_FUNC_2 9 0x0 + Default = 0 +TEX_RGBA_CLAMP_2 10 0x0 + Default = 0 +TEX_RGB_SHADE_FUNC_3 12 0x0 + Default = 0 +TEX_ALPHA_SHADE_FUNC_3 13 0x0 + Default = 0 +TEX_RGBA_CLAMP_3 14 0x0 + Default = 0 +TEX_RGB_SHADE_FUNC_4 16 0x0 + Default = 0 +TEX_ALPHA_SHADE_FUNC_4 17 0x0 + Default = 0 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 265 + Revision 1.4 October 13, 2009 + + + + +TEX_RGBA_CLAMP_4 18 0x0 + Default = 0 +TEX_RGB_SHADE_FUNC_5 20 0x0 + Default = 0 +TEX_ALPHA_SHADE_FUNC_5 21 0x0 + Default = 0 +TEX_RGBA_CLAMP_5 22 0x0 + Default = 0 +TEX_RGB_SHADE_FUNC_6 24 0x0 + Default = 0 +TEX_ALPHA_SHADE_FUNC_6 25 0x0 + Default = 0 +TEX_RGBA_CLAMP_6 26 0x0 + Default = 0 +TEX_RGB_SHADE_FUNC_7 28 0x0 + Default = 0 +TEX_ALPHA_SHADE_FUNC_7 29 0x0 + Default = 0 +TEX_RGBA_CLAMP_7 30 0x0 + Default = 0 + + + +VAP:VAP_VF_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x2084 +DESCRIPTION: Vertex Fetcher Control +Field Name Bits Default Description +PRIM_TYPE 3:0 0x0 Primitive Type + 0 : None (will not trigger Setup Engine to run) + 1 : Point List + 2 : Line List + 3 : Line Strip + 4 : Triangle List + 5 : Triangle Fan + 6 : Triangle Strip + 7 : Triangle with wFlags (aka, Rage128 `Type-2` + triangles) * + 8-11 : Unused + 12 : Line Loop + 13 : Quad List + 14 : Quad Strip + 15 : Polygon + *Encoding 7 indicates whether a 16-bit word of wFlags + is present in the stream of indices arriving when the + VTX_AMODE is programmed as a `0`. The Setup + Engine just steps over the wFlags word; ignoring it. + 0 = Stream contains just indices, as: + [ Index1, Index0] + [ Index3, Index2] + [ Index5, Index4 ] + +© 2008 Advanced Micro Devices, Inc. +Proprietary 266 + Revision 1.4 October 13, 2009 + + + + + etc... + 1 = Stream contains indices and wFlags: + [ Index1, Index0] + [ wFlags,Index 2 ] + [ Index4, Index3] + [ wFlags, Index5 ] + etc... +PRIM_WALK 5:4 0x0 Method of Passing Vertex Data. + 0 : State-Based Vertex Data. (Vertex data and tokens + embedded in command stream.) + 1 = Indexes (Indices embedded in command stream; + vertex data to be fetched from memory.) + 2 = Vertex List (Vertex data to be fetched from + memory.) + 3 = Vertex Data (Vertex data embedded in command + stream.) +RSVD_PREV_USED 10:6 0x0 Reserved bits +INDEX_SIZE 11 0x0 When set, vertex indices are 32-bits/indx, otherwise, 16- + bits/indx. +VTX_REUSE_DIS 12 0x0 When set, vertex reuse is disabled. DO NOT SET unless + PRIM_WALK is Indexes. +DUAL_INDEX_MODE 13 0x0 When set, the incoming index is treated as two separate + indices. Bits 23-16 are used as the index for AOS 0 + (These are 0 for 16-bit indices) Bits 15-0 are used as the + index for AOS 1-15. This mode was added specifically + for HOS usage +USE_ALT_NUM_VERTS 14 0x0 When set, the number of vertices in the command packet + is taken from VAP_ALT_NUM_VERTICES register + instead of bits 31:16 of VAP_VF_CNTL +NUM_VERTICES 31:16 0x0 Number of vertices in the command packet. + + + +VAP:VAP_VF_MAX_VTX_INDX · [R/W] · 32 bits · Access: 32 · MMReg:0x2134 +DESCRIPTION: Maximum Vertex Indx Clamp +Field Name Bits Default Description +MAX_INDX 23:0 0xFFFFFF If index to be fetched is larger than this value, the fetch + indx is set to MAX_INDX + + + +VAP:VAP_VF_MIN_VTX_INDX · [R/W] · 32 bits · Access: 32 · MMReg:0x2138 +DESCRIPTION: Minimum Vertex Indx Clamp +Field Name Bits Default Description +MIN_INDX 23:0 0x0 If index to be fetched is smaller than this value, the fetch + indx is set to MIN_INDX + + + +VAP:VAP_VPORT_XOFFSET · [R/W] · 32 bits · Access: 32 · MMReg:0x1d9c, MMReg:0x209c + +© 2008 Advanced Micro Devices, Inc. +Proprietary 267 + Revision 1.4 October 13, 2009 + + + + +DESCRIPTION: Viewport Transform X Offset +Field Name Bits Default Description +VPORT_XOFFSET 31:0 0x0 Viewport Offset for X coordinates. An IEEE float. + + + +VAP:VAP_VPORT_XSCALE · [R/W] · 32 bits · Access: 32 · MMReg:0x1d98, MMReg:0x2098 +DESCRIPTION: Viewport Transform X Scale Factor +Field Name Bits Default Description +VPORT_XSCALE 31:0 0x0 Viewport Scale Factor for X coordinates. An IEEE float. + + + +VAP:VAP_VPORT_YOFFSET · [R/W] · 32 bits · Access: 32 · MMReg:0x1da4, MMReg:0x20a4 +DESCRIPTION: Viewport Transform Y Offset +Field Name Bits Default Description +VPORT_YOFFSET 31:0 0x0 Viewport Offset for Y coordinates. An IEEE float. + + + +VAP:VAP_VPORT_YSCALE · [R/W] · 32 bits · Access: 32 · MMReg:0x1da0, MMReg:0x20a0 +DESCRIPTION: Viewport Transform Y Scale Factor +Field Name Bits Default Description +VPORT_YSCALE 31:0 0x0 Viewport Scale Factor for Y coordinates. An IEEE float. + + + +VAP:VAP_VPORT_ZOFFSET · [R/W] · 32 bits · Access: 32 · MMReg:0x1dac, MMReg:0x20ac +DESCRIPTION: Viewport Transform Z Offset +Field Name Bits Default Description +VPORT_ZOFFSET 31:0 0x0 Viewport Offset for Z coordinates. An IEEE float. + + + +VAP:VAP_VPORT_ZSCALE · [R/W] · 32 bits · Access: 32 · MMReg:0x1da8, MMReg:0x20a8 +DESCRIPTION: Viewport Transform Z Scale Factor +Field Name Bits Default Description +VPORT_ZSCALE 31:0 0x0 Viewport Scale Factor for Z coordinates. An IEEE float. + + + +VAP:VAP_VTE_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x20b0 +DESCRIPTION: Viewport Transform Engine Control +Field Name Bits Default Description +VPORT_X_SCALE_ENA 0 0x0 Viewport Transform Scale Enable for X component +VPORT_X_OFFSET_ENA 1 0x0 Viewport Transform Offset Enable for X component +VPORT_Y_SCALE_ENA 2 0x0 Viewport Transform Scale Enable for Y component +VPORT_Y_OFFSET_ENA 3 0x0 Viewport Transform Offset Enable for Y component +© 2008 Advanced Micro Devices, Inc. +Proprietary 268 + Revision 1.4 October 13, 2009 + + + + +VPORT_Z_SCALE_ENA 4 0x0 Viewport Transform Scale Enable for Z component +VPORT_Z_OFFSET_ENA 5 0x0 Viewport Transform Offset Enable for Z component +VTX_XY_FMT 8 0x0 Indicates that the incoming X, Y have already been + multiplied by 1/W0. + If OFF, the Setup Engine will bultiply the X, Y + coordinates by 1/W0., +VTX_Z_FMT 9 0x0 Indicates that the incoming Z has already been multiplied + by 1/W0. + If OFF, the Setup Engine will multiply the Z coordinate + by 1/W0. +VTX_W0_FMT 10 0x0 Indicates that the incoming W0 is not 1/W0. + If ON, the Setup Engine will perform the reciprocal to + get 1/W0. +SERIAL_PROC_ENA 11 0x0 If set, x,y,z viewport transform are performed serially + through a single pipeline instead of in parallel. Used to + mimic RL300 design. + + + +VAP:VAP_VTX_AOS_ADDR[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x20c8-0x2120 +DESCRIPTION: Array-of-Structures Address 0 +Field Name Bits Default Description +VTX_AOS_ADDR0 31:2 0x0 Base Address of the Array of Structures. + + + +VAP:VAP_VTX_AOS_ATTR[01-1415] · [R/W] · 32 bits · Access: 32 · MMReg:0x20c4-0x2118 +DESCRIPTION: Array-of-Structures Attributes 0 & 1 +Field Name Bits Default Description +VTX_AOS_COUNT0 6:0 0x0 Number of dwords in this structure. +VTX_AOS_STRIDE0 14:8 0x0 Number of dwords from one array element to the next. +VTX_AOS_COUNT1 22:16 0x0 Number of dwords in this structure. +VTX_AOS_STRIDE1 30:24 0x0 Number of dwords from one array element to the next. + + + +VAP:VAP_VTX_NUM_ARRAYS · [R/W] · 32 bits · Access: 32 · MMReg:0x20c0 +DESCRIPTION: Vertex Array of Structures Control +Field Name Bits Default Description +VTX_NUM_ARRAYS 4:0 0x0 The number of arrays required to represent the current + vertex type. + Each Array is described by the following three fields: + VTX_AOS_ADDR, VTX_AOS_COUNT, + VTX_AOS_STRIDE. +VC_FORCE_PREFETCH 5 0x0 Force Vertex Data Pre-fetching. If this bit is set, then a + 256-bit word will always be fetched, regardless of which + dwords are needed. Typically useful when + VAP_VF_CNTL.PRIM_WALK is set to Vertex List + +© 2008 Advanced Micro Devices, Inc. +Proprietary 269 + Revision 1.4 October 13, 2009 + + + + + (Auto-incremented indices). +VC_DIS_CACHE_INVLD 6 0x0 If set, the vertex cache is not invalidated between draw +(Access: R) packets. This allows vertex cache hits to occur from + packet to packet. This must be set with caution with + respect to multiple contexts in the driver. +AOS_0_FETCH_SIZE 16 0x0 Granule Size to Fetch for AOS 0. + 0 = 128-bit granule size + 1 = 256-bit granule size + This allows the driver to program the fetch size based on + DWORDS/VTX/AOS combined with AGP vs. LOC + Memory. The general belief is that the granule size + should always be 256-bits for LOC memory and AGP8X + data, but should be 128-bit for AGP2X/4X data if the + DWORDS/VTX/AOS is less than TBD (128?) bits. +AOS_1_FETCH_SIZE 17 0x0 See AOS_0_FETCH_SIZE +AOS_2_FETCH_SIZE 18 0x0 See AOS_0_FETCH_SIZE +AOS_3_FETCH_SIZE 19 0x0 See AOS_0_FETCH_SIZE +AOS_4_FETCH_SIZE 20 0x0 See AOS_0_FETCH_SIZE +AOS_5_FETCH_SIZE 21 0x0 See AOS_0_FETCH_SIZE +AOS_6_FETCH_SIZE 22 0x0 See AOS_0_FETCH_SIZE +AOS_7_FETCH_SIZE 23 0x0 See AOS_0_FETCH_SIZE +AOS_8_FETCH_SIZE 24 0x0 See AOS_0_FETCH_SIZE +AOS_9_FETCH_SIZE 25 0x0 See AOS_0_FETCH_SIZE +AOS_10_FETCH_SIZE 26 0x0 See AOS_0_FETCH_SIZE +AOS_11_FETCH_SIZE 27 0x0 See AOS_0_FETCH_SIZE +AOS_12_FETCH_SIZE 28 0x0 See AOS_0_FETCH_SIZE +AOS_13_FETCH_SIZE 29 0x0 See AOS_0_FETCH_SIZE +AOS_14_FETCH_SIZE 30 0x0 See AOS_0_FETCH_SIZE +AOS_15_FETCH_SIZE 31 0x0 See AOS_0_FETCH_SIZE + + + +VAP:VAP_VTX_SIZE · [R/W] · 32 bits · Access: 32 · MMReg:0x20b4 +DESCRIPTION: Vertex Size Specification Register +Field Name Bits Default Description +DWORDS_PER_VTX 6:0 0x0 This field specifies the number of DWORDS per vertex + to expect when VAP_VF_CNTL.PRIM_WALK is set to + Vertex Data (vertex data embedded in command stream). + This field is not used for any other PRIM_WALK + settings. This field replaces the usage of the + VAP_VTX_FMT_0/1 for this purpose in prior + implementations. + + + +VAP:VAP_VTX_STATE_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x2180 +DESCRIPTION: VAP Vertex State Control Register + +© 2008 Advanced Micro Devices, Inc. +Proprietary 270 + Revision 1.4 October 13, 2009 + + + + +Field Name Bits Default Description +COLOR_0_ASSEMBLY_CNTL 1:0 0x0 0 : Select Color 0 + 1 : Select User Color 0 + 2 : Select User Color 1 + 3 : Reserved +COLOR_1_ASSEMBLY_CNTL 3:2 0x0 0 : Select Color 1 + 1 : Select User Color 0 + 2 : Select User Color 1 + 3 : Reserved +COLOR_2_ASSEMBLY_CNTL 5:4 0x0 0 : Select Color 2 + 1 : Select User Color 0 + 2 : Select User Color 1 + 3 : Reserved +COLOR_3_ASSEMBLY_CNTL 7:6 0x0 0 : Select Color 3 + 1 : Select User Color 0 + 2 : Select User Color 1 + 3 : Reserved +COLOR_4_ASSEMBLY_CNTL 9:8 0x0 0 : Select Color 4 + 1 : Select User Color 0 + 2 : Select User Color 1 + 3 : Reserved +COLOR_5_ASSEMBLY_CNTL 11:10 0x0 0 : Select Color 5 + 1 : Select User Color 0 + 2 : Select User Color 1 + 3 : Reserved +COLOR_6_ASSEMBLY_CNTL 13:12 0x0 0 : Select Color 6 + 1 : Select User Color 0 + 2 : Select User Color 1 + 3 : Reserved +COLOR_7_ASSEMBLY_CNTL 15:14 0x0 0 : Select Color 7 + 1 : Select User Color 0 + 2 : Select User Color 1 + 3 : Reserved +UPDATE_USER_COLOR_0_ENA 16 0x0 0 : User Color 0 State is NOT updated when User Color + 0 is written. + 1 : User Color 1 State IS updated when User Color 0 is + written. +Reserved 18 0x0 Set to 0 + + + +VAP:VAP_VTX_ST_BLND_WT_[0-3] · [R/W] · 32 bits · Access: 32 · MMReg:0x2430-0x243c +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 BLND_WT_0 + + + +VAP:VAP_VTX_ST_CLR_[0-7]_A · [R/W] · 32 bits · Access: 32 · MMReg:0x232c-0x239c + +© 2008 Advanced Micro Devices, Inc. +Proprietary 271 + Revision 1.4 October 13, 2009 + + + + +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 CLR_0_A + + + +VAP:VAP_VTX_ST_CLR_[0-7]_B · [R/W] · 32 bits · Access: 32 · MMReg:0x2328-0x2398 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 CLR_0_B + + + +VAP:VAP_VTX_ST_CLR_[0-7]_G · [R/W] · 32 bits · Access: 32 · MMReg:0x2324-0x2394 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 CLR_0_G + + + +VAP:VAP_VTX_ST_CLR_[0-7]_PKD · [W] · 32 bits · Access: 32 · MMReg:0x2470-0x248c +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 CLR_0_PKD + + + +VAP:VAP_VTX_ST_CLR_[0-7]_R · [R/W] · 32 bits · Access: 32 · MMReg:0x2320-0x2390 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 CLR_0_R + + + +VAP:VAP_VTX_ST_DISC_FOG · [R/W] · 32 bits · Access: 32 · MMReg:0x2424 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 DISC_FOG + + + +VAP:VAP_VTX_ST_EDGE_FLAGS · [R/W] · 32 bits · Access: 32 · MMReg:0x245c +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 0 0x0 EDGE_FLAGS + + + +VAP:VAP_VTX_ST_END_OF_PKT · [W] · 32 bits · Access: 32 · MMReg:0x24ac + +© 2008 Advanced Micro Devices, Inc. +Proprietary 272 + Revision 1.4 October 13, 2009 + + + + +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 END_OF_PKT + + + +VAP:VAP_VTX_ST_NORM_0_PKD · [W] · 32 bits · Access: 32 · MMReg:0x2498 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 NORM_0_PKD + + + +VAP:VAP_VTX_ST_NORM_0_X · [R/W] · 32 bits · Access: 32 · MMReg:0x2310 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 NORM_0_X + + + +VAP:VAP_VTX_ST_NORM_0_Y · [R/W] · 32 bits · Access: 32 · MMReg:0x2314 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 NORM_0_Y + + + +VAP:VAP_VTX_ST_NORM_0_Z · [R/W] · 32 bits · Access: 32 · MMReg:0x2318 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 NORM_0_Z + + + +VAP:VAP_VTX_ST_NORM_1_X · [R/W] · 32 bits · Access: 32 · MMReg:0x2450 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 NORM_1_X + + + +VAP:VAP_VTX_ST_NORM_1_Y · [R/W] · 32 bits · Access: 32 · MMReg:0x2454 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 NORM_1_Y + + + +VAP:VAP_VTX_ST_NORM_1_Z · [R/W] · 32 bits · Access: 32 · MMReg:0x2458 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 273 + Revision 1.4 October 13, 2009 + + + + +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 NORM_1_Z + + + +VAP:VAP_VTX_ST_PNT_SPRT_SZ · [R/W] · 32 bits · Access: 32 · MMReg:0x2420 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 PNT_SPRT_SZ + + + +VAP:VAP_VTX_ST_POS_0_W_4 · [R/W] · 32 bits · Access: 32 · MMReg:0x230c +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_0_W + + + +VAP:VAP_VTX_ST_POS_0_X_2 · [W] · 32 bits · Access: 32 · MMReg:0x2490 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_0_X_2 + + + +VAP:VAP_VTX_ST_POS_0_X_3 · [W] · 32 bits · Access: 32 · MMReg:0x24a0 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_0_X_3 + + + +VAP:VAP_VTX_ST_POS_0_X_4 · [R/W] · 32 bits · Access: 32 · MMReg:0x2300 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_0_X + + + +VAP:VAP_VTX_ST_POS_0_Y_2 · [W] · 32 bits · Access: 32 · MMReg:0x2494 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_0_Y_2 + + + +VAP:VAP_VTX_ST_POS_0_Y_3 · [W] · 32 bits · Access: 32 · MMReg:0x24a4 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 274 + Revision 1.4 October 13, 2009 + + + + +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_0_Y_3 + + + +VAP:VAP_VTX_ST_POS_0_Y_4 · [R/W] · 32 bits · Access: 32 · MMReg:0x2304 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_0_Y + + + +VAP:VAP_VTX_ST_POS_0_Z_3 · [W] · 32 bits · Access: 32 · MMReg:0x24a8 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_0_Z_3 + + + +VAP:VAP_VTX_ST_POS_0_Z_4 · [R/W] · 32 bits · Access: 32 · MMReg:0x2308 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_0_Z + + + +VAP:VAP_VTX_ST_POS_1_W · [R/W] · 32 bits · Access: 32 · MMReg:0x244c +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_1_W + + + +VAP:VAP_VTX_ST_POS_1_X · [R/W] · 32 bits · Access: 32 · MMReg:0x2440 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_1_X + + + +VAP:VAP_VTX_ST_POS_1_Y · [R/W] · 32 bits · Access: 32 · MMReg:0x2444 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_1_Y + + + +VAP:VAP_VTX_ST_POS_1_Z · [R/W] · 32 bits · Access: 32 · MMReg:0x2448 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 275 + Revision 1.4 October 13, 2009 + + + + +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 POS_1_Z + + + +VAP:VAP_VTX_ST_PVMS · [R/W] · 32 bits · Access: 32 · MMReg:0x231c +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 PVMS + + + +VAP:VAP_VTX_ST_SHININESS_0 · [R/W] · 32 bits · Access: 32 · MMReg:0x2428 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 SHININESS_0 + + + +VAP:VAP_VTX_ST_SHININESS_1 · [R/W] · 32 bits · Access: 32 · MMReg:0x242c +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 SHININESS_1 + + + +VAP:VAP_VTX_ST_TEX_[0-7]_Q · [R/W] · 32 bits · Access: 32 · MMReg:0x23ac-0x241c +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 TEX_0_Q + + + +VAP:VAP_VTX_ST_TEX_[0-7]_R · [R/W] · 32 bits · Access: 32 · MMReg:0x23a8-0x2418 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 TEX_0_R + + + +VAP:VAP_VTX_ST_TEX_[0-7]_S · [R/W] · 32 bits · Access: 32 · MMReg:0x23a0-0x2410 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 TEX_0_S + + + +VAP:VAP_VTX_ST_TEX_[0-7]_T · [R/W] · 32 bits · Access: 32 · MMReg:0x23a4-0x2414 + +© 2008 Advanced Micro Devices, Inc. +Proprietary 276 + Revision 1.4 October 13, 2009 + + + + +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 TEX_0_T + + + +VAP:VAP_VTX_ST_USR_CLR_A · [R/W] · 32 bits · Access: 32 · MMReg:0x246c +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 USR_CLR_A + + + +VAP:VAP_VTX_ST_USR_CLR_B · [R/W] · 32 bits · Access: 32 · MMReg:0x2468 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 USR_CLR_B + + + +VAP:VAP_VTX_ST_USR_CLR_G · [R/W] · 32 bits · Access: 32 · MMReg:0x2464 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 USR_CLR_G + + + +VAP:VAP_VTX_ST_USR_CLR_PKD · [W] · 32 bits · Access: 32 · MMReg:0x249c +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 USR_CLR_PKD + + + +VAP:VAP_VTX_ST_USR_CLR_R · [R/W] · 32 bits · Access: 32 · MMReg:0x2460 +DESCRIPTION: Data register +Field Name Bits Default Description +DATA_REGISTER 31:0 0x0 USR_CLR_R + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 277 + Revision 1.4 October 13, 2009 + + + + +11.12 Z Buffer Registers + + +ZB:ZB_BW_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f1c +DESCRIPTION: Z Buffer Band-Width Control + Defa +Field Name Bits Description + ult +HIZ_ENABLE 0 0x0 Enables hierarchical Z. + + POSSIBLE VALUES: + 00 - Hierarchical Z Disabled + 01 - Hierarchical Z Enabled +HIZ_MIN 1 0x0 POSSIBLE VALUES: + 00 - Update Hierarchical Z with Max value + 01 - Update Hierarchical Z with Min value +FAST_FILL 2 0x0 POSSIBLE VALUES: + 00 - Fast Fill Disabled + 01 - Fast Fill Enabled (ZB_DEPTHCLEARVALUE ) +RD_COMP_ENABLE 3 0x0 Enables reading of compressed Z data from memory to the + cache. + + POSSIBLE VALUES: + 00 - Z Read Compression Disabled + 01 - Z Read Compression Enabled +WR_COMP_ENABLE 4 0x0 Enables writing of compressed Z data from cache to memory, + + POSSIBLE VALUES: + 00 - Z Write Compression Disabled + 01 - Z Write Compression Enabled +ZB_CB_CLEAR 5 0x0 This bit is set when the Z buffer is used to help the CB in + clearing a region. Part of the region is cleared by the color + buffer and part will be cleared by the Z buffer. Since the Z + buffer does not have any write masks in the cache, full micro- + tiles need to be written. If a partial micro-tile is touched, then + the un-touched part will be unknowns. The cache will operate + in write-allocate mode and quads will be accumulated in the + cache and then evicted to main memory. The color value is + supplied through the ZB_DEPTHCLEARVALUE register. + + POSSIBLE VALUES: + 00 - Z unit cache controller does RMW + 01 - Z unit cache controller does cache-line granular Write + only +FORCE_COMPRESSED_STENCIL_V 6 0x0 Enabling this bit will force all the compressed stencil values +ALUE to be equal to + old_stencil_value&~ZB_STENCILREFMASK.stencilwritem + ask | + ZB_STENCILREFMASK.stencilref&ZB_STENCILREFMA + +© 2008 Advanced Micro Devices, Inc. +Proprietary 278 + Revision 1.4 October 13, 2009 + + + + + SK.stencilwritemask. This should be enabled during stencil + clears to avoid needless decompression. + + POSSIBLE VALUES: + 00 - Do not force the compressed stencil value. + 01 - Force the compressed stencil value. +ZEQUAL_OPTIMIZE_DISABLE 7 0x0 By default this is 0 (enabled). When NEWZ=OLDZ, then + writes do not occur to save BW. + + POSSIBLE VALUES: + 00 - Enable not updating the Z buffer if NewZ=OldZ + 01 - Disable above feature (in case there is a bug) +SEQUAL_OPTIMIZE_DISABLE 8 0x0 By default this is 0 (enabled). When + NEW_STENCIL=OLD_STENCIL, then writes do not occur + to save BW. + + POSSIBLE VALUES: + 00 - Enable not updating the Stencil buffer if NewS=OldS + 01 - Disable above feature (in case there is a bug) +BMASK_DISABLE 10 0x0 Controls whether bytemasking is used or not. + + POSSIBLE VALUES: + 00 - Enable bytemasking + 01 - Disable bytemasking +HIZ_EQUAL_REJECT_ENABLE 11 0x0 Enables hiz rejects when the z function is equals. + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable +HIZ_FP_EXP_BITS 14: 0x0 Number of exponent bits to use for the hiz floating point + 12 format. Values 0 to 5 are legal. 0 will disable the floating + point hiz encoding. +HIZ_FP_INVERT 15 0x0 Determines whether leading zeros or ones are eliminated. + + POSSIBLE VALUES: + 00 - Count leading 1s + 01 - Count leading 0s +TILE_OVERWRITE_RECOMPRESSI 16 0x0 The zb tries to detect single plane equations that completely +ON_DISABLE overwrite a compressed tile. This allows the tile to jump from + the decompressed state to the fully compressed state. + + POSSIBLE VALUES: + 00 - Enable tile overwrite recompression + 01 - Disable tile overwrite recompression +CONTIGUOUS_6XAA_SAMPLES_DI 17 0x0 This disables storing samples contiguously in 6xaa. +SABLE + POSSIBLE VALUES: + 00 - Enable contiguous samples + 01 - Disable contiguous samples + +© 2008 Advanced Micro Devices, Inc. +Proprietary 279 + Revision 1.4 October 13, 2009 + + + + +PEQ_PACKING_ENABLE 18 0x0 Enables packing of the plane equations to eliminate wasted + peq slots. + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable +COVERED_PTR_MASKING_ENABL 19 0x0 Enables discarding of pointers from pixels that are going to be +E covered. This reduces the apparent number of plane equations + in use. + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable + + + +ZB:ZB_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f00 +DESCRIPTION: Z Buffer Control +Field Name Bits Default Description +STENCIL_ENABLE 0 0x0 Enables stenciling. + + POSSIBLE VALUES: + 00 - Disabled + 01 - Enabled +Z_ENABLE 1 0x0 Enables Z functions. + + POSSIBLE VALUES: + 00 - Disabled + 01 - Enabled +ZWRITEENABLE 2 0x0 Enables writing of the Z buffer. + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable +ZSIGNED_COMPARE 3 0x0 Enable signed Z buffer comparison , for W-buffering. + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable +STENCIL_FRONT_BACK 4 0x0 When STENCIL_ENABLE is set, setting + STENCIL_FRONT_BACK bit to one specifies that + stencilfunc/stencilfail/stencilzpass/stencilzfail registers are + used if the quad is generated from front faced primitive + and + stencilfunc_bf/stencilfail_bf/stencilzpass_bf/stencilzfail_bf + are used if the quad is generated from a back faced + primitive. If the STENCIL_FRONT_BACK is not set, + then stencilfunc/stencilfail/stencilzpass/stencilzfail + registers determine the operation independent of the + front/back face state of the quad. +© 2008 Advanced Micro Devices, Inc. +Proprietary 280 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable +ZSIGNED_MAGNITUDE 5 0x0 Specifies the signed number type to use for the Z buffer + comparison. This only has an effect when + ZSIGNED_COMPARE is enabled. + + POSSIBLE VALUES: + 00 - Twos complement + 01 - Signed magnitude +STENCIL_REFMASK_FRONT_BACK 6 0x0 POSSIBLE VALUES: + 00 - Disable + 01 - Enable + + + +ZB:ZB_DEPTHCLEARVALUE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f28 +DESCRIPTION: Z Buffer Clear Value +Field Name Bits Default Description +DEPTHCLEARVALUE 31:0 0x0 When a block has a Z Mask value of 0, all Z values in + that block are cleared to this value. In 24bpp, the stencil + value is also updated regardless of whether it is enabled + or not. + + + +ZB:ZB_DEPTHOFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f20 +DESCRIPTION: Z Buffer Address Offset +Field Name Bits Default Description +DEPTHOFFSET 31:5 0x0 2K aligned Z buffer address offset for macro tiles. + + + +ZB:ZB_DEPTHPITCH · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f24 +DESCRIPTION: Z Buffer Pitch and Endian Control +Field Name Bits Default Description +DEPTHPITCH 13:2 0x0 Z buffer pitch in multiples of 4 pixels. +DEPTHMACROTILE 16 0x0 Specifies whether Z buffer is macro-tiled. macro-tiles are + 2K aligned + + POSSIBLE VALUES: + 00 - macro tiling disabled + 01 - macro tiling enabled +DEPTHMICROTILE 18:17 0x0 Specifies whether Z buffer is micro-tiled. micro-tiles is + 32 bytes + + POSSIBLE VALUES: + 00 - 32 byte cache line is linear + +© 2008 Advanced Micro Devices, Inc. +Proprietary 281 + Revision 1.4 October 13, 2009 + + + + + 01 - 32 byte cache line is tiled + 02 - 32 byte cache line is tiled square (only applies to + 16-bit pixels) + 03 - Reserved +DEPTHENDIAN 20:19 0x0 Specifies endian control for the Z buffer. + + POSSIBLE VALUES: + 00 - No swap + 01 - Word swap + 02 - Dword swap + 03 - Half Dword swap + + + +ZB:ZB_DEPTHXY_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f60 +DESCRIPTION: Depth buffer X and Y coordinate offset +Field Name Bits Default Description +DEPTHX_OFFSET 11:1 0x0 X coordinate offset. multiple of 32 . Bits 4:0 have to be + zero +DEPTHY_OFFSET 27:17 0x0 Y coordinate offset. multiple of 32 . Bits 4:0 have to be + zero + + + +ZB:ZB_FIFO_SIZE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4fd0 +DESCRIPTION: Sets the fifo sizes +Field Name Bits Default Description +OP_FIFO_SIZE 1:0 0x0 Determines the size of the op fifo + + POSSIBLE VALUES: + 00 - Full size + 01 - 1/2 size + 02 - 1/4 size + 03 - 1/8 size + + + +ZB:ZB_FORMAT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f10 +DESCRIPTION: Format of the Data in the Z buffer +Field Name Bits Default Description +DEPTHFORMAT 3:0 0x0 Specifies the format of the Z buffer. + + POSSIBLE VALUES: + 00 - 16-bit Integer Z + 01 - 16-bit compressed 13E3 + 02 - 24-bit Integer Z, 8 bit Stencil (LSBs) + 03 - RESERVED + 04 - RESERVED + 05 - RESERVED + 06 - RESERVED + +© 2008 Advanced Micro Devices, Inc. +Proprietary 282 + Revision 1.4 October 13, 2009 + + + + + 07 - RESERVED + 08 - RESERVED + 09 - RESERVED + 10 - RESERVED + 11 - RESERVED + 12 - RESERVED + 13 - RESERVED + 14 - RESERVED + 15 - RESERVED +INVERT 4 0x0 POSSIBLE VALUES: + 00 - in 13E3 format , count leading 1`s + 01 - in 13E3 format , count leading 0`s. +PEQ8 5 0x0 This bit is unused + + + +ZB:ZB_HIZ_DWORD · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f4c +DESCRIPTION: Hierarchical Z Data +Field Name Bits Default Description +HIZ_DWORD 31:0 0x0 This DWORD contains 8-bit values for 4 blocks.. + Reading this register causes a read from the address + pointed to by RDINDEX. Writing to this register causes + a write to the address pointed to by WRINDEX. + + + +ZB:ZB_HIZ_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f44 +DESCRIPTION: Hierarchical Z Memory Offset +Field Name Bits Default Description +HIZ_OFFSET 17:2 0x0 DWORD offset into HiZ RAM. + + + +ZB:ZB_HIZ_PITCH · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f54 +DESCRIPTION: Hierarchical Z Pitch +Field Name Bits Default Description +HIZ_PITCH 13:4 0x0 Pitch used in HiZ address computation. + + + +ZB:ZB_HIZ_RDINDEX · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f50 +DESCRIPTION: Hierarchical Z Read Index +Field Name Bits Default Description +HIZ_RDINDEX 17:2 0x0 Read index into HiZ RAM. + + + +ZB:ZB_HIZ_WRINDEX · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f48 +DESCRIPTION: Hierarchical Z Write Index +Field Name Bits Default Description +© 2008 Advanced Micro Devices, Inc. +Proprietary 283 + Revision 1.4 October 13, 2009 + + + + +HIZ_WRINDEX 17:2 0x0 Self-incrementing write index into the HiZ RAM. + Starting write index must start on a DWORD boundary. + Each time ZB_HIZ_DWORD is written, this index will + autoincrement. HIZ_OFFSET and HIZ_PITCH are not + used to compute read/write address to HIZ ram, when it + is accessed through WRINDEX and DWORD + + + +ZB:ZB_STENCILREFMASK · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f08 +DESCRIPTION: Stencil Reference Value and Mask +Field Name Bits Default Description +STENCILREF 7:0 0x0 Specifies the reference stencil value. +STENCILMASK 15:8 0x0 This value is ANDed with both the reference and the + current stencil value prior to the stencil test. +STENCILWRITEMASK 23:16 0x0 Specifies the write mask for the stencil planes. + + + +ZB:ZB_STENCILREFMASK_BF · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4fd4 +DESCRIPTION: Stencil Reference Value and Mask for backfacing quads +Field Name Bits Default Description +STENCILREF 7:0 0x0 Specifies the reference stencil value. +STENCILMASK 15:8 0x0 This value is ANDed with both the reference and the + current stencil value prior to the stencil test. +STENCILWRITEMASK 23:16 0x0 Specifies the write mask for the stencil planes. + + + +ZB:ZB_ZCACHE_CTLSTAT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f18 +DESCRIPTION: Z Buffer Cache Control/Status +Field Name Bits Default Description +ZC_FLUSH 0 0x0 Setting this bit flushes the dirty data from the Z cache. + Unless ZC_FREE bit is also set, the tags in the cache + remain valid. A purge is achieved by setting both + ZC_FLUSH and ZC_FREE. This is a sticky bit and it + clears itself at the end of the operation. + + POSSIBLE VALUES: + 00 - No effect + 01 - Flush and Free Z cache lines +ZC_FREE 1 0x0 Setting this bit invalidates the Z cache tags. Unless + ZC_FLUSH bit is also set, the cachelines are not written + to memory. A purge is achieved by setting both + ZC_FLUSH and ZC_FREE. This is a sticky bit that + clears itself at the end of the operation. + + POSSIBLE VALUES: + 00 - No effect + +© 2008 Advanced Micro Devices, Inc. +Proprietary 284 + Revision 1.4 October 13, 2009 + + + + + 01 - Free Z cache lines (invalidate) +ZC_BUSY 31 0x0 This bit is unused ... + + POSSIBLE VALUES: + 00 - Idle + 01 - Busy + + + +ZB:ZB_ZPASS_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f5c +DESCRIPTION: Z Buffer Z Pass Counter Address +Field Name Bits Default Description +ZPASS_ADDR 31:2 0x0 Writing this location with a DWORD address causes the + value in ZB_ZPASS_DATA to be written to main + memory at the location pointed to by this address. + NOTE: R300 has 2 pixel pipes. Broadcasting this address + causes both pipes to write their ZPASS value to the same + address. There is no guarantee which pipe will write last. + So when writing to this register, the GA needs to be + programmed to send the write command to pipe 0. Then + a different address needs to be written to pipe 1. Then + both pipes should be enabled for further register writes. + + + +ZB:ZB_ZPASS_DATA · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f58 +DESCRIPTION: Z Buffer Z Pass Counter Data +Field Name Bits Default Description +ZPASS_DATA 31:0 0x0 Contains the number of Z passed pixels since the last + write to this location. Writing this location resets the + count to the value written. + + + +ZB:ZB_ZSTENCILCNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f04 +DESCRIPTION: Z and Stencil Function Control +Field Name Bits Default Description +ZFUNC 2:0 0x0 Specifies the Z function. + + POSSIBLE VALUES: + 00 - Never + 01 - Less + 02 - Less or Equal + 03 - Equal + 04 - Greater or Equal + 05 - Greater Than + 06 - Not Equal + 07 - Always +STENCILFUNC 5:3 0x0 Specifies the stencil function. + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 285 + Revision 1.4 October 13, 2009 + + + + + POSSIBLE VALUES: + 00 - Never + 01 - Less + 02 - Less or Equal + 03 - Equal + 04 - Greater or Equal + 05 - Greater + 06 - Not Equal + 07 - Always +STENCILFAIL 8:6 0x0 Specifies the stencil value to be written if the stencil test + fails. + + POSSIBLE VALUES: + 00 - Keep: New value = Old value + 01 - Zero: New value = 0 + 02 - Replace: New value = STENCILREF + 03 - Increment: New value++ (clamp) + 04 - Decrement: New value-- (clamp) + 05 - Invert new value: New value = !Old value + 06 - Increment: New value++ (wrap) + 07 - Decrement: New value-- (wrap) +STENCILZPASS 11:9 0x0 Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + passes (or is not enabled). +STENCILZFAIL 14:12 0x0 Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + fails. +STENCILFUNC_BF 17:15 0x0 Same encoding as STENCILFUNC. Specifies the stencil + function for back faced quads , if + STENCIL_FRONT_BACK = 1. +STENCILFAIL_BF 20:18 0x0 Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test fails for back faced + quads, if STENCIL_FRONT_BACK = 1 +STENCILZPASS_BF 23:21 0x0 Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + passes (or is not enabled) for back faced quads, if + STENCIL_FRONT_BACK = 1 +STENCILZFAIL_BF 26:24 0x0 Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + fails for back faced quads, if STENCIL_FRONT_BACK + =1 +ZERO_OUTPUT_MASK 27 0x0 Zeroes the zb coverage mask output. This does not affect + the updating of the depth or stencil values. + + POSSIBLE VALUES: + 00 - Disable + 01 - Enable + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 286 + Revision 1.4 October 13, 2009 + + + + +ZB:ZB_ZTOP · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f14 +Field Name Bits Default Description +ZTOP 0 0x0 POSSIBLE VALUES: + 00 - Z is at the bottom of the pipe, after the fog unit. + 01 - Z is at the top of the pipe, after the scan unit. + + + + +© 2008 Advanced Micro Devices, Inc. +Proprietary 287 |