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| author | Rohan Garg <rohan.garg@intel.com> | 2022-07-26 15:01:57 +0200 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2024-03-29 23:35:35 -0700 |
| commit | 2cdad60174ce00c3081ab88c54d2b19efda118d0 (patch) | |
| tree | 7ff086cb1d6f194aac3bc1874fbf21b13e3e4ea6 | |
| parent | 7e4b94a39944be33b0cec6e1b9a847ad600686ee (diff) | |
intel/eu/validate: Allow SIMD16 for mixed mode float operations on xe2+xe2-compiler-2-subset-2
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
| -rw-r--r-- | src/intel/compiler/brw_eu_validate.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index 8a8b3d10b75..03a55c83a5b 100644 --- a/src/intel/compiler/brw_eu_validate.c +++ b/src/intel/compiler/brw_eu_validate.c @@ -1137,7 +1137,8 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, * "No SIMD16 in mixed mode when destination is f32. Instruction * execution size must be no more than 8." */ - ERROR_IF(exec_size > 8 && dst_type == BRW_REGISTER_TYPE_F && + ERROR_IF(exec_size > 8 && devinfo->ver < 20 && + dst_type == BRW_REGISTER_TYPE_F && opcode != BRW_OPCODE_MOV, "Mixed float mode with 32-bit float destination is limited " "to SIMD8"); |