From 2cdad60174ce00c3081ab88c54d2b19efda118d0 Mon Sep 17 00:00:00 2001 From: Rohan Garg Date: Tue, 26 Jul 2022 15:01:57 +0200 Subject: intel/eu/validate: Allow SIMD16 for mixed mode float operations on xe2+ Signed-off-by: Rohan Garg Reviewed-by: Jordan Justen --- src/intel/compiler/brw_eu_validate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index 8a8b3d10b75..03a55c83a5b 100644 --- a/src/intel/compiler/brw_eu_validate.c +++ b/src/intel/compiler/brw_eu_validate.c @@ -1137,7 +1137,8 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, * "No SIMD16 in mixed mode when destination is f32. Instruction * execution size must be no more than 8." */ - ERROR_IF(exec_size > 8 && dst_type == BRW_REGISTER_TYPE_F && + ERROR_IF(exec_size > 8 && devinfo->ver < 20 && + dst_type == BRW_REGISTER_TYPE_F && opcode != BRW_OPCODE_MOV, "Mixed float mode with 32-bit float destination is limited " "to SIMD8"); -- cgit v1.2.3