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2016-05-08glext.h: Add missing include of stddef.h for ptrdiff_tHEADmaster-darwin-build-fixesmasterJeremy Huddleston Sequoia1-0/+1
Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com>
2016-05-08applegl: Provide requirements of _SET_DrawBuffersJon TURNEY2-1/+7
_SET_DrawBuffers requires driDispatchRemapTable, so we need to link with libmesa for remap.c. libmesa requires the C++ linker. Also need to arrange to call _mesa_init_remap_table() to initialize the remap table. Signed-off-by: Jon TURNEY <jon.turney@dronecode.org.uk> Reviewed-by: Jeremy Huddleston Sequoia <jeremyhu@freedesktop.org>
2016-05-08mesa: Deal with size differences between GLuint and GLhandleARB in ↵Jeremy Huddleston Sequoia1-1/+25
GetAttachedObjectsARB Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com> CC: Nicolai Hähnle <nhaehnle@gmail.com> CC: Matt Turner <mattst88 at gmail.com> CC: Ian Romanick <idr@freedesktop.org>
2016-05-07spirv: Fix structure splitting with per-vertex interface arrays.Kenneth Graunke1-1/+2
We want to use interface_type, not vtn_var->type. They're normally equivalent, but for geometry/tessellation per-vertex interface arrays, we need to unwrap a level. Otherwise, we tried to iterate a structure members but instead used an array length. If the array length was longer than the number of fields in the structure, we'd crash. Fixes the CreatePipelineGeometryInputBlockPositive layer validation test. v2: Just use glsl_without_array() on the vtn_var type (requested by Jason Ekstrand). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-05-07compiler: Add a C wrapper for glsl_type::without_array().Kenneth Graunke2-0/+7
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-05-07radeonsi: fix undefined behavior (memcpy arguments must be non-NULL)Nicolai Hähnle1-1/+3
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-07radeonsi: fix some reported undefined left-shiftsNicolai Hähnle1-3/+3
One of these is an unsigned bitfield, which I suspect is a false positive, but gcc 5.3.1 complains about it with -fsanitize=undefined. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-07gallium/radeon: clean left-shift undefined behaviorNicolai Hähnle11-3989/+3989
Shifting into the sign bit of a signed int is undefined behavior. Unfortunately, there are potentially many places where this happens using the register macros. This commit is the result of running sed -ie "s/(((\(\w\+\)) & 0x\(\w\+\)) << \(\w\+\))/(((unsigned)(\1) \& 0x\2) << \3)/g" on all header files in gallium/{r600,radeon,radeonsi}. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-07gallium: fix various undefined left shifts into sign bitNicolai Hähnle6-8/+8
Funnily enough, some of these were turned into a compile-time error by gcc with -fsanitize=undefined ("initializer is not a constant"). Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-07compiler/glsl: do not downcast list sentinelNicolai Hähnle1-1/+4
This crashes gcc's undefined behaviour sanitizer. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-07mesa/main: fix another undefined left shiftNicolai Hähnle1-1/+1
Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-07mesa/main: define _NEW_xxx flags as unsigned shiftsNicolai Hähnle1-30/+30
Since 1 << 31 complains about undefined behaviour; the others are changed only for consistency. Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-06radeonsi: Compute correct LDS size for fragment shaders.Bas Nieuwenhuizen1-3/+6
No sure where the 36 came from, but we clearly need at least 48 bytes per attribute per primitive. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-06vc4: Add support for loading immediate values in QIR.Eric Anholt4-0/+32
This will be used for resetting the uniform stream in the presence of branching, but may also be useful as an optimization to reduce how many uniforms we have to copy out per draw call (in exchange for increasing icache pressure).
2016-05-06vc4: Make vc4_qpu_validate() produce more verbose failures.Eric Anholt1-35/+71
Seeing the expansion of a QPU_GET_FIELD in an assert isn't very informative, and it's hard find what's going wrong without getting a dump of the instruction that failed.
2016-05-06vc4: Add a small QIR validate pass.Eric Anholt4-0/+127
This has caught a couple of bugs during loop development so far, and I should probably have written it long ago.
2016-05-06vc4: Fix the src count on exp2/log2.Eric Anholt1-2/+2
Found by the upcoming QIR validate pass.
2016-05-06vc4: Reuse QPU disasm's cond flags in QIR.Eric Anholt3-27/+46
In the process, this made me flatten out the "%s%s%s%s" fprintf arguments.
2016-05-06vc4: When emitting an instruction to an existing temp, mark it non-SSA.Eric Anholt1-0/+2
Prevents a bug in the later control-flow support series.
2016-05-06vc4: Make sure that we don't overwrite the signal for PROG_END.Eric Anholt1-0/+8
We should have already emitted a NOP due to the last instruction being a TLB or VPM write. However, if you disable dead code elimination then you might get dead code at the end, and that dead code might have the signal bits set to something non-default, at which point you die in assertion failure.
2016-05-06nvc0: unreference images when the context is destroyedSamuel Pitoiset1-0/+4
Like other resources, we need to unreference all images. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-05-06nir: Remove spurious return from void function.Jose Fonseca1-2/+0
Left over from 450c0613627d5a472fcf1122c15b66988abfb372. Trivial. Built locally with clang and gcc. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95296
2016-05-06radeonsi: set DECOMPRESS_Z_ON_FLUSH if nr_samples >= 4Marek Olšák1-1/+2
Vulkan always sets this. It only affects in-place Z decompression. This is recommended for performance, but what app uses MSAA depth texturing? Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-05-06r600g: use the hw MSAA resolving if formats are compatibleMarek Olšák1-1/+2
This allows resolving RGBA into RGBX. This should improve HL2 Lost Coast performance. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05Revert "i965: Switch to scalar TCS by default."Kenneth Graunke1-1/+1
This reverts commit b593737ed8349b280fa29242c35f565b59ab3025. Apparently it causes GPU hangs on some image load store tests. Let's turn it back off until we figure out why.
2016-05-05st/omx/enc: fix incorrect reference picture order for B framesLeo Liu1-7/+12
Stacking frames is for driver that's capable to do dual instances encoding. Such feature is not enabled for B frames currently. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-05-05i965/fs: Move handling of samples_identical into the switch statementJason Ekstrand1-21/+19
This is where we handle texop_texture_samples so it makes things more consistent.
2016-05-05i965/fs: Simplify texture destination fixupsJason Ekstrand1-21/+11
There are a few different fixups that we have to do for texture destinations that re-arrange channels, fix hardware vs. API mismatches, or just shrink the result to fit in the NIR destination. These were all being done in a somewhat haphazard manner. This commit replaces all of the shuffling with a single LOAD_PAYLOAD operation at the end and makes it much easier to insert fixups between the texture instruction itself and the LOAD_PAYLOAD. Shader-db results on Haswell: total instructions in shared programs: 6227035 -> 6226669 (-0.01%) instructions in affected programs: 19119 -> 18753 (-1.91%) helped: 85 HURT: 0 total cycles in shared programs: 56491626 -> 56476126 (-0.03%) cycles in affected programs: 672420 -> 656920 (-2.31%) helped: 92 HURT: 42
2016-05-05i965/fs: stop inclinding glsl/ir.h in brw_fs.hJason Ekstrand2-1/+1
We are no longer using anything from GLSL IR in the FS backend.
2016-05-05i965/fs: Merge nir_emit_texture and emit_textureJason Ekstrand3-238/+162
The fs_visitor::emit_texture helper originated when we still had both NIR and IR visitors for the FS backend. Since the old visitor was removed, emit_texture serves no real purpose beyond arbitrarily splitting heavily-linked code across two functions.
2016-05-05nir: remove now-unused nir_foreach_block*_call()Connor Abbott1-38/+0
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-05vc4: fixup for new nir_foreach_block()Connor Abbott4-48/+20
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-05-05ir3: fixup for new nir_foreach_block()Connor Abbott1-30/+21
2016-05-05nir/lower_double_ops: fixup for new nir_foreach_block()Jason Ekstrand1-23/+9
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-05nir/lower_double_pack: fixup for new nir_foreach_block()Jason Ekstrand1-26/+21
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-05nir/gather_info: fixup for new foreach_block()Jason Ekstrand1-5/+5
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-05nir/lower_two_sided_color: fixup for new foreach_block()Connor Abbott1-3/+5
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-05nir/lower_tex: fixup for new foreach_block()Connor Abbott1-25/+22
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-05nir/lower_outputs_to_temporaries: fixup for new foreach_block()Connor Abbott1-16/+12
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-05i965: Switch to scalar TCS by default.Kenneth Graunke1-1/+1
Normally, we expect SIMD8 shaders to be more instructions than SIMD4x2 shaders, as it takes four instructions to operate on a vec4, rather than a single instruction. However, the benefit is that it can process 8 objects per shader thread instead of 2. Surprisingly, the shader-db statistics show an improvement in both instruction and cycle counts: Synmark: -31.25% instructions, -29.27% cycles, 0 hurt. Tessmark: -36.92% instructions, -37.81% cycles, 0 hurt. Unigine Heaven: -3.42% instructions, -17.95% cycles, 0 hurt. Shadow of Mordor: +13.24% instructions (26 with fewer instructions, 45 with more), -5.23% cycles (44 with fewer cycles, 27 with more cycles). Presumably, this is because the SIMD8 URB messages are a much more natural fit than the SIMD4x2 URB messages - there's a ton less header setup. I benchmarked Shadow of Mordor and Unigine Heaven on my Skylake GT3e, and the performance seems to be the same or increase ever so slightly (< 1 FPS difference). So I believe it's strictly superior. There's also a lot more optimization potential we can do in scalar mode. This will also help us finish fp64 support, as scalar support is going to land much sooner than vec4-mode support. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-05nir: Optimize out stores of undefs.Kenneth Graunke1-0/+30
There are a couple of cycle count changes in shader-db, but it's basically a wash. However, with the Broadwell scalar TCS backend enabled, many Shadow of Mordor shaders benefit from this patch. Because we don't batch up output writes for TCS, vec4 outputs might not have all components defined. Many output writes have a value of undef, which is useless. With scalar TCS, stats for tessellation shaders on Broadwell: total instructions in shared programs: 1283000 -> 1280444 (-0.20%) instructions in affected programs: 34302 -> 31746 (-7.45%) helped: 71 HURT: 0 total cycles in shared programs: 10798768 -> 10780682 (-0.17%) cycles in affected programs: 158004 -> 139918 (-11.45%) helped: 71 HURT: 0 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-05nir: Replace vecN(undef, undef, ...) with a single undef.Kenneth Graunke1-0/+33
shader-db statistics on Broadwell: total instructions in shared programs: 8963409 -> 8962455 (-0.01%) instructions in affected programs: 60858 -> 59904 (-1.57%) helped: 318 HURT: 0 total cycles in shared programs: 71408022 -> 71406276 (-0.00%) cycles in affected programs: 398416 -> 396670 (-0.44%) helped: 199 HURT: 51 GAINED: 1 The only shaders affected were in Dota 2 Reborn. It also sets up for the next optimization. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-05nir: Rename opt_undef_alu to opt_undef_csel; update comments.Kenneth Graunke1-12/+13
This better reflects what it does. I plan to add other ALU optimizations as well, so the old name would be confusing. In preparation for that, also move the file comments about csels above the opt_undef_csel function, and delete the ones about there not being other optimizations. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-05i965: Rework passthrough TCS checks.Kenneth Graunke4-2/+5
According to Timothy, using program_string_id == 0 to identify the passthrough TCS is going to be problematic for his shader cache work. So, change it to strcmp() the name at visitor creation time. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-05swr: [rasterizer core] Faster modulo operator in ProcessVertsTim Rowley1-1/+4
Avoid % operator, since we know that curVertex is always incrementing. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-05-05swr: [rasterizer] Small warning cleanupTim Rowley2-8/+4
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-05-05swr: [rasterizer] Add SWR_ASSUME / SWR_ASSUME_ASSERT macrosTim Rowley2-14/+52
Fix static code analysis errors found by coverity on Linux Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-05-05swr: [rasterizer] Miscellaneous backend changesTim Rowley3-22/+31
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-05-05swr: [rasterizer] Add support for X24_TYPELESS_G8_UINT formatTim Rowley3-7/+41
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-05-05swr: [rasterizer jitter] Fix printing bugs for tracing.Tim Rowley1-81/+24
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
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