NV4x -> G7x, MCPxx, NV44A.

8 files changed, 79 insertions, 79 deletions

diff --git a/docs/glossary.txt b/docs/glossary.txt
index 7a3fb98d..585091cc 100644
--- a/docs/glossary.txt
+++ b/docs/glossary.txt
@@ -60,8 +60,8 @@ graph object - an engine object bound to PGRAPH.
 I
 
 IGP: integrated graphics processor, a GPU integrated into the northbridge,
-lacking dedicated VRAM. Nvidia IGPs include: NV0A, NV1A, NV1F, NV2A, NV4C,
-NV4E, NV67, NV68, NV63, MCP77, MCP79, MCP89.
+lacking dedicated VRAM. Nvidia IGPs include: NV0A, NV1A, NV1F, NV2A, C51,
+MCP61, MCP67, MCP68, MCP73, MCP77, MCP79, MCP89.
 
 
 P
diff --git a/docs/hw/bus/pci.rst b/docs/hw/bus/pci.rst
index 8f96cadb..6b60c9a9 100644
--- a/docs/hw/bus/pci.rst
+++ b/docs/hw/bus/pci.rst
@@ -80,9 +80,9 @@ On NV1:G80 cards, PCI config space, or first 0x100 bytes of PCIE config
 space, are also mapped to MMIO register space at addresses 0x1800-0x18ff.
 On NV40+ cards, all 0x1000 bytes of PCIE config space are mapped to MMIO
 register space at addresses 0x88000-0x88fff. It's a bad idea to access config
-space addresses >= 0x100 on NV40/NV45/NV4A.
+space addresses >= 0x100 on NV40/NV45/NV44A.
 
-All NV1:NV40 cards, as well as NV40, NV45, NV4A are natively PCI/AGP devices,
+All NV1:NV40 cards, as well as NV40, NV45, NV44A are natively PCI/AGP devices,
 all other cards are natively PCIE devices. Pre-NV40 IGPs are connected through
 an internal AGP bus and are considered AGP devices, while NV40+ IGPs are
 connected by northbridge-internal interfaces and are *not* considered PCIE
diff --git a/docs/hw/bus/pmc.rst b/docs/hw/bus/pmc.rst
index bd39619d..27ca2e5a 100644
--- a/docs/hw/bus/pmc.rst
+++ b/docs/hw/bus/pmc.rst
@@ -202,7 +202,7 @@ On NV4:G80, the bits are:
 - 26: :ref:`PTV <ptv>` [NV17:NV20, NV25:G80]
 - 28: :ref:`PRAMDAC.VIDEO <pvideo>` [NV4:NV10] or :ref:`PVIDEO <pvideo>` [NV10:G80]
 
-.. todo:: figure out the CS thing, figure out the variants. Known not to exist on NV40, NV43, NV44, NV4E, NV49; known to exist on NV63
+.. todo:: figure out the CS thing, figure out the variants. Known not to exist on NV40, NV43, NV44, C51, G71; known to exist on MCP73
 
 On G80:GF100, the bits are:
 
diff --git a/docs/hw/gpu.rst b/docs/hw/gpu.rst
index ddd9c49f..fe92fcd4 100644
--- a/docs/hw/gpu.rst
+++ b/docs/hw/gpu.rst
@@ -83,9 +83,9 @@ is:
 - Rankine family: NV30, NV35, NV31, NV36, NV34
 - Curie family:
 
-  - NV40 subfamily: NV40, NV45, NV41, NV42, NV43, NV44, NV4A
-  - NV47 subfamily: NV47, NV49, NV4B, NV46
-  - the IGPs: NV4E, NV4C, NV67, NV68, NV63
+  - NV40 subfamily: NV40, NV45, NV41, NV42, NV43, NV44, NV44A
+  - G70 subfamily: G70, G71, G73, G72
+  - the IGPs: C51, MCP61, MCP67, MCP68, MCP73
 
 - Tesla family:
 
@@ -445,7 +445,7 @@ family where GPU ids started to diverge from nvidia code names. The changes:
   - a new PCIE GART page table format
   - 3d engine: ???
 
-- NV4A:
+- NV44A:
 
   - like NV44, but AGP instead of PCIE
 
@@ -458,21 +458,21 @@ The GPUs are [vertex shaders : pixel shaders : ROPs]:
 pciid     GPU id    GPU names      vertex  pixel   ROPs date       notes
                                    shaders shaders
 ========= ========= ============== ======= ======= ==== ========== =====
-004X 021X NV40/NV45 NV40/NV45/NV48 6       16      16   14.04.2004 AGP
-00cX      NV41/NV42 NV41/NV42      5       12      12   08.11.2004
-014X      NV43      NV43           3       8       4    12.08.2004
-016X      NV44      NV44           3       4       2    15.12.2004 TURBOCACHE
-022X      NV4A      NV44A          3       4       2    04.04.2005 AGP
-009X      NV47      G70            8       24      16   22.06.2005
-01dX      NV46      G72            3       4       2    18.01.2006 TURBOCACHE
-029X      NV49      G71            8       24      16   09.03.2006
-039X      NV4B      G73            8       12      8    09.03.2006
-024X      NV4E      C51            1       2       1    20.10.2005 IGP, TURBOCACHE
-03dX      NV4C      MCP61          1       2       1    ??.06.2006 IGP, TURBOCACHE
-053X      NV67      MCP67          1       2       2    01.02.2006 IGP, TURBOCACHE
-053X      NV68      MCP68          1       2       2    ??.07.2007 IGP, TURBOCACHE
-07eX      NV63      MCP73          1       2       2    ??.07.2007 IGP, TURBOCACHE
-\-        NV??      RSX            ?       ?       ?    11.11.2006 FlexIO bus interface, used in PS3
+004X 021X 0x40/0x45 NV40/NV45/NV48 6       16      16   14.04.2004 AGP
+00cX      0x41/0x42 NV41/NV42      5       12      12   08.11.2004
+014X      0x43      NV43           3       8       4    12.08.2004
+016X      0x44      NV44           3       4       2    15.12.2004 TURBOCACHE
+022X      0x4a      NV44A          3       4       2    04.04.2005 AGP
+009X      0x47      G70            8       24      16   22.06.2005
+01dX      0x46      G72            3       4       2    18.01.2006 TURBOCACHE
+029X      0x49      G71            8       24      16   09.03.2006
+039X      0x4b      G73            8       12      8    09.03.2006
+024X      0x4e      C51            1       2       1    20.10.2005 IGP, TURBOCACHE
+03dX      0x4c      MCP61          1       2       1    ??.06.2006 IGP, TURBOCACHE
+053X      0x67      MCP67          1       2       2    01.02.2006 IGP, TURBOCACHE
+053X      0x68      MCP68          1       2       2    ??.07.2007 IGP, TURBOCACHE
+07eX      0x63      MCP73          1       2       2    ??.07.2007 IGP, TURBOCACHE
+\-        ???       RSX            ?       ?       ?    11.11.2006 FlexIO bus interface, used in PS3
 ========= ========= ============== ======= ======= ==== ========== =====
 
 .. todo:: all geometry information unverified
@@ -480,7 +480,7 @@ pciid     GPU id    GPU names      vertex  pixel   ROPs date       notes
 .. todo:: any information on the RSX?
 
 It's not clear how NV40 is different from NV45, or NV41 from NV42,
-or NV67 from NV68 - they even share pciid ranges.
+or MCP67 from MCP68 - they even share pciid ranges.
 
 The NV4x IGPs actually have a memory controller as opposed to earlier ones.
 This controller still accesses only host memory, though.
diff --git a/docs/hw/mmio.rst b/docs/hw/mmio.rst
index b3ae4ffe..1bd11ce4 100644
--- a/docs/hw/mmio.rst
+++ b/docs/hw/mmio.rst
@@ -98,7 +98,7 @@ NV3:G80 MMIO map
    0x100000 PFB nv40-pfb NV40:G80&!TC
    0x100000 PFB nv44-pfb NV44:G80&TC
    0x101000 PSTRAPS nv3-pstraps !NV1A
-   0x102000 UNK102000 nv4e-unk102000 NV63
+   0x102000 UNK102000 c51-unk102000 MCP73
    0x110000 PROM nv3-prom NV3:NV4
    0x120000 PALT nv3-palt NV3:NV4
    0x200000 PMEDIA pmedia !IGP4X
@@ -125,20 +125,20 @@ NV3:G80 MMIO map
    0x0800000[chid:0x20][subc:8] USER nv4-user NV10:G80
    0x0c00000[chid:0x200] DMA_USER nv40-dma-user NV40:G80
 
-   .. todo:: check UNK005000 variants [sorta present on NV35, NV34, NV4E, NV63; present on NV5, NV11, NV17, NV1A, NV20; not present on NV44]
+   .. todo:: check UNK005000 variants [sorta present on NV35, NV34, C51, MCP73; present on NV5, NV11, NV17, NV1A, NV20; not present on NV44]
    .. todo:: check PCOUNTER variants
-   .. todo:: some IGP don't have PVPE/PVP1 [NV4E: present, but without PME; NV63: not present at all]
+   .. todo:: some IGP don't have PVPE/PVP1 [C51: present, but without PME; MCP73: not present at all]
    .. todo:: check PSTRAPS on IGPs
    .. todo:: check PROM on IGPs
-   .. todo:: PMEDIA not on IGPs [NV63 and NV4E: not present] and some other cards?
+   .. todo:: PMEDIA not on IGPs [MCP73 and C51: not present] and some other cards?
    .. todo:: PFB not on IGPs
    .. todo:: merge PCRTC+PRMCIO/PRAMDAC+PRMDIO?
    .. todo:: UNK6E0000 variants
    .. todo:: UNK006000 variants
    .. todo:: UNK00E000 variants
-   .. todo:: 102000 variants; present on NV63, not NV4E
+   .. todo:: 102000 variants; present on MCP73, not C51
 
-   .. note:: fully verified on NV3, NV5, NV11, NV17, NV34, NV35, NV44, NV4E, NV63
+   .. note:: fully verified on NV3, NV5, NV11, NV17, NV34, NV35, NV44, C51, MCP73
    
    .. note::
    
@@ -332,7 +332,7 @@ Unknown ranges
 
    .. todo:: RE me
 
-.. space:: 8 nv4e-unk102000 0x1000 ???
+.. space:: 8 c51-unk102000 0x1000 ???
 
    .. todo:: RE me
 
diff --git a/docs/hw/pciid.rst b/docs/hw/pciid.rst
index 16f43e4c..cdcdd950 100644
--- a/docs/hw/pciid.rst
+++ b/docs/hw/pciid.rst
@@ -529,8 +529,8 @@ device id  product
 
 .. _pci-ids-nv44a:
 
-NV44A [NV4A]
-------------
+NV44A
+-----
 
 ========== ========================================================
 device id  product
@@ -542,8 +542,8 @@ device id  product
 
 .. _pci-ids-c51-gpu:
 
-C51 GPU [NV4E]
---------------
+C51 GPU
+-------
 
 ========== ========================================================
 device id  product
@@ -559,8 +559,8 @@ device id  product
 
 .. _pci-ids-g70:
 
-G70 [NV47]
-----------
+G70
+---
 
 ========== ========================================================
 device id  product
@@ -578,8 +578,8 @@ device id  product
 
 .. _pci-ids-g72:
 
-G72 [NV46]
-----------
+G72
+---
 
 ========== ========================================================
 device id  product
@@ -603,8 +603,8 @@ device id  product
 
 .. _pci-ids-g71:
 
-G71 [NV49]
-----------
+G71
+---
 
 ========== ========================================================
 device id  product
@@ -629,8 +629,8 @@ device id  product
 
 .. _pci-ids-g73:
 
-G73 [NV4B]
-----------
+G73
+---
 
 ========== ========================================================
 device id  product
@@ -653,8 +653,8 @@ device id  product
 
 .. _pci-ids-mcp61-gpu:
 
-MCP61 GPU [NV4C]
-----------------
+MCP61 GPU
+---------
 
 ========== ========================================================
 device id  product
@@ -669,8 +669,8 @@ device id  product
 
 .. _pci-ids-mcp67-gpu:
 
-MCP67 GPU [NV67/NV68]
----------------------
+MCP67 GPU
+---------
 
 ========== ========================================================
 device id  product
@@ -687,8 +687,8 @@ device id  product
 
 .. _pci-ids-mcp73-gpu:
 
-MCP73 GPU [NV63]
-----------------
+MCP73 GPU
+---------
 
 ========== ========================================================
 device id  product
diff --git a/docs/hw/pcounter/intro.rst b/docs/hw/pcounter/intro.rst
index 2c301c65..0f0b3eaf 100644
--- a/docs/hw/pcounter/intro.rst
+++ b/docs/hw/pcounter/intro.rst
@@ -188,9 +188,9 @@ NV40
     00a7e0+i*4 QUAD_ACK_TRIGGER - used to ack counter data in quad event mode
     00a800+i*0x20+j*4,j<8 STATUS[i][j] - input status
 
-.. todo:: NV4E has no PCOUNTER, but has a7f4/a7f8 registers
+.. todo:: C51 has no PCOUNTER, but has a7f4/a7f8 registers
 
-.. todo:: NV63 also has a7f4/a7f8 but also has normal PCOUNTER
+.. todo:: MCP73 also has a7f4/a7f8 but also has normal PCOUNTER
 
 
 GF100
diff --git a/docs/hw/pm/nv43-therm.rst b/docs/hw/pm/nv43-therm.rst
index ee51ffd7..0fe2a1a5 100644
--- a/docs/hw/pm/nv43-therm.rst
+++ b/docs/hw/pm/nv43-therm.rst
@@ -19,8 +19,8 @@ temperature range. This range has been replaced by PTHERM on G80+ GPUs.
 
 THERM's MMIO range is 0x15b0:0x15c0. There are two major variants of this range:
 
-- NV43:NV47
-- NV47:G80
+- NV43:G70
+- G70:G80
 
 
 .. _nv43-therm-mmio:
@@ -37,41 +37,41 @@ Address  Present on  Name       Description
 0x0015bc all         TEMP_RANGE LOW and HIGH temperature thresholds
 ======== =========== ========== ============
 
-MMIO 0x15b0: CFG0 [NV43:NV47]
+MMIO 0x15b0: CFG0 [NV43:G70]
   - bits 0-7: ALARM_HIGH
   - bits 16-23: SENSOR_OFFSET (signed integer)
   - bit 24: DISABLE
   - bit 28: ALARM_INTR_EN
 
-MMIO 0x15b0: CFG0 [NV47:G80]
+MMIO 0x15b0: CFG0 [G70:G80]
   - bits 0-13: ALARM_HIGH
   - bits 16-29: SENSOR_OFFSET (signed integer)
   - bit 30: DISABLE
   - bit 31: ENABLE
 
-MMIO 0x15b4: STATUS [NV43:NV47]
+MMIO 0x15b4: STATUS [NV43:G70]
   - bits 0-7: SENSOR_RAW
   - bit 8: ALARM_HIGH
   - bits 25-31: ADC_CLOCK_XXX
 
 .. todo:: figure out what divisors are available
 
-MMIO 0x15b4: STATUS [NV47:G80]
+MMIO 0x15b4: STATUS [G70:G80]
   - bits 0-13: SENSOR_RAW
   - bit 16: ALARM_HIGH
   - bits 26-31: ADC_CLOCK_DIV
     The division is stored right-shifted 4. The possible division values range
     from 32 to 2016 with the possibility to completely bypass the divider.
 
-MMIO 0x15b8: CFG1 [NV43:NV47]
+MMIO 0x15b8: CFG1 [NV43:G70]
   - bit 17: ADC_PAUSE
   - bit 23: CONNECT_SENSOR
 
-MMIO 0x15bc: TEMP_RANGE [NV43:NV47]
+MMIO 0x15bc: TEMP_RANGE [NV43:G70]
   - bits 0-7: LOW
   - bits 8-15: HIGH
 
-MMIO 0x15bc: TEMP_RANGE [NV47:G80]
+MMIO 0x15bc: TEMP_RANGE [G70:G80]
   - bits 0-13: LOW
   - bits 16-29: HIGH
 
@@ -81,20 +81,20 @@ The ADC clock
 
 The source clock for THERM's ADC is:
 
-- NV43:NV47: the host clock
-- NV47:G80: constant (most likely hclck)
+- NV43:G70: the host clock
+- G70:G80: constant (most likely hclck)
 
 (most likely, since the rate doesn't change when I change the HOST clock)
 
 Before reaching the ADC, the clock source is divided by a fixed divider of 1024
 and then by ADC_CLOCK_DIV.
 
-MMIO 0x15b4: STATUS [NV43:NV47]
+MMIO 0x15b4: STATUS [NV43:G70]
   - bits 25-31: ADC_CLOCK_DIV
 
 .. todo:: figure out what divisors are available
 
-MMIO 0x15b4: STATUS [NV47:G80]
+MMIO 0x15b4: STATUS [G70:G80]
   - bits 26-31: ADC_CLOCK_DIV
     The division is stored right-shifted 4. The possible division values range
     from 32 to 2016 with the possibility to completely bypass the divider.
@@ -106,7 +106,7 @@ ADC_clock = source_clock / ADC_CLOCK_DIV
 The accuracy of the reading greatly depends on the ADC clock. A clock too fast
 will produce a lot of noise. A clock too low may actually produce an offseted
 value. The ADC clock rate under 10 kHz is advised, based on limited testing
-on a nv4b.
+on a G73.
 
 .. todo:: Make sure this clock range is safe on all cards
 
@@ -119,31 +119,31 @@ Reading temperature
 
 Temperature is read from:
 
-MMIO 0x15b4: STATUS [NV43:NV47]
+MMIO 0x15b4: STATUS [NV43:G70]
   bits 0-7: SENSOR_RAW
-MMIO 0x15b4: STATUS [NV47:G80]
+MMIO 0x15b4: STATUS [G70:G80]
   bits 0-13: SENSOR_RAW
 
 SENSOR_RAW is the result of the (signed) addition of the actual value read by
 the ADC and SENSOR_OFFSET:
 
-MMIO 0x15b0: CFG0 [NV43:NV47]
+MMIO 0x15b0: CFG0 [NV43:G70]
   - bits 16-23: SENSOR_OFFSET signed
 
-MMIO 0x15b0: CFG0 [NV47:G80]
+MMIO 0x15b0: CFG0 [G70:G80]
   - bits 16-29: SENSOR_OFFSET signed
 
 Starting temperature readouts requires to flip a few switches that are
 GPU-dependent:
 
-MMIO 0x15b0: CFG0 [NV43:NV47]
+MMIO 0x15b0: CFG0 [NV43:G70]
   - bit 24: DISABLE
 
-MMIO 0x15b0: CFG0 [NV47:G80]
+MMIO 0x15b0: CFG0 [G70:G80]
   - bit 30: DISABLE - mutually exclusive with ENABLE
   - bit 31: ENABLE - mutually exclusive with DISABLE
 
-MMIO 0x15b8: CFG1 [NV43:NV47]
+MMIO 0x15b8: CFG1 [NV43:G70]
   - bit 17: ADC_PAUSE
   - bit 23: CONNECT_SENSOR
 
@@ -167,19 +167,19 @@ to be set in order to get the IRQ. You may need to set bits 0x40001 in 0x15a0
 and 1 in 0x15a4. Their purpose has not been understood yet even though they
 may be releated to automatic downclocking.
 
-MMIO 0x15b0: CFG0 [NV43:NV47]
+MMIO 0x15b0: CFG0 [NV43:G70]
   - bits 0-7: ALARM_HIGH
   - bit 28: ALARM_INTR_EN
 
-MMIO 0x15b0: CFG0 [NV47:G80]
+MMIO 0x15b0: CFG0 [G70:G80]
   - bits 0-13: ALARM_HIGH
 
 When SENSOR_RAW > ALARM_HIGH, STATUS.ALARM_HIGH is set.
 
-MMIO 0x15b4: STATUS [NV43:NV47]
+MMIO 0x15b4: STATUS [NV43:G70]
   - bit 8: ALARM_HIGH
 
-MMIO 0x15b4: STATUS [NV47:G80]
+MMIO 0x15b4: STATUS [G70:G80]
   - bit 16: ALARM_HIGH
 
 STATUS.ALARM_HIGH is unset as soon as SENSOR_RAW < ALARM_HIGH, without any
@@ -195,11 +195,11 @@ THERM can check that temperature is inside a range. When the temperature goes
 outside this range, an interrupt is sent. The range is defined in the register
 TEMP_RANGE where the thresholds LOW and HIGH are set.
 
-MMIO 0x15bc: TEMP_RANGE [NV43:NV47]
+MMIO 0x15bc: TEMP_RANGE [NV43:G70]
   - bits 0-7: LOW
   - bits 8-15: HIGH
 
-MMIO 0x15bc: TEMP_RANGE [NV47:G80]
+MMIO 0x15bc: TEMP_RANGE [G70:G80]
   - bits 0-13: LOW
   - bits 16-29: HIGH