diff options
| author | Marcin Kościelnicki <koriakin@0x04.net> | 2014-09-11 01:44:33 +0200 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2014-09-11 02:17:34 +0200 |
| commit | 0c9ea6be9b6c2a00e0188e3eb914ab22591307a5 (patch) | |
| tree | 9a97e70c9ef308c945942525d8a2b73ec4cc3f40 /docs | |
| parent | d084be1adcf7c3a79105343ae6ab92b06f3b1cd5 (diff) | |
NV50 -> G80
Diffstat (limited to 'docs')
84 files changed, 779 insertions, 779 deletions
diff --git a/docs/envydis/index.rst b/docs/envydis/index.rst index 4ebfdc65..9aee9b65 100644 --- a/docs/envydis/index.rst +++ b/docs/envydis/index.rst @@ -50,10 +50,10 @@ Variant selection Select the ISA to disassemble. One of: - - [****] nv50: nv50 [tesla] CUDA/shader ISA + - [****] g80: g80 [tesla] CUDA/shader ISA - [*** ] gf100: gf100 [fermi] CUDA/shader ISA - [** ] gk110: nv?? (tbd) [kepler GK110] CUDA/shader ISA - - [** ] ctx: nv40 and nv50 PGRAPH context-switching microcode + - [** ] ctx: nv40 and g80 PGRAPH context-switching microcode - [*** ] falcon: falcon microcode, used to power various engines on G98+ cards - [****] hwsq: PBUS hardware sequencer microcode - [****] xtensa: xtensa variant as used by video processor 2 [g84-gen] @@ -74,9 +74,9 @@ Variant selection Select variant of the ISA. - For nv50: + For g80: - - nv50: The original NV50 [aka compute capability 1.0] + - g80: The original G80 [aka compute capability 1.0] - g84: G84, G86, G92, G94, G96, G98 [aka compute capability 1.1] - g200: G200 [aka compute capability 1.3] - mcp77: MCP77, MCP79 [aka compute capability 1.2] @@ -89,15 +89,15 @@ Variant selection For ctx: - - nv40: NV40:NV50 cards - - nv50: NV50:G200 cards + - nv40: NV40:G80 cards + - g80: G80:G200 cards - g200: G200:GF100 cards For hwsq: - nv17: NV17:NV41 cards - - nv41: NV41:NV50 cards - - nv50: NV50:GF100 cards + - nv41: NV41:G80 cards + - g80: G80:GF100 cards For falcon: @@ -118,7 +118,7 @@ Variant selection but can also be specified manually. Can be used multiple times to enable several features. - For nv50: + For g80: - sm11: SM1.1 new opcodes [selected by g84, g200, mcp77, gt215] - sm12: SM1.2 new opcodes [selected by g200, mcp77, gt215] @@ -132,15 +132,15 @@ Variant selection For ctx: - - nv40op: NV40:NV50 exclusive opcodes [selected by nv40] - - nv50op: NV50:GF100 exclusive opcodes [selected by nv50, g200] + - nv40op: NV40:G80 exclusive opcodes [selected by nv40] + - g80op: G80:GF100 exclusive opcodes [selected by g80, g200] - callret: call/ret opcodes [selected by g200] For hwsq: - - nv17f: NV17:NV50 flags [selected by nv17, nv41] - - nv41f: NV41:NV50 flags [selected by nv41] - - nv41op: NV41 new opcodes [selected by nv41, nv50] + - nv17f: NV17:G80 flags [selected by nv17, nv41] + - nv41f: NV41:G80 flags [selected by nv41] + - nv41op: NV41 new opcodes [selected by nv41, g80] For falcon: @@ -159,7 +159,7 @@ Variant selection Select processor mode. - For nv50: + For g80: - vp: Vertex program - gp: Geometry program diff --git a/docs/glossary.txt b/docs/glossary.txt index d8b76795..7a3fb98d 100644 --- a/docs/glossary.txt +++ b/docs/glossary.txt @@ -25,7 +25,7 @@ D DMA object: a FIFO object represeting an area of memory, used on NV01:GF100. Can be used to represent both contiguous and paged areas of memory. [memory/nv01-pdma.txt, memory/nv03-dmaobj.txt, memory/nv04-dmaobj.txt, -memory/nv50-vm.txt] +memory/g80-vm.txt] E @@ -74,23 +74,23 @@ PVP2, PBSP, PCRYPT2, PVLD, PVDEC, PPPP, PCRYPT3, PVCOMP, PCOPY, PVENC. R -RAMFC: an area of RAMIN [NV01:NV50] or channel structure [NV50+] used to store +RAMFC: an area of RAMIN [NV01:G80] or channel structure [G80+] used to store PFIFO context for inactive channels. -RAMHT: an area or RAMIN [NV01:NV50], channel structure [NV50+ PFIFO] or -display structure [NV50+ PDISPLAY] used to store associations between FIFO -object handles and object addresses. On NV01:NV50, there's only one RAMHT -covering all channels. On NV50+, each FIFO channel has its own RAMHT. The +RAMHT: an area or RAMIN [NV01:G80], channel structure [G80+ PFIFO] or +display structure [G80+ PDISPLAY] used to store associations between FIFO +object handles and object addresses. On NV01:G80, there's only one RAMHT +covering all channels. On G80+, each FIFO channel has its own RAMHT. The display channels also have a single RAMHT covering them all. However, when a RAMHT covers multiple channels, each entry is tagged with the channel id, thus the actual bindings are always per-channel. -RAMIN: instance memory - on NV01:NV50 cards, a special area at the end of +RAMIN: instance memory - on NV01:G80 cards, a special area at the end of VRAM, used to store a shadow copy of the VBIOS [NV04+ only], RAMFC, RAMHT, RAMRO, FIFO objects, and engine context [NV20+]. Replaced by the channel -structure on NV50+. +structure on G80+. -RAMRO: runout memory - on NV01:NV50 cards, an area of RAMIN used to store +RAMRO: runout memory - on NV01:G80 cards, an area of RAMIN used to store PIO FIFO command submissions that were rejected for some reason, for later processing by host interrupt handler. @@ -113,7 +113,7 @@ bound and unbound to subchannels through the command stream. surface: a 2d or 3d array of samples, elements, or bytes, depending on the viewpoint - depending on how it's used, it can be a render target, a texture, -a framebuffer, etc. [memory/nv50-surface.txt] +a framebuffer, etc. [memory/g80-surface.txt] surface element: see element @@ -129,7 +129,7 @@ YUV surface, compressed texture surface, or a bitmap surface T texture: a surface bound to the texturing units for sampling. This includes -the 2d source surface on nv50+ cards. +the 2d source surface on g80+ cards. V @@ -143,4 +143,4 @@ Z zeta surface: a surface containing the depth buffer, optionally the stencil buffer, and the special coverage component if coverage sampling is in use -[see memory/nv50-surface.txt] +[see memory/g80-surface.txt] diff --git a/docs/hw/bus/bars.rst b/docs/hw/bus/bars.rst index ad22701a..ecb38a44 100644 --- a/docs/hw/bus/bars.rst +++ b/docs/hw/bus/bars.rst @@ -20,7 +20,7 @@ The nvidia GPUs expose the following areas to the outside world through PCI: - ???: BAR2 [only NV1x IGPs?] - ???: BAR2 [only NV20?] - RAMIN aperture: BAR2 or BAR3 - memory, 0x1000000 bytes or more depending on card type [NV40+] -- indirect memory access IO ports: BAR5 - 0x80 bytes of IO port space [NV50+] +- indirect memory access IO ports: BAR5 - 0x80 bytes of IO port space [G80+] - PCI ROM aperture - PCI INTA interrupt line - legacy VGA IO ports: 0x3b0-0x3bb and 0x3c0-0x3df [can be disabled in PCI config] @@ -76,11 +76,11 @@ This is an area of prefetchable memory that maps to the card's VRAM. On native PCIE cards, it uses 64-bit addressing, on native PCI/AGP ones it uses 32-bit addressing. -On non-TURBOCACHE pre-NV50 cards and on NV50+ cards with BAR1 VM disabled, BAR +On non-TURBOCACHE pre-G80 cards and on G80+ cards with BAR1 VM disabled, BAR addresses map directly to VRAM addresses. On TURBOCACHE cards, BAR1 is made of controllable VRAM and GART windows [see :ref:`nv44-host-mem`]. -NV50+ cards have a mode where all BAR references go through the card's VM -subsystem, see :ref:`nv50-host-mem` and :ref:`gf100-host-mem`. +G80+ cards have a mode where all BAR references go through the card's VM +subsystem, see :ref:`g80-host-mem` and :ref:`gf100-host-mem`. On NV3 cards, this BAR also contains RAMIN access aperture at address 0xc00000 [see :ref:`nv3-vram`] @@ -93,8 +93,8 @@ the BAR size depends on card type: - NV4: 16MB - NV5: 32MB - NV10:NV17: 128MB -- NV17:NV50: 64MB-512MB, set via :ref:`straps <pstraps>` -- NV50-: 64MB-64GB, set via straps +- NV17:G80: 64MB-512MB, set via :ref:`straps <pstraps>` +- G80-: 64MB-64GB, set via straps Note that BAR size is independent from actual VRAM size, although on pre-NV30 cards the BAR is guaranteed not to be smaller than VRAM. This means it may @@ -104,14 +104,14 @@ be impossible to map all of the card's memory through the BAR on NV30+ cards. BAR2/BAR3: RAMIN aperture ========================= -RAMIN is, on pre-NV50 cards, a special area at the end of VRAM that contains +RAMIN is, on pre-G80 cards, a special area at the end of VRAM that contains various control structures. RAMIN starts from end of VRAM and the addresses go in reverse direction, thus it needs a special mapping to access it the way it'll be used. While pre-NV40 cards limitted its size to 1MB and could fit the mapping in BAR0, or BAR1 for NV3, NV40+ allow much bigger RAMIN addresses. RAMIN BAR provides such RAMIN mapping on NV40 family cards. -NV50 did away with a special RAMIN area, but it kept the BAR around. It works +G80 did away with a special RAMIN area, but it kept the BAR around. It works like BAR1, but is independent on it and can use a distinct VM DMA object. As opposed to BAR1, all accesses done to BAR3 will be automatically byte-swapped in 32-bit chunks like BAR0 if the big-endian switch is on. It's commonly @@ -133,11 +133,11 @@ that cannot map high memory addresses. Present only on NV3. .. todo:: RE it. or not. -BAR5: NV50 indirect memory access +BAR5: G80 indirect memory access ================================= An area of IO ports used to access BAR0, BAR1, and BAR3 indirectly by real -mode code that cannot map high memory addresses. Present on NV50+ cards. +mode code that cannot map high memory addresses. Present on G80+ cards. On earlier cards, the indirect access feature of VGA IO ports can be used instead. This BAR can also be disabled via :ref:`straps <pstraps>`. @@ -183,18 +183,18 @@ BAR6: PCI ROM aperture .. todo:: figure out size .. todo:: figure out NV3 -.. todo:: verify NV50 +.. todo:: verify G80 The nvidia GPUs expose their BIOS as standard PCI ROM. The exposed ROM aliases either the actual BIOS EEPROM, or the shadow BIOS in VRAM. This setting is exposed in PCI config space. If the "shadow enabled" PCI config register is 0, the PROM MMIO area is enabled, and both PROM and the PCI ROM aperture will access the EEPROM. Disabling the shadowing has a side effect of disabling -video output on pre-NV50 cards. If shadow is enabled, EEPROM is disabled, +video output on pre-G80 cards. If shadow is enabled, EEPROM is disabled, PROM reads will return garbage, and PCI ROM aperture will access the VRAM -shadow copy of BIOS. On pre-NV50 cards, the shadow BIOS is located at address -0 of RAMIN, on NV50+ cards the shadow bios is pointed to by -PDISPLAY.VGA.ROM_WINDOW register - see :ref:`nv50-vga` for details. +shadow copy of BIOS. On pre-G80 cards, the shadow BIOS is located at address +0 of RAMIN, on G80+ cards the shadow bios is pointed to by +PDISPLAY.VGA.ROM_WINDOW register - see :ref:`g80-vga` for details. INTA: the card interrupt diff --git a/docs/hw/bus/hwsq.rst b/docs/hw/bus/hwsq.rst index bcc8f19d..a589a2f0 100644 --- a/docs/hw/bus/hwsq.rst +++ b/docs/hw/bus/hwsq.rst @@ -29,8 +29,8 @@ MMIO registers no annotation - NV17:GF100 [1] NV17:NV41 -[2] NV41:NV50 -[3] NV50:GF100 +[2] NV41:G80 +[3] G80:GF100 [4] G92:GF100 ============== ==================== ========== @@ -45,9 +45,9 @@ Address Variants Name 001314 NV17:NV20 NV25:GF100 FLAGS_1 001318 G92:GF100 ENTRY_POINT_HIGH 001400:001440 NV17:NV20 NV25:NV41 CODE -001400:001480 NV41:NV50 CODE -001400:001500 NV50:GF100 CODE -001578 NV41:NV50 EVENTS +001400:001480 NV41:G80 CODE +001400:001500 G80:GF100 CODE +001578 NV41:G80 EVENTS 080000:080200 G92:GF100 NEW_CODE ============== ==================== ========== @@ -64,8 +64,8 @@ Code space ========== The HWSQ commands are stored in dedicated code RAM. The code RAM is 0x40 -bytes long on NV17:NV41 cards, 0x80 bytes long on NV41:NV50, 0x100 bytes long -on NV50:G92, and 0x200 bytes long on G92+. +bytes long on NV17:NV41 cards, 0x80 bytes long on NV41:G80, 0x100 bytes long +on G80:G92, and 0x200 bytes long on G92+. The code RAM is byte-oriented, but the MMIO registers used to access it are word-oriented, and touch 4 bytes at once. They are treated as little-endian: @@ -81,8 +81,8 @@ by 4, accesses bytes i..i+3 of code RAM. The old 0x1400 window still exists, but is limitted to first 0x100 bytes of code RAM. MMIO 0x1400 + [0..0xf] * 4: CODE [NV17:NV41] -MMIO 0x1400 + [0..0x1f] * 4: CODE [NV41:NV50] -MMIO 0x1400 + [0..0x3f] * 4: CODE [NV50:GF100] +MMIO 0x1400 + [0..0x1f] * 4: CODE [NV41:G80] +MMIO 0x1400 + [0..0x3f] * 4: CODE [G80:GF100] MMIO 0x80000 + [0..0x7f] * 4: NEW_CODE [G92:GF100] Index i accesses code RAM bytes i*4, i*4+1, i*4+2, i*4+3, mapped to bits 0-7, 8-15, 16-23, 24-31 respectively. @@ -257,24 +257,24 @@ MMIO 0x001098 bit 4: HWSQ_OVERRIDE_MODE The known flags are: -- 0: :ref:`60081c/60281c/CR4d b0 [NV17:NV50] <nv10-gpio-lines>` -- 1: :ref:`60081c/60281c/CR4d b1 [NV17:NV50] <nv10-gpio-lines>` -- 2: :ref:`60081c/60281c/CR4d b4 [NV17:NV50] <nv10-gpio-lines>` -- 3: :ref:`60081c/60281c/CR4d b5 [NV17:NV50] <nv10-gpio-lines>` +- 0: :ref:`60081c/60281c/CR4d b0 [NV17:G80] <nv10-gpio-lines>` +- 1: :ref:`60081c/60281c/CR4d b1 [NV17:G80] <nv10-gpio-lines>` +- 2: :ref:`60081c/60281c/CR4d b4 [NV17:G80] <nv10-gpio-lines>` +- 3: :ref:`60081c/60281c/CR4d b5 [NV17:G80] <nv10-gpio-lines>` - 4: :ref:`680880 b28 [NV17:NV40] <pramdac-mmio>` - 5: :ref:`682880 b28 [NV17:NV40] <pramdac-mmio>` -- 6: :ref:`680880 b29 [NV17:NV50] <pramdac-mmio>` -- 7: :ref:`682880 b29 [NV17:NV50] <pramdac-mmio>` -- 14: :ref:`60081c/60281c b28 [NV31:NV50] <nv10-gpio-lines>` -- 15: :ref:`60081c/60281c b29 [NV31:NV50] <nv10-gpio-lines>` +- 6: :ref:`680880 b29 [NV17:G80] <pramdac-mmio>` +- 7: :ref:`682880 b29 [NV17:G80] <pramdac-mmio>` +- 14: :ref:`60081c/60281c b28 [NV31:G80] <nv10-gpio-lines>` +- 15: :ref:`60081c/60281c b29 [NV31:G80] <nv10-gpio-lines>` - 16: FB_PAUSE [NV41-] [see below] -- 25: :ref:`15fc b31 [NV41:NV50] <nv10-gpio-pwm>` -- 26: :ref:`15f4 b31 [NV41:NV50] <nv10-gpio-pwm>` -- 27: :ref:`10f0 b31 [NV17:NV50] <nv10-gpio-pwm>` -- 28: 1084 b22 [NV17:NV50] -- 29: 1084 b24 [NV17:NV50] -- 30: 1084 b26 [NV17:NV50] -- 31: 1084 b27 [NV17:NV50] +- 25: :ref:`15fc b31 [NV41:G80] <nv10-gpio-pwm>` +- 26: :ref:`15f4 b31 [NV41:G80] <nv10-gpio-pwm>` +- 27: :ref:`10f0 b31 [NV17:G80] <nv10-gpio-pwm>` +- 28: 1084 b22 [NV17:G80] +- 29: 1084 b24 [NV17:G80] +- 30: 1084 b26 [NV17:G80] +- 31: 1084 b27 [NV17:G80] .. todo:: 8, 9, 13 seem used by microcode! .. todo:: check variants for 15f4, 15fc @@ -356,10 +356,10 @@ Opcode: 0x5f <e> <v> - ewait #event #value The events are: - 0: FB_PAUSED [see below] -- 1: CRTC0_VBLANK [:ref:`nv41 <pcrtc-blank>`, :ref:`nv50 <pdisplay-blank>`] -- 2: CRTC0_HBLANK [:ref:`nv41 <pcrtc-blank>`, :ref:`nv50 <pdisplay-blank>`] -- 3: CRTC1_VBLANK [:ref:`nv41 <pcrtc-blank>`, :ref:`nv50 <pdisplay-blank>`] -- 4: CRTC1_HBLANK [:ref:`nv41 <pcrtc-blank>`, :ref:`nv50 <pdisplay-blank>`] +- 1: CRTC0_VBLANK [:ref:`nv41 <pcrtc-blank>`, :ref:`G80 <pdisplay-blank>`] +- 2: CRTC0_HBLANK [:ref:`nv41 <pcrtc-blank>`, :ref:`G80 <pdisplay-blank>`] +- 3: CRTC1_VBLANK [:ref:`nv41 <pcrtc-blank>`, :ref:`G80 <pdisplay-blank>`] +- 4: CRTC1_HBLANK [:ref:`nv41 <pcrtc-blank>`, :ref:`G80 <pdisplay-blank>`] Framebuffer pause feature @@ -380,9 +380,9 @@ the framebuffer is actually paused. The FB_PAUSED event is provided for that. The FB_PAUSED event is set to 1 iff framebuffer pause has been requested by HWSQ and completed by memory controller. -On NV41:NV50, framebuffer pause will indefinitely block all accesses to memory +On NV41:G80, framebuffer pause will indefinitely block all accesses to memory until it's unpaused. This includes accesses from the host via BAR1, BAR2, PEEPHOLE, and the PRAMIN range. -On NV50+, framebuffer pause not only blocks memory accesses, it additionally +On G80+, framebuffer pause not only blocks memory accesses, it additionally blocks all accesses to the GPU from host - including MMIO accesses. diff --git a/docs/hw/bus/pbus.rst b/docs/hw/bus/pbus.rst index 41bd8386..d80a7610 100644 --- a/docs/hw/bus/pbus.rst +++ b/docs/hw/bus/pbus.rst @@ -30,17 +30,17 @@ The registers in the PBUS area are: 0x084 DEBUG_1 pbus-debug-1 NV4: 0x098 DEBUG_6 pbus-debug-6 NV17:NV20,NV25: 0x100 INTR pbus-intr NV3: - 0x104 INTR_GPIO pbus-intr-gpio NV31:NV50 + 0x104 INTR_GPIO pbus-intr-gpio NV31:G80 0x140 INTR_ENABLE pbus-intr-enable NV3: - 0x144 INTR_GPIO_ENABLE pbus-intr-gpio-enable NV31:NV50 + 0x144 INTR_GPIO_ENABLE pbus-intr-gpio-enable NV31:G80 0x144 INTR_ENABLE_NRHOST pbus-intr-enable-nrhost GF100: - 0x150 INTR_USER0_TRIGGER pbus-intr-user-trigger NV50: - 0x154[4] INTR_USER0_SCRATCH pbus-intr-user-scratch NV50: + 0x150 INTR_USER0_TRIGGER pbus-intr-user-trigger G80: + 0x154[4] INTR_USER0_SCRATCH pbus-intr-user-scratch G80: 0x170 INTR_USER1_TRIGGER pbus-intr-user-trigger GF100: 0x174[4] INTR_USER1_SCRATCH pbus-intr-user-scratch GF100: 0x200 ROM_TIMINGS nv3-prom-rom-timings NV4:NV10 - 0x200 ROM_TIMINGS nv10-prom-rom-timings NV10:NV50 - 0x204 ROM_SPI_CTRL prom-spi-ctrl NV17:NV20,NV25:NV50 + 0x200 ROM_TIMINGS nv10-prom-rom-timings NV10:G80 + 0x204 ROM_SPI_CTRL prom-spi-ctrl NV17:NV20,NV25:G80 0xa14 IBUS_TIMEOUT pbus-ibus-timeout GT215:GF100 .. todo:: connect @@ -48,10 +48,10 @@ The registers in the PBUS area are: ============= ========== =============== Range Variants Description ============= ========== =============== - 0010f0:0010f4 NV11:NV50 :ref:`PWM - PWM generators <pbus-mmio-pwm>` + 0010f0:0010f4 NV11:G80 :ref:`PWM - PWM generators <pbus-mmio-pwm>` 001300:001380 NV17:NV20 :ref:`HWSQ - hardware sequencer <hwsq-mmio>` NV25:GF100 - 001380:001400 NV41:NV50 :ref:`VGA_STACK <pbus-mmio-vga-stack>` + 001380:001400 NV41:G80 :ref:`VGA_STACK <pbus-mmio-vga-stack>` 001400:001500 NV17:NV20 :ref:`HWSQ - hardware sequencer <hwsq-mmio>` NV25:GF100 001500:001540 ??? :ref:`DEBUG registers <pbus-mmio-debug>` @@ -60,14 +60,14 @@ The registers in the PBUS area are: 001578:001580 NV41:GF100 :ref:`HWSQ - hardware sequencer <hwsq-mmio>` 001580:0015a0 NV17:NV20 CLOCK_GATE - clock gating registers [see below] NV25:GF100 - 0015b0:0015c0 NV43:NV50 :ref:`THERM - thermal sensor <nv43-therm-mmio>` - 0015f4:001604 NV41:NV50 :ref:`PWM - PWM generators <pbus-mmio-pwm>` + 0015b0:0015c0 NV43:G80 :ref:`THERM - thermal sensor <nv43-therm-mmio>` + 0015f4:001604 NV41:G80 :ref:`PWM - PWM generators <pbus-mmio-pwm>` 001700:001800 TC :ref:`HOST_MEM - host memory access setup <pbus-mmio-nv44-host-mem>` - 001700:001800 NV50:GF100 :ref:`HOST_MEM - host memory access setup <pbus-mmio-nv50-host-mem>` + 001700:001800 G80:GF100 :ref:`HOST_MEM - host memory access setup <pbus-mmio-g80-host-mem>` 001700:001800 GF100- :ref:`HOST_MEM - host memory access setup <pbus-mmio-gf100-host-mem>` - 001800:001a00 NV1:NV50 :ref:`PCI - PCI configuration space <pbus-mmio-pci>` - 001900:001980 NV50:GF100 :ref:`REMAP - BAR1 remapping circuitry <pbus-mmio-nv50-remap>` - 001980:001a00 NV50:GF100 :ref:`P2P - NV50 P2P slave <pbus-mmio-nv50-p2p>` + 001800:001a00 NV1:G80 :ref:`PCI - PCI configuration space <pbus-mmio-pci>` + 001900:001980 G80:GF100 :ref:`REMAP - BAR1 remapping circuitry <pbus-mmio-g80-remap>` + 001980:001a00 G80:GF100 :ref:`P2P - G80 P2P slave <pbus-mmio-g80-p2p>` ============= ========== =============== .. todo:: loads and loads of unknown registers not shown @@ -81,9 +81,9 @@ usually group together unrelated bits. The known bits include: .. reg:: 32 pbus-debug-1 misc stuff - - bit 11: FUSE_READOUT_ENABLE - enables reads from fuses in :ref:`PFUSE <pfuse>` [NV50:GF100] + - bit 11: FUSE_READOUT_ENABLE - enables reads from fuses in :ref:`PFUSE <pfuse>` [G80:GF100] - bit 28: HEADS_TIED - mirrors writes to :ref:`CRTC <pcrtc-mmio>`/:ref:`RAMDAC <pramdac-mmio>` registers on any head to - the other head too [NV11:NV20, NV25:NV50] + the other head too [NV11:NV20, NV25:G80] .. reg:: 32 pbus-debug-6 misc stuff @@ -113,7 +113,7 @@ and INTR_EN_NRHOST registers: .. reg:: 32 pbus-intr interrupt status/acknowledge - - bit 0: BUS_ERROR - ??? [NV3:NV50] + - bit 0: BUS_ERROR - ??? [NV3:G80] - bit 1: MMIO_DISABLED_ENG - MMIO access from host failed due to accessing an area disabled via PMC.ENABLE [GF100-] [XXX: document] - bit 2: MMIO_RING_ERR - :ref:`MMIO access from host failed due to some error in @@ -129,12 +129,12 @@ and INTR_EN_NRHOST registers: - bit 12: PEEPHOLE_W_PAIR_MISMATCH - :ref:`violation of PEEPHOLE write port protocol [NV30:GF100] <pbus-intr-peephole-w-pair-mismatch>` - bit 16: THERM_ALARM - Temperature is critical and requires actions - [NV43-] [:ref:`NV43 <nv43-therm-intr-alarm>`, :ref:`NV50 <ptherm-intr>`] + [NV43-] [:ref:`NV43 <nv43-therm-intr-alarm>`, :ref:`G80 <ptherm-intr>`] - bit 17: THERM_THRS_LOW - Temperature is lower than TEMP_RANGE.LOW - [NV43:NV50] [:ref:`NV43 <nv43-therm-intr-range>`] + [NV43:G80] [:ref:`NV43 <nv43-therm-intr-range>`] - bit 18: THERM_THRS_HIGH - Temperature is higher than TEMP_RANGE.HIGH - [NV43:NV50] [:ref:`NV43 <nv43-therm-intr-range>`] - - bit 26: USER0 - user interrupt #0 [NV50-] [see below] + [NV43:G80] [:ref:`NV43 <nv43-therm-intr-range>`] + - bit 26: USER0 - user interrupt #0 [G80-] [see below] - bit 28: USER1 - user interrupt #1. Note that this interrupt cannot be enabled for delivery to NRHOST line. [GF100-] [see below] @@ -149,7 +149,7 @@ are set in the written value. Same bitfields as in INTR, except USER1 is not present. -On NV40:NV50 GPUs, the PBUS additionally deals with GPIO change interrupts, +On NV40:G80 GPUs, the PBUS additionally deals with GPIO change interrupts, which are reported via INTR_GPIO register and enabled via INTR_GPIO_EN register. These registers effectively function as extra bits to INTR and INTR_EN. For description of these registrers and GPIO interupts, see @@ -159,7 +159,7 @@ INTR_EN. For description of these registrers and GPIO interupts, see User interrupts --------------- -NV50+ PBUS has one [NV50:GF100] or two [GF100-] user-triggerable interupts. +G80+ PBUS has one [G80:GF100] or two [GF100-] user-triggerable interupts. These interrupts are triggered by writing any value to a trigger register: .. reg:: 32 intr-user-trigger user interrupt generation diff --git a/docs/hw/bus/pci.rst b/docs/hw/bus/pci.rst index b0d77d88..8f96cadb 100644 --- a/docs/hw/bus/pci.rst +++ b/docs/hw/bus/pci.rst @@ -49,7 +49,7 @@ PCI/PCIE configuration space registers - 0x44-0x4f: PCI AGP capability [AGP cards only] - 0x50-0x53: ROM shadow enable flag - 0 to disable ROM shadow, disable video output, and use EEPROM for PCI ROM; 1 to enable ROM shadow and - video output, using shadow copy in VRAM for PCI ROM. On NV4:NV50 + video output, using shadow copy in VRAM for PCI ROM. On NV4:G80 cards, enabling shadowing additionally disables PROM read/write circuitry. @@ -76,7 +76,7 @@ And for PCIE cards only: All registers introduced by nvidia [ie. not in standard PCI config header or capabilities] are 32-bit LE words. -On NV1:NV50 cards, PCI config space, or first 0x100 bytes of PCIE config +On NV1:G80 cards, PCI config space, or first 0x100 bytes of PCIE config space, are also mapped to MMIO register space at addresses 0x1800-0x18ff. On NV40+ cards, all 0x1000 bytes of PCIE config space are mapped to MMIO register space at addresses 0x88000-0x88fff. It's a bad idea to access config @@ -96,7 +96,7 @@ other one, and show its own pciid instead of the GPU's. .. todo:: is that all? -Note that bus master functionality may need to be enabled for NV50+ VM +Note that bus master functionality may need to be enabled for G80+ VM circuitry to work even when only VRAM is being accessed. The reason for this is currently unknown. diff --git a/docs/hw/bus/pfuse.rst b/docs/hw/bus/pfuse.rst index 08cb297f..fc040b9a 100644 --- a/docs/hw/bus/pfuse.rst +++ b/docs/hw/bus/pfuse.rst @@ -22,8 +22,8 @@ MMIO registers ============== .. space:: 8 pfuse 0x1000 efuses storing GPU options - 0x144 TPC_DISABLE_MASK pfuse-tpc-disable-mask NV50:GF100 - 0x148 PART_DISABLE_MASK pfuse-part-disable-mask NV50:GF100 + 0x144 TPC_DISABLE_MASK pfuse-tpc-disable-mask G80:GF100 + 0x148 PART_DISABLE_MASK pfuse-part-disable-mask G80:GF100 0x1a0 TEMP_CAL_SLOPE_MUL_OFFSET pfuse-temp-cal-slope-mul-offset 0x1a4 TEMP_CAL_OFFSET_MUL_OFFSET pfuse-temp-cal-offset-mul-offset 0x1a8 TEMP_CAL_OK pfuse-temp-cal-ok diff --git a/docs/hw/bus/pmc.rst b/docs/hw/bus/pmc.rst index 76ec3a3c..bd39619d 100644 --- a/docs/hw/bus/pmc.rst +++ b/docs/hw/bus/pmc.rst @@ -143,8 +143,8 @@ either endianness will switch the card to that endianness. This register and the endian switch don't exist on pre-NV1A cards - they're always little-endian. -Note that this switch is also used by NV50+ PFIFO as its default endianness -- see :ref:`NV50+ PFIFO<nv50-pfifo>` for details. +Note that this switch is also used by G80+ PFIFO as its default endianness +- see :ref:`G80+ PFIFO<g80-pfifo>` for details. The MMIO areas containing aliases of 8-bit VGA registers are unaffected by this switch, despite being in BAR0. @@ -184,7 +184,7 @@ On NV3:NV4, the bits are: - 24: :ref:`PCRTC <pcrtc>` - 28: :ref:`PRAMDAC.VIDEO <pvideo>` -On NV4:NV50, the bits are: +On NV4:G80, the bits are: - 0: ??? - alleged to be related to I2C [NV10-] [XXX] - 1: :ref:`PVPE <pvpe>` [NV17-] @@ -193,25 +193,25 @@ On NV4:NV50, the bits are: - 12: :ref:`PGRAPH <nv4-pgraph>` [NV4:NV10] - 12: :ref:`PGRAPH <nv10-pgraph>` [NV10:NV20] - 12: :ref:`PGRAPH <nv20-pgraph>` [NV20:NV40] -- 12: :ref:`PGRAPH <nv40-pgraph>` [NV40:NV50] +- 12: :ref:`PGRAPH <nv40-pgraph>` [NV40:G80] - 13: PGRAPH CS??? apparently exists on some late NV4x... [NV4?-] - 16: :ref:`PTIMER <ptimer>` - 20: PFB [:ref:`NV3 <nv3-pfb>`, :ref:`NV10 <nv10-pfb>`, :ref:`NV40 <nv40-pfb>`, :ref:`NV44 <nv44-pfb>`] - 24: :ref:`PCRTC <pcrtc>` - 25: :ref:`PCRTC2 <pcrtc>` [NV11-] -- 26: :ref:`PTV <ptv>` [NV17:NV20, NV25:NV50] -- 28: :ref:`PRAMDAC.VIDEO <pvideo>` [NV4:NV10] or :ref:`PVIDEO <pvideo>` [NV10:NV50] +- 26: :ref:`PTV <ptv>` [NV17:NV20, NV25:G80] +- 28: :ref:`PRAMDAC.VIDEO <pvideo>` [NV4:NV10] or :ref:`PVIDEO <pvideo>` [NV10:G80] .. todo:: figure out the CS thing, figure out the variants. Known not to exist on NV40, NV43, NV44, NV4E, NV49; known to exist on NV63 -On NV50:GF100, the bits are: +On G80:GF100, the bits are: - 0: ??? - alleged to be related to I2C -- 1: :ref:`PVPE <pvpe>` [NV50:G98 G200:MCP77] +- 1: :ref:`PVPE <pvpe>` [G80:G98 G200:MCP77] - 1: :ref:`PPPP <pppp>` [G98:G200 MCP77-] - 4: :ref:`PMEDIA <pmedia>` -- 8: :ref:`PFIFO <nv50-pfifo>` -- 12: :ref:`PGRAPH <nv50-pgraph>` +- 8: :ref:`PFIFO <g80-pfifo>` +- 12: :ref:`PGRAPH <g80-pgraph>` - 13: :ref:`PCOPY <pcopy>` [GT215-] - 14: :ref:`PCRYPT2 <pcrypt2>` [G84:G98 G200:MCP77] - 14: :ref:`PCRYPT3 <pcrypt3>` [G98:G200 MCP77:GT215] @@ -221,17 +221,17 @@ On NV50:GF100, the bits are: - 16: :ref:`PTIMER <ptimer>` - 17: :ref:`PVP2 <pvp2>` [G84:G98 G200:MCP77] - 17: :ref:`PVDEC <pvdec>` [G98:G200 MCP77-] -- 20: :ref:`PFB <nv50-pfb>` -- 21: :ref:`PGRAPH CHSW <nv50-pfifo-chsw>` [G84-] -- 22: :ref:`PMPEG CHSW <nv50-pfifo-chsw>` [G84-] -- 23: :ref:`PCOPY CHSW <nv50-pfifo-chsw>` [GT215-] -- 24: :ref:`PVP2 CHSW <nv50-pfifo-chsw>` [G84:G98 G200:MCP77] -- 24: :ref:`PVDEC CHSW <nv50-pfifo-chsw>` [G98:G200 MCP77-] -- 25: :ref:`PCRYPT2 CHSW <nv50-pfifo-chsw>` [G84:G98 G200:MCP77] -- 25: :ref:`PCRYPT3 CHSW <nv50-pfifo-chsw>` [G98:G200 MCP77:GT215] -- 25: :ref:`PVCOMP CHSW <nv50-pfifo-chsw>` [MCP89] -- 26: :ref:`PBSP CHSW <nv50-pfifo-chsw>` [G84:G98 G200:MCP77] -- 26: :ref:`PVLD CHSW <nv50-pfifo-chsw>` [G98:G200 MCP77-] +- 20: :ref:`PFB <g80-pfb>` +- 21: :ref:`PGRAPH CHSW <g80-pfifo-chsw>` [G84-] +- 22: :ref:`PMPEG CHSW <g80-pfifo-chsw>` [G84-] +- 23: :ref:`PCOPY CHSW <g80-pfifo-chsw>` [GT215-] +- 24: :ref:`PVP2 CHSW <g80-pfifo-chsw>` [G84:G98 G200:MCP77] +- 24: :ref:`PVDEC CHSW <g80-pfifo-chsw>` [G98:G200 MCP77-] +- 25: :ref:`PCRYPT2 CHSW <g80-pfifo-chsw>` [G84:G98 G200:MCP77] +- 25: :ref:`PCRYPT3 CHSW <g80-pfifo-chsw>` [G98:G200 MCP77:GT215] +- 25: :ref:`PVCOMP CHSW <g80-pfifo-chsw>` [MCP89] +- 26: :ref:`PBSP CHSW <g80-pfifo-chsw>` [G84:G98 G200:MCP77] +- 26: :ref:`PVLD CHSW <g80-pfifo-chsw>` [G98:G200 MCP77-] - 27: ??? [G84-] - 28: ??? [G84-] - 30: :ref:`PDISPLAY <pdisplay>` @@ -421,28 +421,28 @@ For NV3: - 28: :ref:`PBUS <pbus-intr>` - 31: software -For NV4:NV50: +For NV4:G80: -- 0: :ref:`PVPE <pvpe-intr>` [NV17:NV20 and NV25:NV50] +- 0: :ref:`PVPE <pvpe-intr>` [NV17:NV20 and NV25:G80] - 4: :ref:`PMEDIA <pmedia-intr>` - 8: :ref:`PFIFO <nv4-pfifo-intr>` - 12: :ref:`PGRAPH <nv4-pgraph-intr>` -- 16: :ref:`PRAMDAC.VIDEO <pvideo-intr>` [NV4:NV10] or :ref:`PVIDEO <pvideo-intr>` [NV10:NV50] +- 16: :ref:`PRAMDAC.VIDEO <pvideo-intr>` [NV4:NV10] or :ref:`PVIDEO <pvideo-intr>` [NV10:G80] - 20: :ref:`PTIMER <ptimer-intr>` - 24: :ref:`PCRTC <pcrtc-intr>` -- 25: :ref:`PCRTC2 <pcrtc-intr>` [NV17:NV20 and NV25:NV50] +- 25: :ref:`PCRTC2 <pcrtc-intr>` [NV17:NV20 and NV25:G80] - 28: :ref:`PBUS <pbus-intr>` - 31: software -For NV50:GF100: +For G80:GF100: -- 0: :ref:`PVPE <pvpe-intr>` [NV50:G98 G200:MCP77] +- 0: :ref:`PVPE <pvpe-intr>` [G80:G98 G200:MCP77] - 0: :ref:`PPPP <pppp-falcon>` [G98:G200 MCP77-] - 4: :ref:`PMEDIA <pmedia-intr>` -- 8: :ref:`PFIFO <nv50-pfifo-intr>` - has separate NRHOST line on GT215+ +- 8: :ref:`PFIFO <g80-pfifo-intr>` - has separate NRHOST line on GT215+ - 9: ??? [GT215?-] - 11: ??? [GT215?-] -- 12: :ref:`PGRAPH <nv50-pgraph-intr>` +- 12: :ref:`PGRAPH <g80-pgraph-intr>` - 13: ??? [GT215?-] - 14: :ref:`PCRYPT2 <pcrypt2-intr>` [G84:G98 G200:MCP77] - 14: :ref:`PCRYPT3 <pcrypt3-falcon>` [G98:G200 MCP77:GT215] @@ -455,7 +455,7 @@ For NV50:GF100: - 18: :ref:`PDAEMON [GT215-] <pdaemon-falcon>` - 19: :ref:`PTHERM [GT215-] <ptherm-intr>` - 20: :ref:`PTIMER <ptimer-intr>` -- 21: :ref:`PNVIO's GPIO interrupts <nv50-gpio-intr>` +- 21: :ref:`PNVIO's GPIO interrupts <g80-gpio-intr>` - 22: :ref:`PCOPY <pcopy-falcon>` - 26: :ref:`PDISPLAY <pdisplay-intr>` - 27: ??? [GT215?-] @@ -483,7 +483,7 @@ For GF100+: - 18: :ref:`PTHERM <ptherm-intr>` - 19: ??? [GF119-] - 20: :ref:`PTIMER <ptimer-intr>` -- 21: :ref:`PNVIO's GPIO interrupts <nv50-gpio-intr>` +- 21: :ref:`PNVIO's GPIO interrupts <g80-gpio-intr>` - 23: ??? - 24: :ref:`PDAEMON <pdaemon-falcon>` - 25: :ref:`PMFB <pmfb-intr>` diff --git a/docs/hw/bus/prma.rst b/docs/hw/bus/prma.rst index c90bb016..5ad5cfef 100644 --- a/docs/hw/bus/prma.rst +++ b/docs/hw/bus/prma.rst @@ -17,8 +17,8 @@ The MMIO registers ================== .. space:: 8 prma 0x1000 real mode BAR access - 0x080 CTRL prma-ctrl NV50: - 0x084 SCRATCH prma-scratch NV50: + 0x080 CTRL prma-ctrl G80: + 0x084 SCRATCH prma-scratch G80: 0x100 SIG prma-sig 0x104 ADDR prma-addr 0x10c DATA_PARTIAL prma-data-partial diff --git a/docs/hw/bus/ptimer.rst b/docs/hw/bus/ptimer.rst index e95acb0a..ed66f6c9 100644 --- a/docs/hw/bus/ptimer.rst +++ b/docs/hw/bus/ptimer.rst @@ -46,9 +46,9 @@ MMIO register list - NV3- ========================= .. space:: 8 nv3-ptimer 0x1000 time measurement and time-based alarms - 0x060 ??? ptimer-unk060 NV50: - 0x064 ??? ptimer-unk064 NV50: - 0x080 ??? ptimer-unk080-nv17 NV17:NV20,NV25:NV50 + 0x060 ??? ptimer-unk060 G80: + 0x064 ??? ptimer-unk064 G80: + 0x080 ??? ptimer-unk080-nv17 NV17:NV20,NV25:G80 0x080 ??? ptimer-unk080-gf100 GF100: 0x084 MMIO_FAULT_ADDR ptimer-mmio-fault-addr NV41: 0x088 MMIO_FAULT_DATA ptimer-mmio-fault-data NV41: @@ -75,7 +75,7 @@ a clock source. The clock source depends on the card: or external clock source. Internal clock source is the crystal [see :ref:`pstraps`] frequency multiplied by a small ratio, while external clock source is HCLK, the host clock [:ref:`nv40 <nv40-clock-hclk>`, - :ref:`nv50 <nv50-clock-hclk>`] + :ref:`g80 <g80-clock-hclk>`] - G84 and up: like NV41, but external clock source is TCLK, the PTIMER clock [:ref:`G84 <g84-clock-tclk>`, :ref:`GT215 <gt215-clock-tclk>`, :ref:`GF100 <gf100-clock-tclk>`] diff --git a/docs/hw/display/nv50/index.rst b/docs/hw/display/g80/index.rst index b5d04cb0..bf0126a7 100644 --- a/docs/hw/display/nv50/index.rst +++ b/docs/hw/display/g80/index.rst @@ -1,5 +1,5 @@ -NV50- display subsystem -======================= +G80 display subsystem +===================== Contents: diff --git a/docs/hw/display/nv50/pcodec.rst b/docs/hw/display/g80/pcodec.rst index fb7f8267..fb7f8267 100644 --- a/docs/hw/display/nv50/pcodec.rst +++ b/docs/hw/display/g80/pcodec.rst diff --git a/docs/hw/display/nv50/pdisplay-daemon.rst b/docs/hw/display/g80/pdisplay-daemon.rst index bdfa4bf4..bdfa4bf4 100644 --- a/docs/hw/display/nv50/pdisplay-daemon.rst +++ b/docs/hw/display/g80/pdisplay-daemon.rst diff --git a/docs/hw/display/nv50/pdisplay.rst b/docs/hw/display/g80/pdisplay.rst index 93194dad..d41c4c97 100644 --- a/docs/hw/display/nv50/pdisplay.rst +++ b/docs/hw/display/g80/pdisplay.rst @@ -1,8 +1,8 @@ .. _pdisplay: -============================= -PDISPLAY: NV50 display engine -============================= +============================ +PDISPLAY: G80 display engine +============================ .. contents:: @@ -18,7 +18,7 @@ Introduction MMIO registers ============== -.. space:: 8 nv50-pdisplay 0xb0000 unified display engine +.. space:: 8 g80-pdisplay 0xb0000 unified display engine .. todo:: write me diff --git a/docs/hw/display/nv50/pkfuse.rst b/docs/hw/display/g80/pkfuse.rst index 81451a0a..81451a0a 100644 --- a/docs/hw/display/nv50/pkfuse.rst +++ b/docs/hw/display/g80/pkfuse.rst diff --git a/docs/hw/display/nv50/punk1c3.rst b/docs/hw/display/g80/punk1c3.rst index d4e415e6..d4e415e6 100644 --- a/docs/hw/display/nv50/punk1c3.rst +++ b/docs/hw/display/g80/punk1c3.rst diff --git a/docs/hw/display/nv50/vga-mutex.rst b/docs/hw/display/g80/vga-mutex.rst index eebcf756..ab903caf 100644 --- a/docs/hw/display/nv50/vga-mutex.rst +++ b/docs/hw/display/g80/vga-mutex.rst @@ -1,8 +1,8 @@ -.. _nv50-vga-mutex: +.. _g80-vga-mutex: -================ -NV50 VGA mutexes -================ +=============== +G80 VGA mutexes +=============== .. contents:: @@ -11,13 +11,13 @@ Introduction ============ Dedicated mutex support hardware supporting trylock and unlock operations -on 64 mutexes by 2 clients. Present on NV50+ cards. +on 64 mutexes by 2 clients. Present on G80+ cards. MMIO registers ============== -On NV50+, the registers are located in PDISPLAY.VGA area: +On G80+, the registers are located in PDISPLAY.VGA area: - 619e80 MUTEX_TRYLOCK_A[0] - 619e84 MUTEX_TRYLOCK_A[1] diff --git a/docs/hw/display/g80/vga.rst b/docs/hw/display/g80/vga.rst new file mode 100644 index 00000000..def25371 --- /dev/null +++ b/docs/hw/display/g80/vga.rst @@ -0,0 +1,27 @@ +.. _g80-vga: + +================= +G80 VGA emulation +================= + +.. contents:: + +.. todo:: write me + + +Introduction +============ + +.. todo:: write me + + +MMIO registers +============== + +.. space:: 8 g80-prmio 0x1000 VGA registers + + .. todo:: write me + +.. space:: 8 g80-prmfb 0x20000 VGA memory window access + + .. todo:: write me diff --git a/docs/hw/display/index.rst b/docs/hw/display/index.rst index 81f558b2..5ad212b7 100644 --- a/docs/hw/display/index.rst +++ b/docs/hw/display/index.rst @@ -8,4 +8,4 @@ Contents: nv1/index nv3/index - nv50/index + g80/index diff --git a/docs/hw/display/nv3/index.rst b/docs/hw/display/nv3/index.rst index c5305958..959d516a 100644 --- a/docs/hw/display/nv3/index.rst +++ b/docs/hw/display/nv3/index.rst @@ -1,5 +1,5 @@ -NV3:NV50 display subsystem -========================== +NV3:G80 display subsystem +========================= Contents: diff --git a/docs/hw/display/nv3/vga-stack.rst b/docs/hw/display/nv3/vga-stack.rst index b714f502..fe02e1f5 100644 --- a/docs/hw/display/nv3/vga-stack.rst +++ b/docs/hw/display/nv3/vga-stack.rst @@ -17,12 +17,12 @@ it is for, apparently related to VGA. Present on NV41+ cards. .. _pbus-mmio-vga-stack: .. _pdisplay-mmio-vga-stack: .. _nv3-cr-vga-stack: -.. _nv50-cr-vga-stack: +.. _g80-cr-vga-stack: MMIO registers ============== -On NV41:NV50, the registers are located in PBUS area: +On NV41:G80, the registers are located in PBUS area: - 001380 VAL - 001384 CTRL @@ -34,7 +34,7 @@ They are also aliased in the VGA CRTC register space: - CR90 VAL - CR91 CTRL -On NV50+, the registers are located in PDISPLAY.VGA area: +On G80+, the registers are located in PDISPLAY.VGA area: - 619e40 VAL - 619e44 CTRL @@ -53,8 +53,8 @@ Description The stack is made of the following data: - an array of 0x200 bytes [the actual stack] -- a write shadow byte, WVAL [NV50+ only] -- a read shadow byte, RVAL [NV50+ only] +- a write shadow byte, WVAL [G80+ only] +- a read shadow byte, RVAL [G80+ only] - a 10-bit stack pointer [SP] - 3 config bits: - push mode: auto or manual @@ -79,11 +79,11 @@ addition to accessing the VAL reg. For manual pushes, the push should be triggered after writing the value. For pops, the pop should be triggered before or after reading the value, depending on selected manual pop mode. -The stack also keeps track of overflow and underflow errors. On NV41:NV50, +The stack also keeps track of overflow and underflow errors. On NV41:G80, while these error conditions are detected, the offending access is still -executed [and the stack pointer wraps]. On NV50+, the offending access is -discarded. The error status is sticky. On NV41:NV50, it can only be cleared -by poking the CONFIG register clear bits. On NV50+, the overflow status +executed [and the stack pointer wraps]. On G80+, the offending access is +discarded. The error status is sticky. On NV41:G80, it can only be cleared +by poking the CONFIG register clear bits. On G80+, the overflow status is cleared by executing a pop, and the underflow status is cleared by executing a push. @@ -93,9 +93,9 @@ Stack access registers The stack data is read or written through the VAL register: -MMIO 0x001380 / CR 0x90: VAL [NV41:NV50] +MMIO 0x001380 / CR 0x90: VAL [NV41:G80] -MMIO 0x619e40 / CR 0xa2: VAL [NV50-] +MMIO 0x619e40 / CR 0xa2: VAL [G80-] Accesses a stack entry. A write to this register stored the low 8 bits of written data as a byte to be pushed. If automatic push mode is set, the value is pushed immediately. Otherwise, it is pushed after PUSH_TRIGGER @@ -107,9 +107,9 @@ MMIO 0x619e40 / CR 0xa2: VAL [NV50-] The CTRL register is used to manually push/pop the stack and check its status: -MMIO 0x001384 / CR 0x91: CTRL [NV41:NV50] +MMIO 0x001384 / CR 0x91: CTRL [NV41:G80] -MMIO 0x619e44 / CR 0xa3: CTRL [NV50-] +MMIO 0x619e44 / CR 0xa3: CTRL [G80-] - bit 0: PUSH_TRIGGER - when written as 1, executes a push. Always reads as 0. - bit 1: POP_TRIGGER - like above, for pop. - bit 4: EMPTY - read-only, reads as 1 when SP == 0. @@ -122,9 +122,9 @@ MMIO 0x619e44 / CR 0xa3: CTRL [NV50-] To configure the stack, the CONFIG register is used: -MMIO 0x001388: CONFIG [NV41:NV50] +MMIO 0x001388: CONFIG [NV41:G80] -MMIO 0x619e48: CONFIG [NV50-] +MMIO 0x619e48: CONFIG [G80-] - bit 0: PUSH_MODE - selects push mode [see above] - 0: MANUAL @@ -141,22 +141,22 @@ MMIO 0x619e48: CONFIG [NV50-] - 0: POP_READ - pop before read - 1: READ_POP - read before pop - - bit 6: OVERFLOW_CLEAR [NV41:NV50] - when written as 1, clears CTRL.OVERFLOW + - bit 6: OVERFLOW_CLEAR [NV41:G80] - when written as 1, clears CTRL.OVERFLOW to 0. Always reads as 0. - - bit 7: UNDERFLOW_CLEAR [NV41:NV50] - like above, for CTRL.UNDERFLOW + - bit 7: UNDERFLOW_CLEAR [NV41:G80] - like above, for CTRL.UNDERFLOW The stack pointer can be accessed directly by the SP register: -MMIO 0x00138c: SP [NV41:NV50] +MMIO 0x00138c: SP [NV41:G80] -MMIO 0x619e4c: SP [NV50-] +MMIO 0x619e4c: SP [G80-] The stack pointer. Only low 10 bits are valid. Internal operation ================== -NV41:NV50 VAL write:: +NV41:G80 VAL write:: if (SP >= 0x200) CTRL.OVERFLOW = 1; @@ -164,11 +164,11 @@ NV41:NV50 VAL write:: if (CONFIG.PUSH_MODE == AUTO) PUSH(); -NV41:NV50 PUSH:: +NV41:G80 PUSH:: SP++; -NV41:NV50 VAL read:: +NV41:G80 VAL read:: if (SP == 0) CTRL.UNDERFLOW = 1; @@ -182,17 +182,17 @@ NV41:NV50 VAL read:: res = STACK[SP-1]; } -NV41:NV50 POP:: +NV41:G80 POP:: SP--; -NV50+ VAL write:: +G80+ VAL write:: WVAL = val; if (CONFIG.PUSH_MODE == AUTO) PUSH(); -NV50+ PUSH:: +G80+ PUSH:: if (SP >= 0x200) CTRL.OVERFLOW = 1; @@ -200,7 +200,7 @@ NV50+ PUSH:: STACK[SP++] = WVAL; CTRL.UNDERFLOW = 0; -NV50+ VAL read:: +G80+ VAL read:: if (CONFIG.POP_MODE == AUTO) { POP(); @@ -212,7 +212,7 @@ NV50+ VAL read:: res = STACK[SP-1]; } -NV50+ POP:: +G80+ POP:: if (SP == 0) CTRL.UNDERFLOW = 1; diff --git a/docs/hw/display/nv50/vga.rst b/docs/hw/display/nv50/vga.rst deleted file mode 100644 index b3524d6d..00000000 --- a/docs/hw/display/nv50/vga.rst +++ /dev/null @@ -1,27 +0,0 @@ -.. _nv50-vga: - -================== -NV50 VGA emulation -================== - -.. contents:: - -.. todo:: write me - - -Introduction -============ - -.. todo:: write me - - -MMIO registers -============== - -.. space:: 8 nv50-prmio 0x1000 VGA registers - - .. todo:: write me - -.. space:: 8 nv50-prmfb 0x20000 VGA memory window access - - .. todo:: write me diff --git a/docs/hw/fifo/classes.rst b/docs/hw/fifo/classes.rst index 1d34d7ed..a98f16a6 100644 --- a/docs/hw/fifo/classes.rst +++ b/docs/hw/fifo/classes.rst @@ -105,58 +105,58 @@ Class Type Subtype GPUs Name 0012 ctx2d beta NV4:G84 NV1_BETA 0013 op2d NV4:NV5 NV1_OP_ROP_AND 0015 op2d NV4:NV5 NV1_OP_CHROMA -0017 ctx2d chroma NV4:NV50 NV1_CHROMA -0018 ctx2d patt NV4:NV50 NV1_PATTERN +0017 ctx2d chroma NV4:G80 NV1_CHROMA +0018 ctx2d patt NV4:G80 NV1_PATTERN 0019 ctx2d clip NV4:G84 NV1_CLIP 001c r2d lin NV4:NV40 NV1_LIN 001d r2d tri NV4:NV40 NV1_TRI 001e r2d rect NV4:NV40 NV1_RECT -001f r2d blit NV4:NV50 NV1_BLIT +001f r2d blit NV4:G80 NV1_BLIT 0021 r2d ifc NV4:NV40 NV1_IFC 0030 null NV4:GF100 NULL -0036 r2d sifc NV4:NV50 NV3_SIFC -0037 r2d sifm NV4:NV50 NV3_SIFM -0038 uni2d dvd NV4:NV50 NV4_DVD_SUBPICTURE -0039 mem m2mf NV4:NV50 NV3_M2MF +0036 r2d sifc NV4:G80 NV3_SIFC +0037 r2d sifm NV4:G80 NV3_SIFM +0038 uni2d dvd NV4:G80 NV4_DVD_SUBPICTURE +0039 mem m2mf NV4:G80 NV3_M2MF 003d dma NV4:GF100 DMA_IN_MEMORY -0042 ctx2d surf NV4:NV50 NV4_SURFACE_2D +0042 ctx2d surf NV4:G80 NV4_SURFACE_2D 0043 ctx2d rop NV4:G84 NV3_ROP 0044 ctx2d patt NV4:G84 NV4_PATTERN 0048 r3d d3d3 NV4:NV15 NV3_TEXTURED_TRIANGLE 004a r2d gdi NV4:G84 NV4_GDI 004b r2d gdi NV4:NV40 NV3_GDI -0052 ctx2d surf NV4:NV50 NV4_SURFACE_SWZ +0052 ctx2d surf NV4:G80 NV4_SURFACE_SWZ 0053 ctx3d surf NV4:NV20 NV4_SURFACE_3D 0054 r3d d3d5 NV4:NV20 NV4_TEXTURED_TRIANGLE 0055 r3d d3d6 NV4:NV20 NV4_MULTITEX_TRIANGLE 0056 uni3d celsius NV10:NV30 NV10_3D 0057 ctx2d chroma NV4:G84 NV4_CHROMA -0058 ctx2d surf NV4:NV50 NV3_SURFACE_DST -0059 ctx2d surf NV4:NV50 NV3_SURFACE_SRC -005a ctx3d surf NV4:NV50 NV3_SURFACE_COLOR -005b ctx3d surf NV4:NV50 NV3_SURFACE_ZETA -005c r2d lin NV4:NV50 NV4_LIN +0058 ctx2d surf NV4:G80 NV3_SURFACE_DST +0059 ctx2d surf NV4:G80 NV3_SURFACE_SRC +005a ctx3d surf NV4:G80 NV3_SURFACE_COLOR +005b ctx3d surf NV4:G80 NV3_SURFACE_ZETA +005c r2d lin NV4:G80 NV4_LIN 005d r2d tri NV4:G84 NV4_TRI 005e r2d rect NV4:NV40 NV4_RECT 005f r2d blit NV4:G84 NV4_BLIT -0060 r2d index NV4:NV50 NV4_INDEX -0061 r2d ifc NV4:NV50 NV4_IFC -0062 ctx2d surf NV10:NV50 NV10_SURFACE_2D -0063 r2d sifm NV10:NV50 NV5_SIFM +0060 r2d index NV4:G80 NV4_INDEX +0061 r2d ifc NV4:G80 NV4_IFC +0062 ctx2d surf NV10:G80 NV10_SURFACE_2D +0063 r2d sifm NV10:G80 NV5_SIFM 0064 op2d NV4:NV5 NV1_OP_SRCCOPY_AND -0064 r2d index NV5:NV50 NV5_INDEX +0064 r2d index NV5:G80 NV5_INDEX 0065 op2d NV4:NV5 NV3_OP_SRCCOPY -0065 r2d ifc NV5:NV50 NV5_IFC +0065 r2d ifc NV5:G80 NV5_IFC 0066 op2d NV4:NV5 NV4_OP_SRCCOPY_PREMULT -0066 r2d sifc NV5:NV50 NV5_SIFC +0066 r2d sifc NV5:G80 NV5_SIFC 0067 op2d NV4:NV5 NV4_OP_BLEND_PREMULT 0072 ctx2d beta4 NV4:G84 NV4_BETA4 -0076 r2d sifc NV4:NV50 NV4_SIFC -0077 r2d sifm NV4:NV50 NV4_SIFM -007b r2d tex NV10:NV50 NV10_TEXUPLOAD -0088 uni2d dvd NV10:NV50 NV10_DVD_SUBPICTURE +0076 r2d sifc NV4:G80 NV4_SIFC +0077 r2d sifm NV4:G80 NV4_SIFM +007b r2d tex NV10:G80 NV10_TEXUPLOAD +0088 uni2d dvd NV10:G80 NV10_DVD_SUBPICTURE 0089 r2d sifm NV10:NV40 NV10_SIFM -008a r2d ifc NV10:NV50 NV10_IFC +008a r2d ifc NV10:G80 NV10_IFC 0093 ctx3d surf NV10:NV20 NV10_SURFACE_3D 0094 r3d d3d5 NV10:NV20 NV10_TEXTURED_TRIANGLE 0095 r3d d3d6 NV10:NV20 NV10_MULTITEX_TRIANGLE @@ -164,8 +164,8 @@ Class Type Subtype GPUs Name 0097 uni3d kelvin NV20:NV34 NV20_3D 0098 uni3d celsius NV17:NV30 NV11_3D 0099 uni3d celsius NV17:NV20 NV17_3D -009e ctx2d surf NV10:NV50 NV20_SURFACE_SWZ [buggy on NV10] -009f r2d blit NV15:NV50 NV15_BLIT +009e ctx2d surf NV10:G80 NV20_SURFACE_SWZ [buggy on NV10] +009f r2d blit NV15:G80 NV15_BLIT 035c r2d lin NV30:NV40 NV30_LIN 0362 ctx2d surf NV30:NV40 NV30_SURFACE_2D 0364 r2d index NV30:NV40 NV30_INDEX @@ -179,21 +179,21 @@ Class Type Subtype GPUs Name 0597 uni3d kelvin NV25:NV40 NV25_3D 0697 uni3d rankine NV34:NV40 NV34_3D 305c r2d lin NV40:G84 NV30_LIN -3062 ctx2d surf NV40:NV50 NV30_SURFACE_2D +3062 ctx2d surf NV40:G80 NV30_SURFACE_2D 3064 r2d index NV40:G84 NV30_INDEX 3066 r2d sifc NV40:G84 NV30_SIFC 307b r2d tex NV40:G84 NV30_TEXUPLOAD -3089 r2d sifm NV40:NV50 NV30_SIFM +3089 r2d sifm NV40:G80 NV30_SIFM 308a r2d ifc NV40:G84 NV30_IFC -309e ctx2d surf NV40:NV50 NV30_SURFACE_SWZ +309e ctx2d surf NV40:G80 NV30_SURFACE_SWZ 4097 uni3d curie NV40:NV44 NV40_3D -4497 uni3d curie NV44:NV50 NV44_3D -502d uni2d gen NV50:GF100 NV50_2D -5039 mem m2mf NV50:GF100 NV50_M2MF -5062 ctx2d surf NV50:G84 NV50_SURFACE_2D -5089 r2d sifm NV50:G84 NV50_SIFM -5097 uni3d tesla NV50:G200 NV50_3D -50c0 comp tesla NV50:GF100 NV50_COMPUTE +4497 uni3d curie NV44:G80 NV44_3D +502d uni2d gen G80:GF100 G80_2D +5039 mem m2mf G80:GF100 G80_M2MF +5062 ctx2d surf G80:G84 G80_SURFACE_2D +5089 r2d sifm G80:G84 G80_SIFM +5097 uni3d tesla G80:G200 G80_3D +50c0 comp tesla G80:GF100 G80_COMPUTE 74c1 crypt G84:G98 G84_CRYPT 8297 uni3d tesla G84:G200 G84_3D 8397 uni3d tesla G200:GT215 G200_3D @@ -227,8 +227,8 @@ Class Type Subtype GPUs Name 0003 dma NV4:GF100 DMA_TO_MEMORY 003d dma NV4:GF100 DMA_IN_MEMORY ------- ------- ------- --------------- ---- -0039 mem m2mf NV4:NV50 NV3_M2MF -5039 mem m2mf NV50:GF100 NV50_M2MF +0039 mem m2mf NV4:G80 NV3_M2MF +5039 mem m2mf G80:GF100 G80_M2MF 9039 mem m2mf GF100:GK104 GF100_M2MF a040 mem p2mf GK104:GK110 GK104_P2MF a140 mem p2mf GK110:... GK110_P2MF @@ -245,30 +245,30 @@ a0b5 mem copy GK104:... GK104_COPY ------- ------- ------- --------------- ---- 0012 ctx2d beta NV4:G84 NV1_BETA 0072 ctx2d beta4 NV4:G84 NV4_BETA4 -0017 ctx2d chroma NV4:NV50 NV1_CHROMA +0017 ctx2d chroma NV4:G80 NV1_CHROMA 0057 ctx2d chroma NV4:G84 NV4_CHROMA -0018 ctx2d patt NV4:NV50 NV1_PATTERN +0018 ctx2d patt NV4:G80 NV1_PATTERN 0044 ctx2d patt NV4:G84 NV4_PATTERN 0019 ctx2d clip NV4:G84 NV1_CLIP 0043 ctx2d rop NV4:G84 NV3_ROP -0058 ctx2d surf NV4:NV50 NV3_SURFACE_DST -0059 ctx2d surf NV4:NV50 NV3_SURFACE_SRC -005a ctx3d surf NV4:NV50 NV3_SURFACE_COLOR -005b ctx3d surf NV4:NV50 NV3_SURFACE_ZETA -0052 ctx2d surf NV4:NV50 NV4_SURFACE_SWZ -009e ctx2d surf NV10:NV50 NV20_SURFACE_SWZ [buggy on NV10] +0058 ctx2d surf NV4:G80 NV3_SURFACE_DST +0059 ctx2d surf NV4:G80 NV3_SURFACE_SRC +005a ctx3d surf NV4:G80 NV3_SURFACE_COLOR +005b ctx3d surf NV4:G80 NV3_SURFACE_ZETA +0052 ctx2d surf NV4:G80 NV4_SURFACE_SWZ +009e ctx2d surf NV10:G80 NV20_SURFACE_SWZ [buggy on NV10] 039e ctx2d surf NV30:NV40 NV30_SURFACE_SWZ -309e ctx2d surf NV40:NV50 NV30_SURFACE_SWZ -0042 ctx2d surf NV4:NV50 NV4_SURFACE_2D -0062 ctx2d surf NV10:NV50 NV10_SURFACE_2D +309e ctx2d surf NV40:G80 NV30_SURFACE_SWZ +0042 ctx2d surf NV4:G80 NV4_SURFACE_2D +0062 ctx2d surf NV10:G80 NV10_SURFACE_2D 0362 ctx2d surf NV30:NV40 NV30_SURFACE_2D -3062 ctx2d surf NV40:NV50 NV30_SURFACE_2D -5062 ctx2d surf NV50:G84 NV50_SURFACE_2D +3062 ctx2d surf NV40:G80 NV30_SURFACE_2D +5062 ctx2d surf G80:G84 G80_SURFACE_2D 0053 ctx3d surf NV4:NV20 NV4_SURFACE_3D 0093 ctx3d surf NV10:NV20 NV10_SURFACE_3D ------- ------- ------- --------------- ---- 001c r2d lin NV4:NV40 NV1_LIN -005c r2d lin NV4:NV50 NV4_LIN +005c r2d lin NV4:G80 NV4_LIN 035c r2d lin NV30:NV40 NV30_LIN 305c r2d lin NV40:G84 NV30_LIN ------- ------- ------- --------------- ---- @@ -278,47 +278,47 @@ a0b5 mem copy GK104:... GK104_COPY 001e r2d rect NV4:NV40 NV1_RECT 005e r2d rect NV4:NV40 NV4_RECT ------- ------- ------- --------------- ---- -001f r2d blit NV4:NV50 NV1_BLIT +001f r2d blit NV4:G80 NV1_BLIT 005f r2d blit NV4:G84 NV4_BLIT -009f r2d blit NV15:NV50 NV15_BLIT +009f r2d blit NV15:G80 NV15_BLIT ------- ------- ------- --------------- ---- -0060 r2d index NV4:NV50 NV4_INDEX -0064 r2d index NV5:NV50 NV5_INDEX +0060 r2d index NV4:G80 NV4_INDEX +0064 r2d index NV5:G80 NV5_INDEX 0364 r2d index NV30:NV40 NV30_INDEX 3064 r2d index NV40:G84 NV30_INDEX ------- ------- ------- --------------- ---- 0021 r2d ifc NV4:NV40 NV1_IFC -0061 r2d ifc NV4:NV50 NV4_IFC -0065 r2d ifc NV5:NV50 NV5_IFC -008a r2d ifc NV10:NV50 NV10_IFC +0061 r2d ifc NV4:G80 NV4_IFC +0065 r2d ifc NV5:G80 NV5_IFC +008a r2d ifc NV10:G80 NV10_IFC 038a r2d ifc NV30:NV40 NV30_IFC 308a r2d ifc NV40:G84 NV30_IFC ------- ------- ------- --------------- ---- -0036 r2d sifc NV4:NV50 NV3_SIFC -0076 r2d sifc NV4:NV50 NV4_SIFC -0066 r2d sifc NV5:NV50 NV5_SIFC +0036 r2d sifc NV4:G80 NV3_SIFC +0076 r2d sifc NV4:G80 NV4_SIFC +0066 r2d sifc NV5:G80 NV5_SIFC 0366 r2d sifc NV30:NV40 NV30_SIFC 3066 r2d sifc NV40:G84 NV30_SIFC ------- ------- ------- --------------- ---- -0037 r2d sifm NV4:NV50 NV3_SIFM -0077 r2d sifm NV4:NV50 NV4_SIFM -0063 r2d sifm NV10:NV50 NV5_SIFM +0037 r2d sifm NV4:G80 NV3_SIFM +0077 r2d sifm NV4:G80 NV4_SIFM +0063 r2d sifm NV10:G80 NV5_SIFM 0089 r2d sifm NV10:NV40 NV10_SIFM 0389 r2d sifm NV30:NV40 NV30_SIFM -3089 r2d sifm NV40:NV50 NV30_SIFM -5089 r2d sifm NV50:G84 NV50_SIFM +3089 r2d sifm NV40:G80 NV30_SIFM +5089 r2d sifm G80:G84 G80_SIFM ------- ------- ------- --------------- ---- 004b r2d gdi NV4:NV40 NV3_GDI 004a r2d gdi NV4:G84 NV4_GDI ------- ------- ------- --------------- ---- -007b r2d tex NV10:NV50 NV10_TEXUPLOAD +007b r2d tex NV10:G80 NV10_TEXUPLOAD 037b r2d tex NV30:NV40 NV30_TEXUPLOAD 307b r2d tex NV40:G84 NV30_TEXUPLOAD ------- ------- ------- --------------- ---- -0038 uni2d dvd NV4:NV50 NV4_DVD_SUBPICTURE -0088 uni2d dvd NV10:NV50 NV10_DVD_SUBPICTURE +0038 uni2d dvd NV4:G80 NV4_DVD_SUBPICTURE +0088 uni2d dvd NV10:G80 NV10_DVD_SUBPICTURE ------- ------- ------- --------------- ---- -502d uni2d gen NV50:GF100 NV50_2D +502d uni2d gen G80:GF100 G80_2D 902d uni2d gen GF100:... GF100_2D ------- ------- ------- --------------- ---- 0048 r3d d3d3 NV4:NV15 NV3_TEXTURED_TRIANGLE @@ -342,9 +342,9 @@ a0b5 mem copy GK104:... GK104_COPY 0697 uni3d rankine NV34:NV40 NV34_3D ------- ------- ------- --------------- ---- 4097 uni3d curie NV40:NV44 NV40_3D -4497 uni3d curie NV44:NV50 NV44_3D +4497 uni3d curie NV44:G80 NV44_3D ------- ------- ------- --------------- ---- -5097 uni3d tesla NV50:G200 NV50_3D +5097 uni3d tesla G80:G200 G80_3D 8297 uni3d tesla G84:G200 G84_3D 8397 uni3d tesla G200:GT215 G200_3D 8597 uni3d tesla GT215:MCP89 GT215_3D @@ -357,7 +357,7 @@ a0b5 mem copy GK104:... GK104_COPY a097 uni3d kepler GK104:GK110 GK104_3D a197 uni3d kepler GK110:... GK110_3D ------- ------- ------- --------------- ---- -50c0 comp tesla NV50:GF100 NV50_COMPUTE +50c0 comp tesla G80:GF100 G80_COMPUTE 85c0 comp tesla GT215:GF100 GT215_COMPUTE ------- ------- ------- --------------- ---- 90c0 comp fermi GF100:GK104 GF100_COMPUTE diff --git a/docs/hw/fifo/dma-pusher.rst b/docs/hw/fifo/dma-pusher.rst index bf786e49..928e314b 100644 --- a/docs/hw/fifo/dma-pusher.rst +++ b/docs/hw/fifo/dma-pusher.rst @@ -22,7 +22,7 @@ converted directly to command stream, except when the "jump", "return", or disabled, and command stream is instead created with use of an "IB buffer". The IB buffer is a circular buffer of (base,length) pairs describing areas of pushbuffer that will be stitched together to create the command stream. NV4- -style mode is available on NV4:GF100, IB mode is available on NV50+. +style mode is available on NV4:GF100, IB mode is available on G80+. .. todo:: check for NV4-style mode on GF100 @@ -48,30 +48,30 @@ b3 dma_state.subc all Current subchannel b24 dma_state.mcnt all Current method count b32 dcount_shadow NV5: number of already-processed methods in cmd bool dma_state.ni NV10+ Current command's NI flag -bool dma_state.lenp NV50+ [#I]_ Large NI command length pending +bool dma_state.lenp G80+ [#I]_ Large NI command length pending b32 ref NV10+ reference counter [shared with puller] bool subr_active NV1A+ [#O]_ Subroutine active b32 subr_return NV1A+ [#O]_ subroutine return address bool big_endian NV11:G80 [#S]_ pushbuffer endian switch -bool sli_enable NV50+ [#S]_ SLI cond command enabled -b12 sli_mask NV50+ [#S]_ SLI cond mask +bool sli_enable G80+ [#S]_ SLI cond command enabled +b12 sli_mask G80+ [#S]_ SLI cond mask bool sli_active NV40+ SLI cond currently active -bool ib_enable NV50+ [#S]_ IB mode enabled -bool nonmain NV50+ [#I]_ non-main pushbuffer active -b8 dma_put_high NV50+ extra 8 bits for dma_put -b8 dma_put_high_rs NV50+ dma_put_high read shadow -b8 dma_put_high_ws NV50+ [#O]_ dma_put_high write shadow -b8 dma_get_high NV50+ extra 8 bits for dma_get -b8 dma_get_high_rs NV50+ dma_get_high read shadow -b32 ib_put NV50+ [#I]_ IB current end position -b32 ib_get NV50+ [#I]_ IB current read position -b40 ib_address NV50+ [#S]_ [#I]_ IB address -b8 ib_order NV50+ [#S]_ [#I]_ IB size -b32 dma_mget NV50+ [#I]_ main pushbuffer last read address -b8 dma_mget_high NV50+ [#I]_ extra 8 bits for dma_mget -bool dma_mget_val NV50+ [#I]_ dma_mget valid flag -b8 dma_mget_high_rs NV50+ [#I]_ dma_mget_high read shadow -bool dma_mget_val_rs NV50+ [#I]_ dma_mget_val read shadow +bool ib_enable G80+ [#S]_ IB mode enabled +bool nonmain G80+ [#I]_ non-main pushbuffer active +b8 dma_put_high G80+ extra 8 bits for dma_put +b8 dma_put_high_rs G80+ dma_put_high read shadow +b8 dma_put_high_ws G80+ [#O]_ dma_put_high write shadow +b8 dma_get_high G80+ extra 8 bits for dma_get +b8 dma_get_high_rs G80+ dma_get_high read shadow +b32 ib_put G80+ [#I]_ IB current end position +b32 ib_get G80+ [#I]_ IB current read position +b40 ib_address G80+ [#S]_ [#I]_ IB address +b8 ib_order G80+ [#S]_ [#I]_ IB size +b32 dma_mget G80+ [#I]_ main pushbuffer last read address +b8 dma_mget_high G80+ [#I]_ extra 8 bits for dma_mget +bool dma_mget_val G80+ [#I]_ dma_mget valid flag +b8 dma_mget_high_rs G80+ [#I]_ dma_mget_high read shadow +bool dma_mget_val_rs G80+ [#I]_ dma_mget_val read shadow ====== ================ ======== =========================================== .. [#S] means that this part of state can only be modified by kernel intervention @@ -137,7 +137,7 @@ addr R/W name description 0x8c R/W IB_PUT [#I]_ ib_put ==== === ============= ================================================= -The channel control area is accessed in 32-bit chunks, but on nv50+, DMA_GET, +The channel control area is accessed in 32-bit chunks, but on G80+, DMA_GET, DMA_PUT and DMA_MGET are effectively 40-bit quantities. To prevent races, the high parts of them have read and write shadows. When you read the address corresponding to the low part, the whole value is atomically read. The low @@ -162,7 +162,7 @@ areas: the old-style is in BAR0 at 0x800000 + 0x10000 * channel ID, supports channels 0-0x1f, can do both PIO and DMA submission, but does not have DMA_CGET when used in DMA mode. The new-style area is in BAR0 at 0xc0000 + 0x1000 * channel ID, supports only DMA mode, supports all channels, and has -DMA_CGET. On NV50 cards, channel 0 supports PIO mode and has channel control +DMA_CGET. On G80 cards, channel 0 supports PIO mode and has channel control area at 0x800000, while channels 1-126 support DMA mode and have channel control areas at 0xc00000 + 0x2000 * channel ID. On GF100, the channel control areas are accessed through selectable addresses in BAR1 and are backed by VRAM @@ -189,13 +189,13 @@ getting a VM fault when attempting to read from pushbuffer results in raising DMA_PUSHER error of type MEM_FAULT. On pre-NV1A cards, the word read from pushbuffer is always treated as -little-endian. On NV1A:NV50 cards, the endianness is determined by the -big_endian flag. On NV50+, the PFIFO endianness is a global switch. +little-endian. On NV1A:G80 cards, the endianness is determined by the +big_endian flag. On G80+, the PFIFO endianness is a global switch. .. todo:: What about GF100? Note that pushbuffer addresses over 0xffffffff shouldn't be used in NV4-style -mode, even on NV50 - they cannot be expressed in jump commands, dma_limit, nor +mode, even on G80 - they cannot be expressed in jump commands, dma_limit, nor subr_return. Why dma_put writing supports it is a mystery. The usual way to use NV4-style mode is: @@ -397,8 +397,8 @@ otherwise. The sli_enable flag determines if the command is available. If it's not set, the command effectively doesn't exist. Note that sli_enable and sli_mask exist -on both NV40:NV50 and NV50+, but on NV40:NV50 they have to be set uniformly -for all channels on the card, while NV50+ allows independent settings for each +on both NV40:G80 and G80+, but on NV40:G80 they have to be set uniformly +for all channels on the card, while G80+ allows independent settings for each channel. The XX bits in the command are ignored. @@ -455,7 +455,7 @@ The pusher pseudocode - pre-GF100 throw DMA_PUSHER(MEM_FAULT); if (gpu < NV1A) word = READ_DMAOBJ_32(dma_pushbuffer, dma_get, LE); - else if (gpu < NV50) + else if (gpu < G80) word = READ_DMAOBJ_32(dma_pushbuffer, dma_get, big_endian?BE:LE); else word = READ_DMAOBJ_32(dma_pushbuffer, dma_get, pfifo_endian); diff --git a/docs/hw/fifo/nv50-pfifo.rst b/docs/hw/fifo/g80-pfifo.rst index 54f50586..dbbea476 100644 --- a/docs/hw/fifo/nv50-pfifo.rst +++ b/docs/hw/fifo/g80-pfifo.rst @@ -1,4 +1,4 @@ -.. _nv50-pfifo: +.. _g80-pfifo: ================== Tesla PFIFO engine @@ -16,16 +16,16 @@ Introduction MMIO registers ============== -.. space:: 8 nv50-pfifo 0x2000 DMA FIFO submission to engines +.. space:: 8 g80-pfifo 0x2000 DMA FIFO submission to engines .. todo:: write me -.. space:: 8 nv50-pfifo-cache 0x1000 PFIFO cache data +.. space:: 8 g80-pfifo-cache 0x1000 PFIFO cache data .. todo:: write me -.. _nv50-pfifo-intr: +.. _g80-pfifo-intr: Interrupts ========== @@ -33,8 +33,8 @@ Interrupts .. todo:: write me -.. _nv50-pfifo-vm: -.. _nv50-pfifo-bg: +.. _g80-pfifo-vm: +.. _g80-pfifo-bg: VM engines ========== @@ -42,7 +42,7 @@ VM engines .. todo:: write me -.. _nv50-pfifo-chsw: +.. _g80-pfifo-chsw: Channel switching ================= @@ -55,10 +55,10 @@ FIFO submission area .. todo:: write me -.. space:: 8 nv50-pio-user 0x2000 PFIFO MMIO submission area +.. space:: 8 g80-pio-user 0x2000 PFIFO MMIO submission area .. todo:: document me -.. space:: 8 nv50-dma-user 0x2000 PFIFO DMA submission area +.. space:: 8 g80-dma-user 0x2000 PFIFO DMA submission area .. todo:: document me diff --git a/docs/hw/fifo/index.rst b/docs/hw/fifo/index.rst index 90a80075..47931065 100644 --- a/docs/hw/fifo/index.rst +++ b/docs/hw/fifo/index.rst @@ -13,7 +13,7 @@ Contents: classes nv1-pfifo nv4-pfifo - nv50-pfifo + g80-pfifo gf100-pfifo gf100-pspoon pcopy diff --git a/docs/hw/fifo/intro.rst b/docs/hw/fifo/intro.rst index 44d246ec..bb8d5f5c 100644 --- a/docs/hw/fifo/intro.rst +++ b/docs/hw/fifo/intro.rst @@ -77,7 +77,7 @@ Id Present on Name Description ===== =========== =========================== =================================================== This file deals only with the user-visible side of the PFIFO. For kernel-side -programming, see :ref:`nv1-pfifo`, :ref:`nv4-pfifo`, :ref:`nv50-pfifo`, +programming, see :ref:`nv1-pfifo`, :ref:`nv4-pfifo`, :ref:`g80-pfifo`, or :ref:`gf100-pfifo`. .. note:: GF100 information can still be very incomplete / not exactly true. @@ -98,7 +98,7 @@ The PFIFO can be split into roughly 4 pieces: A channel consists of the following: -- channel mode: PIO [NV1:GF100], DMA [NV4:GF100], or IB [NV50-] +- channel mode: PIO [NV1:GF100], DMA [NV4:GF100], or IB [G80-] - PFIFO :ref:`DMA pusher <fifo-dma-pusher>` state [DMA and IB channels only] - PFIFO CACHE state: the commands already accepted but not yet executed - PFIFO :ref:`puller <fifo-puller>` state @@ -106,12 +106,12 @@ A channel consists of the following: on PFIFO [not user-visible] - RAMHT [pre-GF100 only]: a table of "objects" that the channel can use. The objects are identified by arbitrary 32-bit handles, and can be DMA objects - [see :ref:`nv3-dmaobj`, :ref:`nv4-dmaobj`, :ref:`nv50-dmaobj`] or - engine objects [see :ref:`fifo-puller` and engine documentation]. On pre-NV50 + [see :ref:`nv3-dmaobj`, :ref:`nv4-dmaobj`, :ref:`g80-dmaobj`] or + engine objects [see :ref:`fifo-puller` and engine documentation]. On pre-G80 cards, individual objects can be shared between channels. -- vspace [NV50+ only]: A hierarchy of page tables that describes the virtual +- vspace [G80+ only]: A hierarchy of page tables that describes the virtual memory space visible to engines while executing commands for the channel. - Multiple channels can share a vspace. [see :ref:`nv50-vm`, + Multiple channels can share a vspace. [see :ref:`g80-vm`, :ref:`gf100-vm`] - engine-specific state @@ -120,10 +120,10 @@ mode is available on pre-GF100 cards, and involves poking the methods directly to the channel control area. It's slow and fragile - everything breaks down easily when more than one channel is used simultanously. Not recommended. See :ref:`fifo-pio` for details. On NV1:NV40, all channels support PIO mode. On -NV40:NV50, only first 32 channels support PIO mode. On NV50:GF100 only +NV40:G80, only first 32 channels support PIO mode. On G80:GF100 only channel 0 supports PIO mode. -.. todo:: check PIO channels support on NV40:NV50 +.. todo:: check PIO channels support on NV40:G80 NV1 PFIFO doesn't support any DMA mode. @@ -136,7 +136,7 @@ through the channel control area. Thus, commands can now be submitted by multiple applications simultaneously, without coordination with each other and without kernel's help. DMA mode is described in :ref:`fifo-dma-pusher`. -NV50 introduced IB mode. IB mode is a modified version of DMA mode that, +G80 introduced IB mode. IB mode is a modified version of DMA mode that, instead of following a single stream of commands from memory, has the ability to stitch together parts of multiple memory areas into a single command stream - allowing constructs that submit commands with parameters pulled directly from @@ -179,13 +179,13 @@ Method execution is described in detail in :ref:`DMA puller <fifo-puller>` and engine-specific documentation. Pre-NV1A, PFIFO treats everything as little-endian. NV1A introduced big-endian -mode, which affects pushbuffer/IB reads and semaphores. On NV1A:NV50 cards, -the endianness can be selected per channel via the big_endian flag. On NV50+ cards, +mode, which affects pushbuffer/IB reads and semaphores. On NV1A:G80 cards, +the endianness can be selected per channel via the big_endian flag. On G80+ cards, PFIFO endianness is a global switch. .. todo:: look for GF100 PFIFO endian switch The channel control area endianness is not affected by the big_endian flag or -NV50+ PFIFO endianness switch. Instead, it follows the PMC MMIO endianness switch. +G80+ PFIFO endianness switch. Instead, it follows the PMC MMIO endianness switch. .. todo:: is it still true for GF100, with VRAM-backed channel control area? diff --git a/docs/hw/fifo/nv4-pfifo.rst b/docs/hw/fifo/nv4-pfifo.rst index ff6c99b7..2918b540 100644 --- a/docs/hw/fifo/nv4-pfifo.rst +++ b/docs/hw/fifo/nv4-pfifo.rst @@ -1,8 +1,8 @@ .. _nv4-pfifo: -===================== -NV4:NV50 PFIFO engine -===================== +==================== +NV4:G80 PFIFO engine +==================== .. contents:: diff --git a/docs/hw/fifo/pcopy.rst b/docs/hw/fifo/pcopy.rst index f04ea025..9d7fd189 100644 --- a/docs/hw/fifo/pcopy.rst +++ b/docs/hw/fifo/pcopy.rst @@ -60,11 +60,11 @@ Core clock: cv0: NVCLK cv1: hub clock [Fermi clock #9] -NV50 VM engine: +Tesla VM engine: 0xd -NV50 VM client: +Tesla VM client: 0x13 -NV50 context DMA: +Tesla context DMA: 0xc Fermi VM engine: engine #0: 0x15 diff --git a/docs/hw/fifo/puller.rst b/docs/hw/fifo/puller.rst index 5a3c9867..b82e46cb 100644 --- a/docs/hw/fifo/puller.rst +++ b/docs/hw/fifo/puller.rst @@ -70,19 +70,19 @@ NV4:GF100 --------- Internally, a FIFO object is a [usually small] block of data residing in -"instance memory". The instance memory is RAMIN for pre-nv50 GPUs, and the -channel structure for nv50+ GPUs. The first few bits of a FIFO object +"instance memory". The instance memory is RAMIN for pre-G80 GPUs, and the +channel structure for G80+ GPUs. The first few bits of a FIFO object determine its 'class'. Class is 8 bits on NV4:NV25, 12 bits on NV25:NV40, 16 bits on NV40:GF100. The data associated with a handle in RAMHT consists of engine id, which determines the object's behavior when bound to a subchannel, and its address -in RAMIN [pre-NV50] or offset from channel structure start [NV50+]. +in RAMIN [pre-G80] or offset from channel structure start [G80+]. Apart from method 0, the engine id is ignored. The suitability of an object for a given method is determined by reading its class and checking if it makes sense. Most methods other than 0 expect a DMA object, although a couple -of pre-NV50 graph objects have methods that expect other graph objects. +of pre-G80 graph objects have methods that expect other graph objects. The following are commonly accepted object classes: @@ -94,7 +94,7 @@ The following are commonly accepted object classes: Other object classes are engine-specific. For more information on DMA objects, see :ref:`nv3-dmaobj`, -:ref:`nv4-dmaobj`, or :ref:`nv50-dmaobj`. +:ref:`nv4-dmaobj`, or :ref:`g80-dmaobj`. NV3 @@ -133,7 +133,7 @@ b32 acquire_timestamp NV1A+ semaphore acquire timestamp b32 acquire_value NV1A+ semaphore acquire value dmaobj dma_semaphore NV11:GF100 semaphore DMA object b12/16 semaphore_offset NV11:GF100 old-style semaphore address -bool semaphore_off_val NV50:GF100 semaphore_offset valid +bool semaphore_off_val G80:GF100 semaphore_offset valid b40 semaphore_address G84+ new-style semaphore address b32 semaphore_sequence G84+ new-style semaphore value bool acquire_source G84:GF100 semaphore acquire address selection @@ -350,7 +350,7 @@ are supported by G84+ GPUs. The differences are: Old-style semaphores -- limitted addressing range: 12-bit [NV1A:NV50] or 16-bit [NV50:GF100] offset +- limitted addressing range: 12-bit [NV1A:G80] or 16-bit [G80:GF100] offset in a DMA object. Thus a special DMA object is required. - release writes a single word - acquire supports only "wait for value equal to X" mode @@ -363,18 +363,18 @@ New-style semaphores or equal X" modes Semaphores have to be 4-byte aligned. All values are stored with endianness -selected by big_endian flag [NV1A:NV50] or by PFIFO endianness [NV50+] +selected by big_endian flag [NV1A:G80] or by PFIFO endianness [G80+] On pre-GF100, both old-style semaphores and new-style semaphores use the DMA object stored in dma_semaphore, which can be set through DMA_SEMAPHORE method. -Note that this method is buggy on pre-NV50 GPUs and accepts only *write-only* +Note that this method is buggy on pre-G80 GPUs and accepts only *write-only* DMA objects of class 0x0002. You have to work around the bug by preparing such DMA objects [or using a kernel that intercepts the error and does the binding manually]. Old-style semaphores read/write the location specified in semaphore_offset, which can be set by SEMAPHORE_OFFSET method. The offset has to be divisible -by 4 and fit in 12 bits [NV1A:NV50] or 16 bits [NV50:GF100]. An acquire is +by 4 and fit in 12 bits [NV1A:G80] or 16 bits [G80:GF100]. An acquire is triggered by using the SEMAPHORE_ACQUIRE mthd with the expected value as the parameter - further command processing will halt until the memory location contains the selected value. A release is triggered by using the @@ -407,12 +407,12 @@ waits for a value that, ANDed with semaphore_sequence, gives a non-0 result Failures of semaphore-related methods will trigger the SEMAPHORE error. The SEMAPHORE error has several subtypes, depending on card generation. -NV1A:NV50 SEMAPHORE error subtypes: +NV1A:G80 SEMAPHORE error subtypes: - 1: INVALID_OPERAND: wrong parameter to a method - 2: INVALID_STATE: attempt to acquire/release without proper setup -NV50:GF100 SEMAPHORE error subtypes: +G80:GF100 SEMAPHORE error subtypes: - 1: ADDRESS_UNALIGNED: address not divisible by 4 - 2: INVALID_STATE: attempt to acquire/release without proper setup @@ -436,7 +436,7 @@ mthd 0x0060 / 0x018: DMA_SEMAPHORE [O] [NV1A:GF100] :: obj = RAMHT_LOOKUP(param).addr; - if (gpu < NV50) { + if (gpu < G80) { if (OBJECT_CLASS(obj) != 2) throw SEMAPHORE(INVALID_OPERAND); if (DMAOBJ_RIGHTS(obj) != WO) @@ -444,15 +444,15 @@ mthd 0x0060 / 0x018: DMA_SEMAPHORE [O] [NV1A:GF100] if (!DMAOBJ_PT_PRESENT(obj)) throw SEMAPHORE(INVALID_OPERAND); } - /* NV50 doesn't bother with verification */ + /* G80 doesn't bother with verification */ dma_semaphore = obj; -.. todo:: is there ANY way to make NV50 reject non-DMA object classes? +.. todo:: is there ANY way to make G80 reject non-DMA object classes? mthd 0x0064 / 0x019: SEMAPHORE_OFFSET [NV1A-] :: - if (gpu < NV50) { + if (gpu < G80) { if (param & ~0xffc) throw SEMAPHORE(INVALID_OPERAND); semaphore_offset = param; @@ -470,13 +470,13 @@ mthd 0x0064 / 0x019: SEMAPHORE_OFFSET [NV1A-] mthd 0x0068 / 0x01a: SEMAPHORE_ACQUIRE [NV1A-] :: - if (gpu < NV50 && !dma_semaphore) + if (gpu < G80 && !dma_semaphore) /* unbound DMA object */ throw SEMAPHORE(INVALID_STATE); - if (gpu >= NV50 && !semaphore_off_val) + if (gpu >= G80 && !semaphore_off_val) throw SEMAPHORE(INVALID_STATE); b32 word; - if (gpu < NV50) { + if (gpu < G80) { word = READ_DMAOBJ_32(dma_semaphore, semaphore_offset, big_endian?BE:LE); } else { try { @@ -493,7 +493,7 @@ mthd 0x0068 / 0x01a: SEMAPHORE_ACQUIRE [NV1A-] acquire_value = param; acquire_timestamp = ???; /* XXX: figure out timestamp/timeout business */ - if (gpu >= NV50) { + if (gpu >= G80) { acquire_mode = 0; acquire_source = 0; } @@ -502,12 +502,12 @@ mthd 0x0068 / 0x01a: SEMAPHORE_ACQUIRE [NV1A-] mthd 0x006c / 0x01b: SEMAPHORE_RELEASE [NV1A-] :: - if (gpu < NV50 && !dma_semaphore) + if (gpu < G80 && !dma_semaphore) /* unbound DMA object */ throw SEMAPHORE(INVALID_STATE); - if (gpu >= NV50 && !semaphore_off_val) + if (gpu >= G80 && !semaphore_off_val) throw SEMAPHORE(INVALID_STATE); - if (gpu < NV50) { + if (gpu < G80) { WRITE_DMAOBJ_32(dma_semaphore, semaphore_offset, param, big_endian?BE:LE); } else { try { @@ -620,7 +620,7 @@ mthd 0x0020 / 0x008: NOTIFY_INTR [G84:] .. todo:: check how this is reported on GF100 The G84+ WRCACHE_FLUSH method can be used to flush PFIFO's write post caches. -[see :ref:`nv50-vm`] +[see :ref:`g80-vm`] mthd 0x0024 / 0x009: WRCACHE_FLUSH [G84:] :: diff --git a/docs/hw/gpu.rst b/docs/hw/gpu.rst index 85e95e73..ddd9c49f 100644 --- a/docs/hw/gpu.rst +++ b/docs/hw/gpu.rst @@ -89,7 +89,7 @@ is: - Tesla family: - - NV50 subfamily: NV50 + - G80 subfamily: G80 - G84 subfamily: G84, G86, G92, G94, G96, G98 - G200 subfamily: G200, MCP77, MCP79 - GT215 subfamily: GT215, GT216, GT218, MCP89 @@ -120,7 +120,7 @@ The GPU has integrated audio output, MIDI synthetiser and Sega Saturn game controller port. Its rendering pipeline, as opposed to all later families, deals with quadratic surfaces, as opposed to triangles. Its video output circuitry is also totally different from NV3+, and replaces the VGA part as -opposed to extending it like NV3:NV50 do. +opposed to extending it like NV3:G80 do. There's also NV2, which has even more legendary status. It was supposed to be another card based on quadratic surfaces, but it got stuck in development hell @@ -405,7 +405,7 @@ Curie family ------------ This family was the first to feature PCIE cards, and many fundamental areas -got significant changes, which later paved the way for NV50. It is also the +got significant changes, which later paved the way for G80. It is also the family where GPU ids started to diverge from nvidia code names. The changes: - NV40: @@ -493,9 +493,9 @@ Tesla family ------------ The card where they redesigned everything. The most significant change was the -redesigned memory subsystem, complete with a paging MMU [see :ref:`nv50-vm`]. +redesigned memory subsystem, complete with a paging MMU [see :ref:`g80-vm`]. -- NV50: +- G80: - a new VM subsystem, complete with redesigned DMA objects - RAMIN is gone, all structures can be placed arbitrarily in VRAM, and @@ -561,7 +561,7 @@ The GPUs in this family are: core hda id name TPCs MPs/TPC PARTs date notes pciid pciid ===== ===== ==== =========== ==== ======= ===== ========== ====== -019X \- NV50 G80 8 2 6 08.11.2006 +019X \- 0x50 G80 8 2 6 08.11.2006 040X \- 0x84 G84 2 2 2 17.04.2007 042X \- 0x86 G86 1 2 2 17.04.2007 060X+ \- 0x92 G92 8 2 4 29.10.2007 diff --git a/docs/hw/graph/2d/ctxobj.rst b/docs/hw/graph/2d/ctxobj.rst index 3441043a..e5dcd103 100644 --- a/docs/hw/graph/2d/ctxobj.rst +++ b/docs/hw/graph/2d/ctxobj.rst @@ -26,7 +26,7 @@ The methods are: 0100 NOP [NV4-] 0104 NOTIFY -0110 WAIT_FOR_IDLE [NV50-] +0110 WAIT_FOR_IDLE [G80-] 0140 PM_TRIGGER [NV40-?] [XXX] 0180 N DMA_NOTIFY [NV4-] 0200 O PATCH_BETA_OUTPUT [NV4:NV20] @@ -64,7 +64,7 @@ The methods are: 0100 NOP [NV4-] 0104 NOTIFY -0110 WAIT_FOR_IDLE [NV50-] +0110 WAIT_FOR_IDLE [G80-] 0140 PM_TRIGGER [NV40-?] [XXX] 0180 N DMA_NOTIFY [NV4-] 0200 O PATCH_ROP_OUTPUT [NV4:NV20] @@ -94,7 +94,7 @@ color key is only used when enabled in options for a given graph object. The objects in this family are: - objtype 0x03: NV1_CHROMA [NV1:NV4] -- class 0x0017: NV1_CHROMA [NV4:NV50] +- class 0x0017: NV1_CHROMA [NV4:G80] - class 0x0057: NV4_CHROMA [NV4:G84] The PLANE object family deals with setting the color for plane masking. The @@ -110,7 +110,7 @@ The methods for these families are: 0100 NOP [NV4-] 0104 NOTIFY -0110 WAIT_FOR_IDLE [NV50-] +0110 WAIT_FOR_IDLE [G80-] 0140 PM_TRIGGER [NV40-?] [XXX] 0180 N DMA_NOTIFY [NV4-] 0200 O PATCH_IMAGE_OUTPUT [NV4:NV20] @@ -159,7 +159,7 @@ The methods for this family are: 0100 NOP [NV4-] 0104 NOTIFY -0110 WAIT_FOR_IDLE [NV50-] +0110 WAIT_FOR_IDLE [G80-] 0140 PM_TRIGGER [NV40-?] [XXX] 0180 N DMA_NOTIFY [NV4-] 0200 O PATCH_IMAGE_OUTPUT [NV4:NV20] @@ -224,7 +224,7 @@ The methods are: 0100 NOP [NV4-] 0104 NOTIFY -0110 WAIT_FOR_IDLE [NV50-] +0110 WAIT_FOR_IDLE [G80-] 0140 PM_TRIGGER [NV40-?] [XXX] 0180 N DMA_NOTIFY [NV4-] 0200 O PATCH_BETA_OUTPUT [NV4:NV20] diff --git a/docs/hw/graph/2d/intro.rst b/docs/hw/graph/2d/intro.rst index 88b91d1c..83ba2b52 100644 --- a/docs/hw/graph/2d/intro.rst +++ b/docs/hw/graph/2d/intro.rst @@ -16,7 +16,7 @@ The 2d engine is rather orthogonal and has the following features: - solid color shapes (points, lines, triangles, rectangles) - pixels uploaded directly through command stream, raw or expanded using a palette - - text with in-memory fonts [NV3:NV50] + - text with in-memory fonts [NV3:G80] - rectangles blitted from another area of video memory - pixels read by DMA - linearly and quadratically textured quads [NV1:NV3] @@ -44,7 +44,7 @@ The objects The 2d engine is controlled by the user via PGRAPH objects. On NV1:G84, each piece of 2d functionality has its own object class - a matching set of objects -needs to be used together to perform an operation. NV50+ have a unified 2d +needs to be used together to perform an operation. G80+ have a unified 2d engine object that can be used to control all of the 2d pipeline in one place. The non-unified objects can be divided into 3 classes: @@ -461,14 +461,14 @@ Unified 2d objects .. todo:: write me 0100 NOP [graph/intro.txt] -0104 NOTIFY [NV50_2D] [graph/intro.txt] +0104 NOTIFY [G80_2D] [graph/intro.txt] [XXX: GF100 methods] 0110 WAIT_FOR_IDLE [graph/intro.txt] 0140 PM_TRIGGER [graph/intro.txt] -0180 DMA_NOTIFY [NV50_2D] [graph/intro.txt] -0184 DMA_SRC [NV50_2D] [XXX] -0188 DMA_DST [NV50_2D] [XXX] -018c DMA_COND [NV50_2D] [XXX] +0180 DMA_NOTIFY [G80_2D] [graph/intro.txt] +0184 DMA_SRC [G80_2D] [XXX] +0188 DMA_DST [G80_2D] [XXX] +018c DMA_COND [G80_2D] [XXX] [XXX: 0200-02ac] 02b0 PATTERN_OFFSET [graph/pattern.txt] 02b4 PATTERN_SELECT [graph/pattern.txt] diff --git a/docs/hw/graph/2d/pattern.rst b/docs/hw/graph/2d/pattern.rst index a26dd0b7..bab03559 100644 --- a/docs/hw/graph/2d/pattern.rst +++ b/docs/hw/graph/2d/pattern.rst @@ -18,7 +18,7 @@ the blending operation is the pattern. A pattern is an infinitely repeating - color pattern: an aribtrary 8x8 R8G8B8 image [NV4-] The pattern can be set through the NV1-style \*_PATTERN context objects, or -through the NV50-style unified 2d objects. For details on how and when the +through the G80-style unified 2d objects. For details on how and when the pattern is used, see :ref:`graph-2d-pattern`. The graph context used for pattern storage is made of: @@ -29,16 +29,16 @@ The graph context used for pattern storage is made of: - shape selection: 8x8, 1x64, or 64x1 - the bitmap: 2 32-bit words - 2 colors: A8R10G10B10 format [NV1:NV4] - - 2 colors: 32-bit word + format selector each [NV4:NV50] - - 2 colors: 32-bit word each [NV50-] - - color format selection [NV50-] - - bitmap format selection [NV50-] + - 2 colors: 32-bit word + format selector each [NV4:G80] + - 2 colors: 32-bit word each [G80-] + - color format selection [G80-] + - bitmap format selection [G80-] - color pattern state [NV4-]: - 64 colors: R8G8B8 format -- pattern offset: 2 6-bit numbers [NV50-] +- pattern offset: 2 6-bit numbers [G80-] .. _obj-pattern: @@ -50,14 +50,14 @@ The PATTERN object family deals with setting up the pattern. The objects in this family are: - objtype 0x06: NV1_PATTERN [NV1:NV4] -- class 0x0018: NV1_PATTERN [NV4:NV50] +- class 0x0018: NV1_PATTERN [NV4:G80] - class 0x0044: NV4_PATTERN [NV4:G84] The methods for this family are: 0100 NOP [NV4-] [graph/intro.txt] 0104 NOTIFY [graph/intro.txt] -0110 WAIT_FOR_IDLE [NV50-] [graph/intro.txt] +0110 WAIT_FOR_IDLE [G80-] [graph/intro.txt] 0140 PM_TRIGGER [NV40-?] [XXX] [graph/intro.txt] 0180 N DMA_NOTIFY [NV4-] [graph/intro.txt] 0200 O PATCH_IMAGE_OUTPUT [NV4:NV20] [see below] @@ -89,7 +89,7 @@ mthd 0x030c: TYPE [NV4_PATTERN] 1: BITMAP 2: COLOR Operation:: - if (NV4:NV50) { + if (NV4:G80) { PATTERN_TYPE = param; } else { SHADOW_COMP2D.PATTERN_TYPE = param; @@ -108,7 +108,7 @@ mthd 0x308: BITMAP_SHAPE [\*_PATTERN] Operation:: if (param > 2) throw(INVALID_ENUM); - if (NV1:NV50) { + if (NV1:G80) { PATTERN_BITMAP_SHAPE = param; } else { SHADOW_COMP2D.PATTERN_BITMAP_SHAPE = param; @@ -138,8 +138,8 @@ Pattern coordinates =================== The pattern pixel is selected according to pattern coordinates: px, py. On -NV1:NV50, the pattern coordinates are equal to absolute [ie. not -canvas-relative] coordinates in the destination surface. On NV50+, an offset +NV1:G80, the pattern coordinates are equal to absolute [ie. not +canvas-relative] coordinates in the destination surface. On G80+, an offset can be added to the coordinates. The offset is set by the PATTERN_OFFSET method: @@ -177,14 +177,14 @@ The color to use for given pattern coordinates is selected as follows:: color = PATTERN_BITMAP_COLOR[pixel]; On NV1:NV4, the color is internally stored in A8R10G10B10 format and -upconverted from the source format when submitted. On NV4:NV50, it's stored +upconverted from the source format when submitted. On NV4:G80, it's stored in the original format it was submitted with, and is annotated with the format -information as of the submission. On NV50+, it's also stored as it was +information as of the submission. On G80+, it's also stored as it was submitted, but is not annotated with format information - the format used to interpret it is the most recent pattern color format submitted. -On NV1:NV50, the color and bitmap formats are stored in graph options for the -PATTERN object. On NV50+, they're part of main graph state instead. +On NV1:G80, the color and bitmap formats are stored in graph options for the +PATTERN object. On G80+, they're part of main graph state instead. The methods dealing with bitmap patterns are: @@ -224,7 +224,7 @@ Operation:: } } -mthd 0x2e8: PATTERN_COLOR_FORMAT [NV50_2D] +mthd 0x2e8: PATTERN_COLOR_FORMAT [G80_2D] Sets the color format used for bitmap pattern colors. One of: 0: A16R5G6B5 1: X16A1R5G5B5 @@ -243,7 +243,7 @@ mthd 0x304: BITMAP_FORMAT [\*_PATTERN] [NV4-] 1: LE 2: CGA6 Operation:: - if (NV4:NV50) { + if (NV4:G80) { switch (param) { case 1: cur_grobj.bitmap_format = LE; break; case 2: cur_grobj.bitmap_format = CGA6; break; @@ -277,7 +277,7 @@ Operation:: PATTERN_BITMAP_COLOR[i].G = get_color_b10(cur_grobj, param); PATTERN_BITMAP_COLOR[i].R = get_color_b10(cur_grobj, param); PATTERN_BITMAP_COLOR[i].A = get_color_b8(cur_grobj, param); - } else if (NV4:NV50) { + } else if (NV4:G80) { PATTERN_BITMAP_COLOR[i] = param; /* XXX: details */ CONTEXT_FORMAT.PATTERN_BITMAP_COLOR[i] = cur_grobj.color_format; @@ -290,7 +290,7 @@ mthd 0x2f8+i*4, i<2: PATTERN_BITMAP [\*_2D] Sets the pattern bitmap. i=0 sets bits 0-31, i=1 sets bits 32-63. Operation:: tmp = param; - if (cur_grobj.BITMAP_FORMAT == CGA6 && NV1:NV50) { /* XXX: check if also NV4+ */ + if (cur_grobj.BITMAP_FORMAT == CGA6 && NV1:G80) { /* XXX: check if also NV4+ */ /* pattern stored internally in LE format - for CGA6, reverse bits in all bytes */ tmp = (tmp & 0xaaaaaaaa) >> 1 | (tmp & 0x55555555) << 1; diff --git a/docs/hw/graph/2d/solid.rst b/docs/hw/graph/2d/solid.rst index 2a20019b..33102107 100644 --- a/docs/hw/graph/2d/solid.rst +++ b/docs/hw/graph/2d/solid.rst @@ -12,7 +12,7 @@ One of 2d engine functions is drawing solid [single-color] primitives. The solid drawing functions use the usual 2D pipeline as described in graph/2d.txt and are available on all cards. The primitives supported are: -- points [NV1:NV4 and NV50+] +- points [NV1:NV4 and G80+] - lines [NV1:NV4] - lins [half-open lines] - triangles @@ -22,7 +22,7 @@ The 2d engine is limitted to integer vertex coordinates [ie. all primitive vertices must lie in pixel centres]. On NV1:G84 cards, the solid drawing functions are exposed via separate -source object types for each type of primitive. On NV50+, all solid drawing +source object types for each type of primitive. On G80+, all solid drawing functionality is exposed via the unified 2d object. @@ -30,7 +30,7 @@ Source objects ============== Each supported primitive type has its own source object class family on -NV1:NV50. These families are: +NV1:G80. These families are: - POINT [NV1:NV4] - LINE [NV1:NV4] @@ -47,7 +47,7 @@ The common methods accepted by all solid source objects are: 0100 NOP [NV4-] [graph/intro.txt] 0104 NOTIFY [graph/intro.txt] 010c PATCH [NV4:?] [graph/2d.txt] -0110 WAIT_FOR_IDLE [NV50-] [graph/intro.txt] +0110 WAIT_FOR_IDLE [G80-] [graph/intro.txt] 0140 PM_TRIGGER [NV40-?] [graph/intro.txt] 0180 N DMA_NOTIFY [NV4-] [graph/intro.txt] 0184 N NV1_CLIP [NV5-] [graph/2d.txt] @@ -103,7 +103,7 @@ The LINE/LIN object families draw lines/lins, respectively. The objects are: - objtype 0x09: NV1_LINE [NV1:NV4] - objtype 0x0a: NV1_LIN [NV1:NV4] - class 0x001c: NV1_LIN [NV4:NV40] -- class 0x005c: NV4_LIN [NV4:NV50] +- class 0x005c: NV4_LIN [NV4:G80] - class 0x035c: NV30_LIN [NV30:NV40] - class 0x305c: NV30_LIN [NV40:G84] diff --git a/docs/hw/graph/intro.rst b/docs/hw/graph/intro.rst index daf1977d..aea27041 100644 --- a/docs/hw/graph/intro.rst +++ b/docs/hw/graph/intro.rst @@ -93,9 +93,9 @@ Memory to memory copy objects: ====== =========== ========== ============ class variants name description ====== =========== ========== ============ -0x0039 NV4:NV50 NV3_M2MF :ref:`copies data from one buffer to another <obj-m2mf>` -0x5039 NV50:GF100 NV50_M2MF :ref:`copies data from one buffer to another <obj-m2mf>` -0x9039 GF100:GK104 GF100_M2MF :ref:`copies data from one buffer to another <obj-m2mf>` +0x0039 NV4:G80 NV3_M2MF :ref:`copies data from one buffer to another <obj-m2mf>` +0x5039 G80:GF100 G80_M2MF :ref:`copies data from one buffer to another <obj-m2mf>` +0x9039 GF100:GK104 GF100_M2MF :ref:`copies data from one buffer to another <obj-m2mf>` 0xa040 GK104:GK110 GK104_P2MF :ref:`copies data from FIFO to memory buffer <obj-p2mf>` 0xa140 GK110: GK110_P2MF :ref:`copies data from FIFO to memory buffer <obj-p2mf>` ====== =========== ========== ============ @@ -106,26 +106,26 @@ Context objects: class variants name description ====== ========= =============== ============ 0x0012 NV4:G84 NV1_BETA :ref:`sets beta factor for blending <obj-beta>` -0x0017 NV4:NV50 NV1_CHROMA :ref:`sets color for color key <obj-chroma>` +0x0017 NV4:G80 NV1_CHROMA :ref:`sets color for color key <obj-chroma>` 0x0057 NV4:G84 NV4_CHROMA :ref:`sets color for color key <obj-chroma>` -0x0018 NV4:NV50 NV1_PATTERN :ref:`sets pattern for raster op <obj-pattern>` +0x0018 NV4:G80 NV1_PATTERN :ref:`sets pattern for raster op <obj-pattern>` 0x0044 NV4:G84 NV1_PATTERN :ref:`sets pattern for raster op <obj-pattern>` 0x0019 NV4:G84 NV1_CLIP :ref:`sets user clipping rectangle <obj-clip>` 0x0043 NV4:G84 NV1_ROP :ref:`sets raster operation <obj-rop>` 0x0072 NV4:G84 NV4_BETA4 :ref:`sets component beta factors for pre-multiplied blending <obj-beta4>` -0x0058 NV4:NV50 NV3_SURF_DST :ref:`sets the 2d destination surface <obj-surf>` -0x0059 NV4:NV50 NV3_SURF_SRC :ref:`sets the 2d blit source surface <obj-surf>` -0x005a NV4:NV50 NV3_SURF_COLOR :ref:`sets the 3d color surface <obj-surf>` -0x005b NV4:NV50 NV3_SURF_ZETA :ref:`sets the 3d zeta surface <obj-surf>` -0x0052 NV4:NV50 NV4_SWZSURF :ref:`sets 2d swizzled destination surface <obj-swzsurf>` -0x009e NV10:NV50 NV10_SWZSURF :ref:`sets 2d swizzled destination surface <obj-swzsurf>` +0x0058 NV4:G80 NV3_SURF_DST :ref:`sets the 2d destination surface <obj-surf>` +0x0059 NV4:G80 NV3_SURF_SRC :ref:`sets the 2d blit source surface <obj-surf>` +0x005a NV4:G80 NV3_SURF_COLOR :ref:`sets the 3d color surface <obj-surf>` +0x005b NV4:G80 NV3_SURF_ZETA :ref:`sets the 3d zeta surface <obj-surf>` +0x0052 NV4:G80 NV4_SWZSURF :ref:`sets 2d swizzled destination surface <obj-swzsurf>` +0x009e NV10:G80 NV10_SWZSURF :ref:`sets 2d swizzled destination surface <obj-swzsurf>` 0x039e NV30:NV40 NV30_SWZSURF :ref:`sets 2d swizzled destination surface <obj-swzsurf>` -0x309e NV40:NV50 NV30_SWZSURF :ref:`sets 2d swizzled destination surface <obj-swzsurf>` -0x0042 NV4:NV50 NV4_SURF2D :ref:`sets 2d destination and source surfaces <obj-surf2d>` -0x0062 NV10:NV50 NV10_SURF2D :ref:`sets 2d destination and source surfaces <obj-surf2d>` +0x309e NV40:G80 NV30_SWZSURF :ref:`sets 2d swizzled destination surface <obj-swzsurf>` +0x0042 NV4:G80 NV4_SURF2D :ref:`sets 2d destination and source surfaces <obj-surf2d>` +0x0062 NV10:G80 NV10_SURF2D :ref:`sets 2d destination and source surfaces <obj-surf2d>` 0x0362 NV30:NV40 NV30_SURF2D :ref:`sets 2d destination and source surfaces <obj-surf2d>` -0x3062 NV40:NV50 NV30_SURF2D :ref:`sets 2d destination and source surfaces <obj-surf2d>` -0x5062 NV50:G84 NV50_SURF2D :ref:`sets 2d destination and source surfaces <obj-surf2d>` +0x3062 NV40:G80 NV30_SURF2D :ref:`sets 2d destination and source surfaces <obj-surf2d>` +0x5062 G80:G84 G80_SURF2D :ref:`sets 2d destination and source surfaces <obj-surf2d>` 0x0053 NV4:NV20 NV4_SURF3D :ref:`sets 3d color and zeta surfaces <obj-surf3d>` 0x0093 NV10:NV20 NV10_SURF3D :ref:`sets 3d color and zeta surfaces <obj-surf3d>` ====== ========= =============== ============ @@ -136,7 +136,7 @@ Solids rendering objects: class variants name description ====== ========= ========= ============ 0x001c NV4:NV40 NV1_LIN :ref:`renders a lin <obj-lin>` -0x005c NV4:NV50 NV4_LIN :ref:`renders a lin <obj-lin>` +0x005c NV4:G80 NV4_LIN :ref:`renders a lin <obj-lin>` 0x035c NV30:NV40 NV30_LIN :ref:`renders a lin <obj-lin>` 0x305c NV40:G84 NV30_LIN :ref:`renders a lin <obj-lin>` 0x001d NV4:NV40 NV1_TRI :ref:`renders a triangle <obj-tri>` @@ -151,23 +151,23 @@ Image upload from CPU objects: class variants name description ====== ========= ============ ============ 0x0021 NV4:NV40 NV1_IFC :ref:`image from CPU <obj-ifc>` -0x0061 NV4:NV50 NV4_IFC :ref:`image from CPU <obj-ifc>` -0x0065 NV5:NV50 NV5_IFC :ref:`image from CPU <obj-ifc>` -0x008a NV10:NV50 NV10_IFC :ref:`image from CPU <obj-ifc>` +0x0061 NV4:G80 NV4_IFC :ref:`image from CPU <obj-ifc>` +0x0065 NV5:G80 NV5_IFC :ref:`image from CPU <obj-ifc>` +0x008a NV10:G80 NV10_IFC :ref:`image from CPU <obj-ifc>` 0x038a NV30:NV40 NV30_IFC :ref:`image from CPU <obj-ifc>` 0x308a NV40:G84 NV40_IFC :ref:`image from CPU <obj-ifc>` -0x0036 NV4:NV50 NV1_SIFC :ref:`stretched image from CPU <obj-sifc>` -0x0076 NV4:NV50 NV4_SIFC :ref:`stretched image from CPU <obj-sifc>` -0x0066 NV5:NV50 NV5_SIFC :ref:`stretched image from CPU <obj-sifc>` +0x0036 NV4:G80 NV1_SIFC :ref:`stretched image from CPU <obj-sifc>` +0x0076 NV4:G80 NV4_SIFC :ref:`stretched image from CPU <obj-sifc>` +0x0066 NV5:G80 NV5_SIFC :ref:`stretched image from CPU <obj-sifc>` 0x0366 NV30:NV40 NV30_SIFC :ref:`stretched image from CPU <obj-sifc>` 0x3066 NV40:G84 NV40_SIFC :ref:`stretched image from CPU <obj-sifc>` -0x0060 NV4:NV50 NV4_INDEX :ref:`indexed image from CPU <obj-index>` -0x0064 NV5:NV50 NV5_INDEX :ref:`indexed image from CPU <obj-index>` +0x0060 NV4:G80 NV4_INDEX :ref:`indexed image from CPU <obj-index>` +0x0064 NV5:G80 NV5_INDEX :ref:`indexed image from CPU <obj-index>` 0x0364 NV30:NV40 NV30_INDEX :ref:`indexed image from CPU <obj-index>` 0x3064 NV40:G84 NV40_INDEX :ref:`indexed image from CPU <obj-index>` -0x007b NV10:NV50 NV10_TEXTURE :ref:`texture from CPU <obj-texture>` +0x007b NV10:G80 NV10_TEXTURE :ref:`texture from CPU <obj-texture>` 0x037b NV30:NV40 NV30_TEXTURE :ref:`texture from CPU <obj-texture>` -0x307b NV40:NV50 NV40_TEXTURE :ref:`texture from CPU <obj-texture>` +0x307b NV40:G80 NV40_TEXTURE :ref:`texture from CPU <obj-texture>` ====== ========= ============ ============ .. todo:: figure out wtf is the deal with TEXTURE objects @@ -177,18 +177,18 @@ Other 2d source objects: ====== ========= ========= ============ class variants name description ====== ========= ========= ============ -0x001f NV4:NV50 NV1_BLIT :ref:`blits inside framebuffer <obj-blit>` +0x001f NV4:G80 NV1_BLIT :ref:`blits inside framebuffer <obj-blit>` 0x005f NV4:G84 NV4_BLIT :ref:`blits inside framebuffer <obj-blit>` -0x009f NV15:NV50 NV15_BLIT :ref:`blits inside framebuffer <obj-blit>` -0x0037 NV4:NV50 NV3_SIFM :ref:`scaled image from memory <obj-sifm>` -0x0077 NV4:NV50 NV4_SIFM :ref:`scaled image from memory <obj-sifm>` -0x0063 NV10:NV50 NV5_SIFM :ref:`scaled image from memory <obj-sifm>` +0x009f NV15:G80 NV15_BLIT :ref:`blits inside framebuffer <obj-blit>` +0x0037 NV4:G80 NV3_SIFM :ref:`scaled image from memory <obj-sifm>` +0x0077 NV4:G80 NV4_SIFM :ref:`scaled image from memory <obj-sifm>` +0x0063 NV10:G80 NV5_SIFM :ref:`scaled image from memory <obj-sifm>` 0x0089 NV10:NV40 NV10_SIFM :ref:`scaled image from memory <obj-sifm>` 0x0389 NV30:NV40 NV30_SIFM :ref:`scaled image from memory <obj-sifm>` -0x3089 NV40:NV50 NV30_SIFM :ref:`scaled image from memory <obj-sifm>` -0x5089 NV50:G84 NV50_SIFM :ref:`scaled image from memory <obj-sifm>` +0x3089 NV40:G80 NV30_SIFM :ref:`scaled image from memory <obj-sifm>` +0x5089 G80:G84 G80_SIFM :ref:`scaled image from memory <obj-sifm>` 0x004b NV4:NV40 NV3_GDI :ref:`draws GDI primitives <obj-gdi>` -0x004a NV4:NV50 NV4_GDI :ref:`draws GDI primitives <obj-gdi>` +0x004a NV4:G80 NV4_GDI :ref:`draws GDI primitives <obj-gdi>` ====== ========= ========= ============ :ref:`YCbCr two-source blending objects <obj-dvd>`: @@ -196,8 +196,8 @@ class variants name description ====== ========= ========= class variants name ====== ========= ========= -0x0038 NV4:NV50 NV4_DVD_SUBPICTURE -0x0088 NV10:NV50 NV10_DVD_SUBPICTURE +0x0038 NV4:G80 NV4_DVD_SUBPICTURE +0x0088 NV10:G80 NV10_DVD_SUBPICTURE ====== ========= ========= .. todo:: find better name for these two @@ -207,7 +207,7 @@ class variants name ====== ========== ========= class variants name ====== ========== ========= -0x502d NV50:GF100 NV50_2D +0x502d G80:GF100 G80_2D 0x902d GF100- GF100_2D ====== ========== ========= @@ -232,13 +232,13 @@ NV10-style 3d objects: 0x0397 [NV30:NV40] NV30_3D - Rankine Direct3D 9 SM 2 engine [graph/nv30-3d.txt] 0x0497 [NV35:NV34] NV35_3D - Rankine Direct3D 9 SM 2 engine [graph/nv30-3d.txt] 0x0697 [NV34:NV40] NV34_3D - Rankine Direct3D 9 SM 2 engine [graph/nv30-3d.txt] -0x4097 [NV40:NV50 non-TC] NV40_3D - Curie Direct3D 9 SM 3 engine [graph/nv40-3d.txt] -0x4497 [NV40:NV50 TC] NV44_3D - Curie Direct3D 9 SM 3 engine [graph/nv40-3d.txt] -0x5097 [NV50:G200] NV50_3D - Tesla Direct3D 10 engine [graph/nv50-3d.txt] -0x8297 [G84:G200] G84_3D - Tesla Direct3D 10 engine [graph/nv50-3d.txt] -0x8397 [G200:GT215] G200_3D - Tesla Direct3D 10 engine [graph/nv50-3d.txt] -0x8597 [GT215:MCP89] GT215_3D - Tesla Direct3D 10.1 engine [graph/nv50-3d.txt] -0x8697 [MCP89:GF100] MCP89_3D - Tesla Direct3D 10.1 engine [graph/nv50-3d.txt] +0x4097 [NV40:G80 non-TC] NV40_3D - Curie Direct3D 9 SM 3 engine [graph/nv40-3d.txt] +0x4497 [NV40:G80 TC] NV44_3D - Curie Direct3D 9 SM 3 engine [graph/nv40-3d.txt] +0x5097 [G80:G200] G80_3D - Tesla Direct3D 10 engine [graph/g80-3d.txt] +0x8297 [G84:G200] G84_3D - Tesla Direct3D 10 engine [graph/g80-3d.txt] +0x8397 [G200:GT215] G200_3D - Tesla Direct3D 10 engine [graph/g80-3d.txt] +0x8597 [GT215:MCP89] GT215_3D - Tesla Direct3D 10.1 engine [graph/g80-3d.txt] +0x8697 [MCP89:GF100] MCP89_3D - Tesla Direct3D 10.1 engine [graph/g80-3d.txt] 0x9097 [GF100:GK104] GF100_3D - Fermi Direct3D 11 engine [graph/gf100-3d.txt] 0x9197 [GF108:GK104] GF108_3D - Fermi Direct3D 11 engine [graph/gf100-3d.txt] 0x9297 [GF110:GK104] GF110_3D - Fermi Direct3D 11 engine [graph/gf100-3d.txt] @@ -246,8 +246,8 @@ NV10-style 3d objects: 0xa197 [GK110-] GK110_3D - Kepler Direct3D 11.1 engine [graph/gf100-3d.txt] And the compute objects: -0x50c0 [NV50:GF100] NV50_COMPUTE - CUDA 1.x engine [graph/nv50-compute.txt] -0x85c0 [GT215:GF100] GT215_COMPUTE - CUDA 1.x engine [graph/nv50-compute.txt] +0x50c0 [G80:GF100] G80_COMPUTE - CUDA 1.x engine [graph/g80-compute.txt] +0x85c0 [GT215:GF100] GT215_COMPUTE - CUDA 1.x engine [graph/g80-compute.txt] 0x90c0 [GF100:GK104] GF100_COMPUTE - CUDA 2.x engine [graph/gf100-compute.txt] 0x91c0 [GF110:GK104] GF110_COMPUTE - CUDA 2.x engine [graph/gf100-compute.txt] 0xa0c0 [GK104:GK110] GK104_COMPUTE - CUDA 3.x engine [graph/gf100-compute.txt] @@ -402,7 +402,7 @@ base+0xc: in order, it is guaranteed that the whole notifier structure has been written by the time this field is set to 0. -.. todo:: verify big endian on non-NV50 +.. todo:: verify big endian on non-G80 There are two types of notifiers: ordinary notifiers [NV1-] and M2MF notifiers [NV3-]. Normal notifiers are written when explicitely requested by the NOTIFY diff --git a/docs/hw/graph/tesla/3d.rst b/docs/hw/graph/tesla/3d.rst index cd049518..ded8fae1 100644 --- a/docs/hw/graph/tesla/3d.rst +++ b/docs/hw/graph/tesla/3d.rst @@ -1,8 +1,8 @@ .. _obj-tesla-3d: -===================== -NV50 Tesla 3D objects -===================== +==================== +G80 Tesla 3D objects +==================== .. contents:: diff --git a/docs/hw/graph/tesla/compute.rst b/docs/hw/graph/tesla/compute.rst index ed353bb1..77fe8c3a 100644 --- a/docs/hw/graph/tesla/compute.rst +++ b/docs/hw/graph/tesla/compute.rst @@ -1,8 +1,8 @@ .. _obj-tesla-compute: -========================== -NV50 Tesla compute objects -========================== +========================= +G80 Tesla compute objects +========================= .. contents:: diff --git a/docs/hw/graph/tesla/crop.rst b/docs/hw/graph/tesla/crop.rst index 40125bee..f0b0939e 100644 --- a/docs/hw/graph/tesla/crop.rst +++ b/docs/hw/graph/tesla/crop.rst @@ -1,4 +1,4 @@ -.. _nv50-crop: +.. _g80-crop: Color raster output: CROP ========================= diff --git a/docs/hw/graph/tesla/ctxctl.rst b/docs/hw/graph/tesla/ctxctl.rst index ade1f21a..d2508e03 100644 --- a/docs/hw/graph/tesla/ctxctl.rst +++ b/docs/hw/graph/tesla/ctxctl.rst @@ -1,8 +1,8 @@ -.. _nv50-ctxctl: +.. _g80-ctxctl: -============================= -NV50 PGRAPH context switching -============================= +============================ +G80 PGRAPH context switching +============================ .. contents:: diff --git a/docs/hw/graph/tesla/cuda/isa.rst b/docs/hw/graph/tesla/cuda/isa.rst index 52557124..70d069c6 100644 --- a/docs/hw/graph/tesla/cuda/isa.rst +++ b/docs/hw/graph/tesla/cuda/isa.rst @@ -176,7 +176,7 @@ The registers in Tesla ISA are: .. todo:: seems to always be 0x20. Is it really that boring, or does MP switch to a smaller/bigger stride sometimes? - - $sr4-$sr7 aka $pm0-$pm3: :ref:`MP performance counters <nv50-mp-pm>`. + - $sr4-$sr7 aka $pm0-$pm3: :ref:`MP performance counters <g80-mp-pm>`. - $sr8 aka $sampleid [GT215:]: the sample ID. Useful only in fragment programs when sample shading is enabled. diff --git a/docs/hw/graph/tesla/index.rst b/docs/hw/graph/tesla/index.rst index 40a91c01..a16ea3bf 100644 --- a/docs/hw/graph/tesla/index.rst +++ b/docs/hw/graph/tesla/index.rst @@ -1,5 +1,5 @@ -NV50 Tesla graphics and compute engine -====================================== +G80 Tesla graphics and compute engine +===================================== Contents: diff --git a/docs/hw/graph/tesla/pgraph.rst b/docs/hw/graph/tesla/pgraph.rst index f55ee26a..7f614c91 100644 --- a/docs/hw/graph/tesla/pgraph.rst +++ b/docs/hw/graph/tesla/pgraph.rst @@ -1,14 +1,14 @@ -.. _nv50-pgraph: -.. _nv50-pgraph-vfetch: -.. _nv50-pgraph-strmout: -.. _nv50-pgraph-ccache: -.. _nv50-pgraph-texture: -.. _nv50-pgraph-rop: -.. _nv50-pgraph-dispatch: -.. _nv50-pgraph-clipid: - -============================================== -NV50 PGRAPH: 2d/3d graphics and compute engine +.. _g80-pgraph: +.. _g80-pgraph-vfetch: +.. _g80-pgraph-strmout: +.. _g80-pgraph-ccache: +.. _g80-pgraph-texture: +.. _g80-pgraph-rop: +.. _g80-pgraph-dispatch: +.. _g80-pgraph-clipid: + +============================================= +80 PGRAPH: 2d/3d graphics and compute engine ============================================== .. contents:: @@ -23,12 +23,12 @@ Introduction MMIO registers ============== -.. space:: 8 nv50-pgraph 0x10000 2d/3d graphics and compute engine +.. space:: 8 g80-pgraph 0x10000 2d/3d graphics and compute engine .. todo:: write me -.. _nv50-pgraph-intr: +.. _g80-pgraph-intr: Interrupts ========== diff --git a/docs/hw/graph/tesla/prop.rst b/docs/hw/graph/tesla/prop.rst index 33f6807b..5db71464 100644 --- a/docs/hw/graph/tesla/prop.rst +++ b/docs/hw/graph/tesla/prop.rst @@ -1,4 +1,4 @@ -.. _nv50-prop: +.. _g80-prop: Pre-ROP: PROP ============= diff --git a/docs/hw/graph/tesla/vfetch.rst b/docs/hw/graph/tesla/vfetch.rst index b3b1253d..e4853620 100644 --- a/docs/hw/graph/tesla/vfetch.rst +++ b/docs/hw/graph/tesla/vfetch.rst @@ -1,4 +1,4 @@ -.. _nv50-vfetch: +.. _g80-vfetch: Vertex fetch: VFETCH ==================== diff --git a/docs/hw/graph/tesla/zrop.rst b/docs/hw/graph/tesla/zrop.rst index dccc3580..1be06eff 100644 --- a/docs/hw/graph/tesla/zrop.rst +++ b/docs/hw/graph/tesla/zrop.rst @@ -1,4 +1,4 @@ -.. _nv50-zrop: +.. _g80-zrop: Zeta raster output: ZROP ======================== diff --git a/docs/hw/intro.rst b/docs/hw/intro.rst index 6d9fce0e..a4f00f9f 100644 --- a/docs/hw/intro.rst +++ b/docs/hw/intro.rst @@ -125,7 +125,7 @@ integrated into the main system chipset. They don't have on-board memory or memory controller, sharing the main system RAM instead. -GPU schematic - NV3:NV50 +GPU schematic - NV3:G80 ======================== @@ -247,7 +247,7 @@ by a common bus and visible through PCI BAR0 [see :ref:`bars`]. This bus is not shown above. -GPU schematic - NV50:GF100 +GPU schematic - G80:GF100 ========================== :: diff --git a/docs/hw/io/nv50-gpio.rst b/docs/hw/io/g80-gpio.rst index 78588718..70f0ad10 100644 --- a/docs/hw/io/nv50-gpio.rst +++ b/docs/hw/io/g80-gpio.rst @@ -1,8 +1,8 @@ -.. _nv50-gpio: +.. _g80-gpio: -===================== -NV50:GF119 GPIO lines -===================== +==================== +G80:GF119 GPIO lines +==================== .. contents:: @@ -15,7 +15,7 @@ Introduction .. todo:: write me -.. _nv50-gpio-intr: +.. _g80-gpio-intr: Interrupts ========== @@ -23,10 +23,10 @@ Interrupts .. todo:: write me -NV50 GPIO NVIO specials -======================= +G80 GPIO NVIO specials +====================== -This list applies to NV50. +This list applies to G80. ===== ========== ======= Line Output Input diff --git a/docs/hw/io/index.rst b/docs/hw/io/index.rst index d1f57c02..b62369e8 100644 --- a/docs/hw/io/index.rst +++ b/docs/hw/io/index.rst @@ -10,6 +10,6 @@ Contents: prom pnvio nv10-gpio - nv50-gpio + g80-gpio nv1-peeprom pmedia diff --git a/docs/hw/io/nv10-gpio.rst b/docs/hw/io/nv10-gpio.rst index b58400d5..45cc27cb 100644 --- a/docs/hw/io/nv10-gpio.rst +++ b/docs/hw/io/nv10-gpio.rst @@ -1,8 +1,8 @@ .. _nv10-gpio: -==================== -NV10:NV50 GPIO lines -==================== +=================== +NV10:G80 GPIO lines +=================== .. contents:: diff --git a/docs/hw/io/pstraps.rst b/docs/hw/io/pstraps.rst index d2c69672..148a02b8 100644 --- a/docs/hw/io/pstraps.rst +++ b/docs/hw/io/pstraps.rst @@ -179,23 +179,23 @@ Set 0: - 0: 16MB - 1: 128MB -- bits 16-19 [NV17:NV20 and NV25:NV50]: flat panel config [used to select entry from fp mode table] -- bits 20-21: DEVICE_ID bits 2-3 [NV17:NV20 and NV25:NV50] -- bit 22: crystal type bit 1 [NV17:NV20 and NV25:NV50] -- bits 23-24 [NV17:NV20 and NV25:NV50]: BAR1 size +- bits 16-19 [NV17:NV20 and NV25:G80]: flat panel config [used to select entry from fp mode table] +- bits 20-21: DEVICE_ID bits 2-3 [NV17:NV20 and NV25:G80] +- bit 22: crystal type bit 1 [NV17:NV20 and NV25:G80] +- bits 23-24 [NV17:NV20 and NV25:G80]: BAR1 size - 0: 64MB - 1: 128MB - 2: 256MB - 3: 512MB -- bit 25 [NV17:NV20 and NV25:NV50]: BAR0 size [XXX: I'm almost sure it does something else too] +- bit 25 [NV17:NV20 and NV25:G80]: BAR0 size [XXX: I'm almost sure it does something else too] - 0: 16MB - 1: 128MB - bits 26-28: ? -- bits 29-30 [NV17:NV20 and NV25:NV50]: bios ROM type +- bits 29-30 [NV17:NV20 and NV25:G80]: bios ROM type - 0: parallel - 1: serial [SPI] @@ -220,8 +220,8 @@ Set 1: - bits 5-30: ? -NV50+ families straps sets -========================== +G80+ families straps sets +========================= Set 0: diff --git a/docs/hw/memory/nv50-comp.rst b/docs/hw/memory/g80-comp.rst index bda95d0f..875dc82c 100644 --- a/docs/hw/memory/nv50-comp.rst +++ b/docs/hw/memory/g80-comp.rst @@ -1,8 +1,8 @@ -.. _nv50-comp: +.. _g80-comp: -===================== -NV50 VRAM compression -===================== +==================== +G80 VRAM compression +==================== .. contents:: diff --git a/docs/hw/memory/nv50-host-mem.rst b/docs/hw/memory/g80-host-mem.rst index 788f8e0e..e185042f 100644 --- a/docs/hw/memory/nv50-host-mem.rst +++ b/docs/hw/memory/g80-host-mem.rst @@ -1,8 +1,8 @@ -.. _nv50-host-mem: +.. _g80-host-mem: -================================ -NV50:GF100 host memory interface -================================ +=============================== +G80:GF100 host memory interface +=============================== .. contents:: @@ -15,14 +15,14 @@ Introduction .. todo:: write me -.. _pbus-mmio-nv50-host-mem: +.. _pbus-mmio-g80-host-mem: MMIO registers ============== .. todo:: write me -.. space:: 8 nv50-pflush 0x1000 used to flush BAR writes +.. space:: 8 g80-pflush 0x1000 used to flush BAR writes .. todo:: write me diff --git a/docs/hw/memory/nv50-p2p.rst b/docs/hw/memory/g80-p2p.rst index 9632f896..e92363a2 100644 --- a/docs/hw/memory/nv50-p2p.rst +++ b/docs/hw/memory/g80-p2p.rst @@ -1,8 +1,8 @@ -.. _nv50-p2p: +.. _g80-p2p: -============================ -NV50:GF100 P2P memory access -============================ +=========================== +G80:GF100 P2P memory access +=========================== .. contents:: @@ -15,7 +15,7 @@ Introduction .. todo:: write me -.. _pbus-mmio-nv50-p2p: +.. _pbus-mmio-g80-p2p: MMIO registers ============== diff --git a/docs/hw/memory/g80-pfb.rst b/docs/hw/memory/g80-pfb.rst new file mode 100644 index 00000000..7e98dfed --- /dev/null +++ b/docs/hw/memory/g80-pfb.rst @@ -0,0 +1,23 @@ +.. _g80-pfb: + +================================ +PFB: G80:GF100 memory controller +================================ + +.. contents:: + +.. todo:: write me + + +Introduction +============ + +.. todo:: write me + + +MMIO registers +============== + +.. space:: 8 g80-pfb 0x1000 memory interface & VM control + + .. todo:: write me diff --git a/docs/hw/memory/nv50-remap.rst b/docs/hw/memory/g80-remap.rst index 719b955f..672c4f58 100644 --- a/docs/hw/memory/nv50-remap.rst +++ b/docs/hw/memory/g80-remap.rst @@ -1,8 +1,8 @@ -.. _nv50-remap: +.. _g80-remap: -======================== -NV50:GF100 BAR1 remapper -======================== +======================= +G80:GF100 BAR1 remapper +======================= .. contents:: @@ -15,7 +15,7 @@ Introduction .. todo:: write me -.. _pbus-mmio-nv50-remap: +.. _pbus-mmio-g80-remap: MMIO registers ============== diff --git a/docs/hw/memory/nv50-surface.rst b/docs/hw/memory/g80-surface.rst index 1de8a79b..dd355906 100644 --- a/docs/hw/memory/nv50-surface.rst +++ b/docs/hw/memory/g80-surface.rst @@ -1,8 +1,8 @@ -.. _nv50-surface: +.. _g80-surface: -===================== -NV50- surface formats -===================== +=================== +G80 surface formats +=================== .. contents:: @@ -10,7 +10,7 @@ NV50- surface formats Introduction ============ -This file deals with nv50+ cards only. For older cards, see :ref:`nv1-surface`. +This file deals with G80+ cards only. For older cards, see :ref:`nv1-surface`. A "surface" is a 2d or 3d array of elements. Surfaces are used for image storage, and can be bound to at least the following slots on the engines: @@ -20,7 +20,7 @@ storage, and can be bound to at least the following slots on the engines: - 3d/compute texture units: the textures - 3d color render targets - 3d zeta render target -- compute g[] spaces [NV50:GF100] +- compute g[] spaces [G80:GF100] - 3d/compute image units [GF100+] - PCOPY input and output buffers - PDISPLAY: the framebuffer @@ -28,7 +28,7 @@ storage, and can be bound to at least the following slots on the engines: .. todo:: vdec stuff .. todo:: GF100 ZCULL? -Surfaces on nv50+ cards come in two types: linear and tiled. Linear surfaces +Surfaces on G80+ cards come in two types: linear and tiled. Linear surfaces have a simple format, but they're are limited to 2 dimensions only, don't support arrays nor mipmapping when used as textures, cannot be used for zeta buffers, and have lower performance than tiled textures. Tiled surfaces @@ -104,14 +104,14 @@ Tiled surfaces A tiled surface is a 3d array of elements, stored in memory in units called "tiles". There are two levels of tiling. The lower-level tile is called -a "roptile" and has a fixed size. This size is 64 bytes × 4 × 1 on NV50:GF100 +a "roptile" and has a fixed size. This size is 64 bytes × 4 × 1 on G80:GF100 cards, 64 bytes × 8 × 1 for GF100+ cards. The higher-level tile is called a bigtile, and is of variable size between 1×1×1 and 32×32×32 roptiles. The attributes defining a tiled surface are: - address: 40-bit VM address, aligned to roptile size [0x100 bytes on - NV50:GF100, 0x200 bytes on GF100] + G80:GF100, 0x200 bytes on GF100] - tile size x: 0-5, log2 of roptiles per bigtile in x dimension - tile size y: 0-5, log2 of roptiles per bigtile in y dimension - tile size z: 0-5, log2 of roptiles per bigtile in z dimension @@ -129,7 +129,7 @@ specific to the binding point. In particular, x tile size greater than 0 is only supported by the render targets and texture units, with render targets only supporting 0 and 1. y tile sizes 0-5 can be safely used with all tiled surface binding points, and z tile sizes 0-5 can be used with binding points -other than NV50 g[] spaces, which only support 0. +other than G80 g[] spaces, which only support 0. The tiled format works as follows: @@ -217,7 +217,7 @@ storage type dependent, invisible to the user, and will be covered below. As an example, let's take a 13 × 17 × 3 surface with element size of 16 bytes, tile size x of 1, tile size y of 1, and tile size z of 1. Further, -the card is assumed to be nv50. The surface will be located in memory the +the card is assumed to be G80. The surface will be located in memory the following way: - bigtile size in bytes = 0x800 bytes @@ -325,7 +325,7 @@ following way: Textures, mipmapping and arrays =============================== -A texture on NV50/GF100 can have one of 9 types: +A texture on G80/GF100 can have one of 9 types: - 1D: made of 1 or more mip levels, each mip level is a tiled surface with height and depth forced to 1 @@ -381,7 +381,7 @@ stored sequentially:: subtexture_address[i] = texture_address + i * subtexture_bytes; } -For more information about textures, see graph/nv50-texture.txt +For more information about textures, see graph/g80-texture.txt Multisampled surfaces @@ -397,7 +397,7 @@ These samples correspond to various points inside the pixel, called sample positions. When a multisample surface has to be displayed, it is downsampled to a normal surface by an operation called "resolving". -nv50+ GPUs also support a variant of multisampling called "coverage sampling" +G80+ GPUs also support a variant of multisampling called "coverage sampling" or CSAA. When CSAA is used, there are two sample types: full samples and coverage samples. Full samples behave as in normal multisampling. Coverage samples have assigned positions inside a pixel, but their values are not @@ -871,7 +871,7 @@ RT multisample configuration. For textures, Z corresponds to C0, S to C1, and C to C2. However, C cannot be used together with Z and/or S in a single sampler. Z and S sampling works normally, but when C is sampled, the sampler returns preprocessed weights -instead of the raw value - see graph/nv50-texture.txt for more information +instead of the raw value - see graph/g80-texture.txt for more information about the sampling process. The formats are: @@ -952,7 +952,7 @@ by x coordinate of the sample, then by its y coordinate. This format can be used for 2d engine and texturing. When used for texturing, it forces using a special "box" filter: result of sampling is a percentage of "lit" area in WxH rectangle centered on the sampled location. See -graph/nv50-texture.txt for more details. +graph/g80-texture.txt for more details. .. todo:: figure out more. Check how it works with 2d engine. @@ -965,10 +965,10 @@ Element size 8: - color format 0x1c: BITMAP -NV50 storage types -================== +G80 storage types +================= -On nv50, the storage type is made of two parts: the storage type itself, and +On G80, the storage type is made of two parts: the storage type itself, and the compression mode. The storage type is a 7-bit enum, the compression mode is a 2-bit enum. @@ -997,7 +997,7 @@ types: VRAM geometry. Boundaries between VRAM areas using NONE/SSR and LSR need to be properly aligned in physical space to prevent conflicts. -Long range reordering is described in detail in :ref:`nv50-vram`. +Long range reordering is described in detail in :ref:`g80-vram`. The storage types can be roughly split into the following groups: @@ -1005,9 +1005,9 @@ The storage types can be roughly split into the following groups: - tiled color storage types: used for non-zeta tiled surfaces - zeta storage types: used for zeta surfaces -On the original nv50, non-0 storage types can only be used on VRAM, on G84 +On the original G80, non-0 storage types can only be used on VRAM, on G84 and later cards they can also be used on system RAM. Compression modes other -than NONE can only be used on VRAM. However, due to the nv50 limitation, tiled +than NONE can only be used on VRAM. However, due to the G80 limitation, tiled surfaces stored in system RAM are allowed to use storage type 0, and will work correctly for texturing and m2mf source/destination - rendering to them with 2d or 3d engine is impossible, though. diff --git a/docs/hw/memory/nv50-vm.rst b/docs/hw/memory/g80-vm.rst index b442a2b4..7763f59d 100644 --- a/docs/hw/memory/nv50-vm.rst +++ b/docs/hw/memory/g80-vm.rst @@ -1,8 +1,8 @@ -.. _nv50-vm: +.. _g80-vm: -=================== -NV50 virtual memory -=================== +==================== +Tesla virtual memory +==================== .. contents:: @@ -10,7 +10,7 @@ NV50 virtual memory Introduction ============ -NV50 generation cards feature an MMU that translates user-visible logical +G80 generation cards feature an MMU that translates user-visible logical addresses to physical ones. The translation has two levels: DMA objects, which behave like x86 segments, and page tables. The translation involves the following address spaces: @@ -28,7 +28,7 @@ the following address spaces: can be VRAM, SYSRAM_SNOOP, or SYSRAM_NOSNOOP. They can refer to: - VRAM: 32-bit linear addresses - high 8 bits are ignored - on-board - memory of the card. Supports LSR and compression. See :ref:`nv50-vram` + memory of the card. Supports LSR and compression. See :ref:`g80-vram` - SYSRAM: 40-bit linear addresses - accessing this space will cause the card to invoke PCIE read/write transactions to the given bus address, allowing it to access system RAM or other PCI devices' memory. @@ -38,7 +38,7 @@ the following address spaces: Mostly, linear addresses are a result of logical address translation, but some memory areas are specified directly by their linear addresses. - 12-bit tag addresses: select a cell in hidden compression tag RAM, used - for compressed areas of VRAM. See :ref:`nv50-comp` + for compressed areas of VRAM. See :ref:`g80-comp` - physical address: for VRAM, the partition/subpartition/row/bank/column coordinates of a memory cell; for SYSRAM, the final bus address @@ -78,69 +78,69 @@ VM users VM is used by several clients, which are identified by VM client id: -.. enum:: nv50-vm-client +.. enum:: g80-vm-client .. value:: 0x00 STRMOUT :engine: PGRAPH - :ref: nv50-vm-client-strmout + :ref: g80-vm-client-strmout PGRAPH streamout writes .. value:: 0x03 DISPATCH :engine: PGRAPH - :ref: nv50-vm-client-dispatch + :ref: g80-vm-client-dispatch PGRAPH context save/restore, NOTIFY, QUERY, COND, and m2mf .. value:: 0x04 PFIFO_WRITE :engine: PFIFO PFIFO_BG PEEPHOLE BAR - :ref: nv50-vm-client-pfifo-write + :ref: g80-vm-client-pfifo-write Non-blocking write accesses by PFIFO, for FIFOs and BARs .. value:: 0x05 CCACHE :engine: PGRAPH - :ref: nv50-vm-client-ccache + :ref: g80-vm-client-ccache PGRAPH c[], code, TIC, and TSC accesses .. value:: 0x06 PVPE VP1,VP2 :engine: PMPEG PME PVP1 - :ref: nv50-vm-client-pvpe + :ref: g80-vm-client-pvpe - VM front-end for PMPEG + PME [NV50 only] + PVP1 [NV50 only] + VM front-end for PMPEG + PME [G80 only] + PVP1 [G80 only] .. value:: 0x06 PPPP VP3,VP4 :engine: PPPP - :ref: nv50-vm-client-pppp + :ref: g80-vm-client-pppp .. value:: 0x07 CLIPID :engine: PGRAPH - :ref: nv50-vm-client-clipid + :ref: g80-vm-client-clipid PGRAPH window clip id reads/writes .. value:: 0x08 PFIFO_READ :engine: PFIFO PFIFO_BG PEEPHOLE BAR - :ref: nv50-vm-client-pfifo-read + :ref: g80-vm-client-pfifo-read Reads by PFIFO, for FIFOs and BARs .. value:: 0x09 VFETCH :engine: PGRAPH - :ref: nv50-vm-client-vfetch + :ref: g80-vm-client-vfetch PGRAPH vertex array fetch .. value:: 0x0a TEXTURE :engine: PGRAPH - :ref: nv50-vm-client-texture + :ref: g80-vm-client-texture PGRAPH texture fetches .. value:: 0x0b PROP :engine: PGRAPH - :ref: nv50-vm-client-prop + :ref: g80-vm-client-prop PGRAPH raster output and CUDA global/local memory accesses @@ -162,7 +162,7 @@ VM is used by several clients, which are identified by VM client id: .. value:: 0x0e PCRYPT2 VP2 :engine: PCRYPT2 - :ref: nv50-vm-client-pcrypt2 + :ref: g80-vm-client-pcrypt2 .. value:: 0x0e PCRYPT3 VP3 :engine: PCRYPT3 @@ -170,7 +170,7 @@ VM is used by several clients, which are identified by VM client id: .. value:: 0x0f PCOUNTER G84: :engine: PCOUNTER - :ref: nv50-vm-client-pcounter + :ref: g80-vm-client-pcounter .. value:: 0x11 PDAEMON GT215: :engine: PDAEMON @@ -188,10 +188,10 @@ A related concept is VM engine, which is a group of clients that share TLBs and stay on the same channel at any single moment. It's possible for a client to be part of several VM engines. The engines are: -.. enum:: nv50-vm-engine +.. enum:: g80-vm-engine .. value:: 0x0 PGRAPH - :ref: nv50-vm-engine-pgraph + :ref: g80-vm-engine-pgraph .. value:: 0x1 PVP1 VP1 :ref: pvp1 @@ -203,13 +203,13 @@ to be part of several VM engines. The engines are: :ref: pvdec .. value:: 0x4 PEEPHOLE - :ref: nv50-vm-engine-peephole + :ref: g80-vm-engine-peephole .. value:: 0x5 PFIFO - :ref: nv50-vm-engine-pfifo + :ref: g80-vm-engine-pfifo .. value:: 0x6 BAR - :ref: nv50-vm-engine-bar + :ref: g80-vm-engine-bar .. value:: 0x7 PME VP1 :ref: pme @@ -239,7 +239,7 @@ to be part of several VM engines. The engines are: :ref: pcounter .. value:: 0xc PFIFO_BG G84: - :ref: nv50-vm-engine-pfifo-bg + :ref: g80-vm-engine-pfifo-bg Handles background semaphore acquire polling. @@ -284,12 +284,12 @@ ids depends on both engine and client id. The DMA slots are - 5/4/1: FIFO semaphore write - 5/8/1: FIFO semaphore read - c/8/1: FIFO background semaphore read -- 1/6/8: PVP1 context [NV50:G84] -- 7/6/4: PME context [NV50:G84] -- 8/6/1: PMPEG CMD [NV50:G98 G200:MCP77] -- 8/6/2: PMPEG DATA [NV50:G98 G200:MCP77] -- 8/6/3: PMPEG IMAGE [NV50:G98 G200:MCP77] -- 8/6/4: PMPEG context [NV50:G98 G200:MCP77] +- 1/6/8: PVP1 context [G80:G84] +- 7/6/4: PME context [G80:G84] +- 8/6/1: PMPEG CMD [G80:G98 G200:MCP77] +- 8/6/2: PMPEG DATA [G80:G98 G200:MCP77] +- 8/6/3: PMPEG IMAGE [G80:G98 G200:MCP77] +- 8/6/4: PMPEG context [G80:G98 G200:MCP77] - 8/6/5: PMPEG QUERY [G84:G98 G200:MCP77] - b/f/0: PCOUNTER record buffer [G84:GF100] - 1/c/0-f: PVP2 DMA ports 0-0xf [G84:G98 G200:MCP77] @@ -337,7 +337,7 @@ inside it, the channel structure has no fixed size, although the maximal address of channel objects is 0xffff0. Channel structure has to be aligned to 0x1000 bytes. -The original NV50 channel structure has the following fixed elements: +The original G80 channel structure has the following fixed elements: - 0x000-0x200: RAMFC [fifo channels only] - 0x200-0x400: DMA objects for fifo engines' contexts [fifo channels only] @@ -353,7 +353,7 @@ The channel objects are specified by 16-bit offsets from start of the channel structure in 0x10-byte units. -.. _nv50-dmaobj: +.. _g80-dmaobj: DMA objects =========== @@ -466,13 +466,13 @@ The fifo engine context dmaobjs are a special set of DMA objects worth mentioning. They're used by the fifo engines to store per-channel state while given channel is inactive on the relevant engine. Their size and structure depend on the engine. They have fixed selectors, and hence reside -at fixed positions inside the channel structure. On the original NV50, the +at fixed positions inside the channel structure. On the original G80, the objects are: ======== ======= ======= Selector Address Engine ======== ======= ======= -0x0020 0x00200 :ref:`PGRAPH <nv50-pgraph>` +0x0020 0x00200 :ref:`PGRAPH <g80-pgraph>` 0x0022 0x00220 :ref:`PVP1 <pvp1>` 0x0024 0x00240 :ref:`PME <pme>` 0x0026 0x00260 :ref:`PMPEG <pmpeg>` @@ -483,7 +483,7 @@ On G84+ cards, they are: ======== ======= ========== ======= Selector Address Present on Engine ======== ======= ========== ======= - 0x0002 0x00020 all :ref:`PGRAPH <nv50-pgraph>` + 0x0002 0x00020 all :ref:`PGRAPH <g80-pgraph>` 0x0004 0x00040 VP2 :ref:`PVP2 <pvp2>` 0x0004 0x00040 VP3- :ref:`PVDEC <pvdec>` 0x0006 0x00060 VP2 :ref:`PMPEG <pmpeg>` @@ -504,7 +504,7 @@ If paged DMA object is used, the virtual address is further looked up in page tables. The page tables are two-level. Top level is 0x800-entry page directory, where each entry covers 0x20000000 bytes of virtual address space. The page directory is embedded in the channel structure. It starts at offset -0x1400 on the original NV50, at 0x200 on G84+. Each page directory entry, or +0x1400 on the original G80, at 0x200 on G84+. Each page directory entry, or PDE, is 8 bytes long. The PDEs point to page tables and specify the page table attributes. Each page table can use either small, medium [GT215-] or large pages. Small pages are 0x1000 bytes long, medium pages are 0x4000 bytes long, @@ -609,7 +609,7 @@ MMIO 0x100c80: A flush consists of writing engine << 16 | 1 to this register and waiting until bit 0 becomes 0. However, note that G86 PGRAPH has a bug that can result in a lockup if PGRAPH TLB flush is initiated while PGRAPH is running, -see graph/nv50-pgraph.txt for details. +see graph/g80-pgraph.txt for details. User vs supervisor accesses diff --git a/docs/hw/memory/nv50-vram.rst b/docs/hw/memory/g80-vram.rst index 4ee20ac7..3dc927be 100644 --- a/docs/hw/memory/nv50-vram.rst +++ b/docs/hw/memory/g80-vram.rst @@ -1,8 +1,8 @@ -.. _nv50-vram: +.. _g80-vram: -=================================== -NV50:GF100 VRAM structure and usage -=================================== +================================== +G80:GF100 VRAM structure and usage +================================== .. contents:: @@ -10,17 +10,17 @@ NV50:GF100 VRAM structure and usage Introduction ============ -The basic structure of NV50 memory is similiar to other card generations +The basic structure of G80 memory is similiar to other card generations and is described in :ref:`vram`. -There are two sub-generations of NV50 memory controller: the original NV50 one -and the GT215 one. The NV50 memory controller was designed for DDR2 and GDDR3 +There are two sub-generations of G80 memory controller: the original G80 one +and the GT215 one. The G80 memory controller was designed for DDR2 and GDDR3 memory. It's split into several [1-8] partitions, each of them having 64-bit memory bus. The GT215 memory controller added support for DDR3 and GDDR5 memory and split the partitions into two subpartitions, each of them having 32-bit memory bus. -On NV50, the combination of DDR2/GDDR3 [ie. 4n prefetch] memory with 64-bit +On G80, the combination of DDR2/GDDR3 [ie. 4n prefetch] memory with 64-bit memory bus results in 32-byte minimal transfer size. For that reason, 32-byte units are called sectors. On GT215, DDR3/GDDR5 [ie. 8n prefetch] memory with 32-bit memory bus gives the same figure. @@ -32,7 +32,7 @@ in a single partition. Also, format dependent memory address reordering is applied within a block. The final fixed level of VRAM granularity is a 0x10000-byte [64kiB] large -page. While NV50 VM supports using smaller page sizes for VRAM, certain +page. While G80 VM supports using smaller page sizes for VRAM, certain features [compression, long partition cycle] should only be enabled on per-large page basis. @@ -108,13 +108,13 @@ The outputs of this process are: Partition pre-ID and ID adjust are intermediate values in this process. -On NV50 [and NV50 only], there are two partition cycles available: short one +On G80 [and G80 only], there are two partition cycles available: short one and long one. The short one switches partitions every block, while the long one switches partitions roughly every 4 blocks. However, to make sure addresses don't "bleed" between large page bounduaries, long partition cycle reverts to switching partitions every block near large page bounduaries:: - if partition_cycle == LONG and gpu == NV50: + if partition_cycle == LONG and gpu == G80: # round down to 4 * partition_count multiple group_start = block_index / (4 * partition_count) * 4 * partition_count group_end = group_start + 4 * partition_count - 1 @@ -192,7 +192,7 @@ Subpartition cycle ================== On GT215+, once the partition block index has been determined, it has to be -further transformed to subpartition ID and subpartition block index. On NV50, +further transformed to subpartition ID and subpartition block index. On G80, this step doesn't exist - partitions are not split into subpartitions, and "subpartition" in further steps should be taken to actually refer to a partition. diff --git a/docs/hw/memory/index.rst b/docs/hw/memory/index.rst index 3e8c3b9f..98b87629 100644 --- a/docs/hw/memory/index.rst +++ b/docs/hw/memory/index.rst @@ -20,14 +20,14 @@ Contents: nv40-pfb nv44-pfb nv44-host-mem - nv50-surface - nv50-vm - nv50-host-mem - nv50-vram - nv50-comp - nv50-p2p - nv50-remap - nv50-pfb + g80-surface + g80-vm + g80-host-mem + g80-vram + g80-comp + g80-p2p + g80-remap + g80-pfb gf100-vm gf100-host-mem gf100-vram diff --git a/docs/hw/memory/nv1-surface.rst b/docs/hw/memory/nv1-surface.rst index 6845fe44..c3847a27 100644 --- a/docs/hw/memory/nv1-surface.rst +++ b/docs/hw/memory/nv1-surface.rst @@ -1,8 +1,8 @@ .. _nv1-surface: -======================== -NV1:NV50 surface formats -======================== +======================= +NV1:G80 surface formats +======================= .. contents:: diff --git a/docs/hw/memory/nv4-dmaobj.rst b/docs/hw/memory/nv4-dmaobj.rst index 2d370d96..62d35d6d 100644 --- a/docs/hw/memory/nv4-dmaobj.rst +++ b/docs/hw/memory/nv4-dmaobj.rst @@ -1,8 +1,8 @@ .. _nv4-dmaobj: -==================== -NV4:NV50 DMA objects -==================== +=================== +NV4:G80 DMA objects +=================== .. contents:: diff --git a/docs/hw/memory/nv4-vram.rst b/docs/hw/memory/nv4-vram.rst index 3f16afbd..b58e673b 100644 --- a/docs/hw/memory/nv4-vram.rst +++ b/docs/hw/memory/nv4-vram.rst @@ -1,8 +1,8 @@ .. _nv4-vram: -================================= -NV4:NV50 VRAM structure and usage -================================= +================================ +NV4:G80 VRAM structure and usage +================================ .. contents:: diff --git a/docs/hw/memory/nv40-pfb.rst b/docs/hw/memory/nv40-pfb.rst index f13c8d00..bc7cc911 100644 --- a/docs/hw/memory/nv40-pfb.rst +++ b/docs/hw/memory/nv40-pfb.rst @@ -1,8 +1,8 @@ -.. _nv44-pfb: +.. _nv40-pfb: -=========================================== -PFB: NV44:NV50 TURBOCACHE memory controller -=========================================== +====================================== +PFB: NV40:G80 non-TC memory controller +====================================== .. contents:: @@ -18,6 +18,6 @@ Introduction MMIO registers ============== -.. space:: 8 nv44-pfb 0x1000 memory interface & PCIE GART +.. space:: 8 nv40-pfb 0x1000 memory interface & PCIE GART .. todo:: write me diff --git a/docs/hw/memory/nv44-pfb.rst b/docs/hw/memory/nv44-pfb.rst index 804e5929..a6020095 100644 --- a/docs/hw/memory/nv44-pfb.rst +++ b/docs/hw/memory/nv44-pfb.rst @@ -1,8 +1,8 @@ -.. _nv40-pfb: +.. _nv44-pfb: -======================================= -PFB: NV40:NV50 non-TC memory controller -======================================= +========================================== +PFB: NV44:G80 TURBOCACHE memory controller +========================================== .. contents:: @@ -18,6 +18,6 @@ Introduction MMIO registers ============== -.. space:: 8 nv40-pfb 0x1000 memory interface & PCIE GART +.. space:: 8 nv44-pfb 0x1000 memory interface & PCIE GART .. todo:: write me diff --git a/docs/hw/memory/nv50-pfb.rst b/docs/hw/memory/nv50-pfb.rst deleted file mode 100644 index 54ae4b20..00000000 --- a/docs/hw/memory/nv50-pfb.rst +++ /dev/null @@ -1,23 +0,0 @@ -.. _nv50-pfb: - -================================= -PFB: NV50:GF100 memory controller -================================= - -.. contents:: - -.. todo:: write me - - -Introduction -============ - -.. todo:: write me - - -MMIO registers -============== - -.. space:: 8 nv50-pfb 0x1000 memory interface & VM control - - .. todo:: write me diff --git a/docs/hw/memory/peephole.rst b/docs/hw/memory/peephole.rst index 27d53c38..65ac76b2 100644 --- a/docs/hw/memory/peephole.rst +++ b/docs/hw/memory/peephole.rst @@ -11,26 +11,26 @@ Introduction ============ PEEPHOLE is a mechanism to indirectly access memory form the CPU. It is -present on NV30+ cards. On NV30:NV50, it accesses physical [unpaged] VRAM. -On NV50+, it can access either physical VRAM, or virtual [paged] memory via +present on NV30+ cards. On NV30:G80, it accesses physical [unpaged] VRAM. +On G80+, it can access either physical VRAM, or virtual [paged] memory via standard VM circuitry. Additionally, on G84+, the PEEPHOLE MMIO registers are stuffed into a dedicated range [0x060000:0x061000], so that the driver can allow userspace programs access to the PEEPHOLE and nothing else. PEEPHOLE is part of PBUS and thus not affected by any PMC.ENABLE bit. The -actual memory access is handled by PFIFO on NV50+ cards. +actual memory access is handled by PFIFO on G80+ cards. The PEEPHOLE has two ports: a write-only port and a read-write port. The ports -share a common VM context on NV50+, but are otherwise independent. The +share a common VM context on G80+, but are otherwise independent. The write-only port is only present on NV30:GF100. The addresses used for PEEPHOLE accesses have to be 4-byte aligned, and the window for indirect access is 4 bytes long. The addresses are 29-bit on -NV30:NV50 [enough to address all of VRAM], 32-bit on NV50:GF100, 40-bit on +NV30:G80 [enough to address all of VRAM], 32-bit on G80:GF100, 40-bit on GF100+. -For details on setting up the target physical/VM space on NV50:GF100, see -:ref:`nv50-host-mem`; for GF100+ see :ref:`gf100-host-mem`. +For details on setting up the target physical/VM space on G80:GF100, see +:ref:`g80-host-mem`; for GF100+ see :ref:`gf100-host-mem`. Note that, on NV30:GF100 cards, the PEEPHOLE is subject to PMC hidden window masking - see :ref:`pmc-vram-hide` for details. @@ -104,7 +104,7 @@ The address and data registers are: MMIO 0x001560: PEEPHOLE_W_ADDR [NV30:G84] MMIO 0x060000: PEEPHOLE_W_ADDR [G84:GF100] - The address register. On NV30:NV50, only bits 2-28 are valid. On NV50+, only + The address register. On NV30:G80, only bits 2-28 are valid. On G80+, only bits 2-31 are valid. MMIO 0x001564: PEEPHOLE_W_DATA [NV30:G84] @@ -171,8 +171,8 @@ MMIO 0x06000c: PEEPHOLE_RW_ADDR_HIGH [GF100-] MMIO 0x001570: PEEPHOLE_RW_ADDR [NV30:G84] MMIO 0x060010: PEEPHOLE_RW_ADDR_LOW [G84-] - The low part of the address register. On NV30:NV50, only bits 2-28 are - valid. On NV50+, only bits 2-31 are valid. + The low part of the address register. On NV30:G80, only bits 2-28 are + valid. On G80+, only bits 2-31 are valid. MMIO 0x001574: PEEPHOLE_RW_DATA [NV30:G84] diff --git a/docs/hw/mmio.rst b/docs/hw/mmio.rst index bb0aeafe..b3ae4ffe 100644 --- a/docs/hw/mmio.rst +++ b/docs/hw/mmio.rst @@ -65,65 +65,65 @@ NV1 MMIO map 0x1000000 FB nv1-fb -NV3:NV50 MMIO map +NV3:G80 MMIO map ================= .. space:: 8 nv3-mmio 0x1000000 - 0x000000 PMC pmc 0x001000 PBUS pbus 0x002000 PFIFO nv1-pfifo NV3:NV4 - 0x002000 PFIFO nv4-pfifo NV4:NV50 + 0x002000 PFIFO nv4-pfifo NV4:G80 0x004000 UNK004000 nv3-unk004000 NV3:NV4 0x004000 UNK004000 nv34-unk004000 NV34:NV40 - 0x004000 PCLOCK nv40-pclock NV40:NV50 + 0x004000 PCLOCK nv40-pclock NV40:G80 0x005000 UNK005000 nv4-unk005000 NV4:NV40,IGP4X 0x006000 UNK006000 unk006000 NV20:NV34 0x007000 PRMA prma - 0x008000 PVIDEO pvideo NV10:NV50 + 0x008000 PVIDEO pvideo NV10:G80 0x009000 PTIMER nv3-ptimer 0x00a000 PCOUNTER nv10-pcounter NV10:NV40 - 0x00a000 PCOUNTER nv40-pcounter NV40:NV50 - 0x00b000 PVPE pvpe NV17:NV20,NV30:NV50 - 0x00c000 PCONTROL nv40-pcontrol NV40:NV50 - 0x00d000 PTV ptv NV17:NV20,NV30:NV50 + 0x00a000 PCOUNTER nv40-pcounter NV40:G80 + 0x00b000 PVPE pvpe NV17:NV20,NV30:G80 + 0x00c000 PCONTROL nv40-pcontrol NV40:G80 + 0x00d000 PTV ptv NV17:NV20,NV30:G80 0x00e000 UNK00E000 unk00e000 NV17:NV20 - 0x00f000 PVP1 pvp1 NV41:NV50 - 0x088000 PPCI ppci NV40:NV50 - 0x090000 PFIFO_CACHE nv40-pfifo-cache NV40:NV50 + 0x00f000 PVP1 pvp1 NV41:G80 + 0x088000 PPCI ppci NV40:G80 + 0x090000 PFIFO_CACHE nv40-pfifo-cache NV40:G80 0x0a0000 PRMFB nv3-prmfb 0x0c0000 PRMVIO prmvio NV3:NV40 - 0x0c0000[2/0x2000] PRMVIO prmvio NV40:NV50 + 0x0c0000[2/0x2000] PRMVIO prmvio NV40:G80 0x100000 PFB nv3-pfb NV3:NV10 0x100000 PFB nv10-pfb NV10:NV40&!IGP1X - 0x100000 PFB nv40-pfb NV40:NV50&!TC - 0x100000 PFB nv44-pfb NV44:NV50&TC + 0x100000 PFB nv40-pfb NV40:G80&!TC + 0x100000 PFB nv44-pfb NV44:G80&TC 0x101000 PSTRAPS nv3-pstraps !NV1A 0x102000 UNK102000 nv4e-unk102000 NV63 0x110000 PROM nv3-prom NV3:NV4 0x120000 PALT nv3-palt NV3:NV4 0x200000 PMEDIA pmedia !IGP4X 0x300000 PROM nv3-prom NV4:NV17,NV20:NV25 - 0x300000 PROM nv17-prom NV17:NV20,NV25:NV50&!IGP4X + 0x300000 PROM nv17-prom NV17:NV20,NV25:G80&!IGP4X 0x400000 PGRAPH nv3-pgraph NV3:NV4 0x400000 PGRAPH nv4-pgraph NV4:NV10 0x400000 PGRAPH nv10-pgraph NV10:NV20 0x400000 PGRAPH nv20-pgraph NV20:NV40 - 0x400000 PGRAPH nv40-pgraph NV40:NV50 + 0x400000 PGRAPH nv40-pgraph NV40:G80 0x401000 PDMA nv3-pdma NV3:NV4 0x600000 PCRTC pcrtc NV4:NV11,NV20:NV25 - 0x600000[2/0x2000] PCRTC pcrtc NV11:NV20,NV25:NV50 + 0x600000[2/0x2000] PCRTC pcrtc NV11:NV20,NV25:G80 0x601000 PRMCIO prmcio NV3:NV11,NV20:NV25 - 0x601000[2/0x2000] PRMCIO prmcio NV11:NV20,NV25:NV50 + 0x601000[2/0x2000] PRMCIO prmcio NV11:NV20,NV25:G80 0x680000 PRAMDAC pramdac NV3:NV11,NV20:NV25 - 0x680000[2/0x2000] PRAMDAC pramdac NV11:NV20,NV25:NV50 + 0x680000[2/0x2000] PRAMDAC pramdac NV11:NV20,NV25:G80 0x681000 PRMDIO prmdio NV3:NV11,NV20:NV25 - 0x681000[2/0x2000] PRMDIO prmdio NV11:NV20,NV25:NV50 + 0x681000[2/0x2000] PRMDIO prmdio NV11:NV20,NV25:G80 0x6e0000 UNK6E0000 unk6e0000 NV17:NV40 - 0x700000 PRAMIN nv4-pramin NV4:NV50 + 0x700000 PRAMIN nv4-pramin NV4:G80 0x0800000[chid:0x80][subc:8] USER nv1-user NV3:NV4 0x0800000[chid:0x10][subc:8] USER nv4-user NV4:NV10 - 0x0800000[chid:0x20][subc:8] USER nv4-user NV10:NV50 - 0x0c00000[chid:0x200] DMA_USER nv40-dma-user NV40:NV50 + 0x0800000[chid:0x20][subc:8] USER nv4-user NV10:G80 + 0x0c00000[chid:0x200] DMA_USER nv40-dma-user NV40:G80 .. todo:: check UNK005000 variants [sorta present on NV35, NV34, NV4E, NV63; present on NV5, NV11, NV17, NV1A, NV20; not present on NV44] .. todo:: check PCOUNTER variants @@ -147,23 +147,23 @@ NV3:NV50 MMIO map accessing these ranges. The same applies for NV2x and PVPE. -NV50:GF100 MMIO map +G80:GF100 MMIO map =================== -.. space:: 8 nv50-mmio 0x1000000 - +.. space:: 8 g80-mmio 0x1000000 - 0x000000 PMC pmc * ROOT 0x001000 PBUS pbus * ROOT - 0x002000 PFIFO nv50-pfifo * ROOT - 0x004000 PCLOCK nv50-pclock NV50:GT215 IBUS + 0x002000 PFIFO g80-pfifo * ROOT + 0x004000 PCLOCK g80-pclock G80:GT215 IBUS 0x004000 PCLOCK gt215-pclock GT215:GF100 IBUS 0x007000 PRMA prma * ROOT 0x009000 PTIMER nv3-ptimer * ROOT 0x00a000 PCOUNTER nv40-pcounter * IBUS 0x00b000 PVPE pvpe VP1,VP2 IBUS - 0x00c000 PCONTROL nv50-pcontrol NV50:GT215 IBUS + 0x00c000 PCONTROL g80-pcontrol G80:GT215 IBUS 0x00c000 PCONTROL gt215-pcontrol GT215:GF100 IBUS 0x00e000 PNVIO pnvio * IBUS - 0x00e800 PIOCLOCK nv50-pioclock NV50:GT215 IBUS + 0x00e800 PIOCLOCK g80-pioclock G80:GT215 IBUS 0x00e800 PIOCLOCK gt215-pioclock GT215:GF100 IBUS 0x00f000 PVP1 pvp1 VP1 IBUS 0x00f000 PVP2 pvp2 VP2 IBUS @@ -172,7 +172,7 @@ NV50:GF100 MMIO map 0x021000 PFUSE pfuse * IBUS 0x022000 UNK022000 unk022000 G84: IBUS 0x060000 PEEPHOLE peephole G84: ROOT - 0x070000 PFLUSH nv50-pflush G84:GF100 ROOT + 0x070000 PFLUSH g80-pflush G84:GF100 ROOT 0x080000 PHWSQ_LARGE_CODE phwsq-large-code G92:GF100 ROOT 0x084000 PVLD pvld VP3,VP4 IBUS 0x085000 PVDEC pvdec VP3,VP4 IBUS @@ -181,9 +181,9 @@ NV50:GF100 MMIO map 0x088000 PPCI ppci * IBUS 0x089000 UNK089000 unk089000 G84: IBUS 0x08a000 PPCI_HDA ppci-hda GT215:GF100 IBUS - 0x090000 PFIFO_CACHE nv50-pfifo-cache * ROOT - 0x0a0000 PRMFB nv50-prmfb * ROOT - 0x100000 PFB nv50-pfb * IBUS + 0x090000 PFIFO_CACHE g80-pfifo-cache * ROOT + 0x0a0000 PRMFB g80-prmfb * ROOT + 0x100000 PFB g80-pfb * IBUS 0x101000 PSTRAPS nv3-pstraps * IBUS 0x102000 PCRYPT2 pcrypt2 VP2 IBUS 0x102000 UNK102000 unk102000 IGP ROOT @@ -196,14 +196,14 @@ NV50:GF100 MMIO map 0x200000 PMEDIA pmedia * IBUS 0x280000 UNK280000 unk280000 MCP89 ROOT 0x2ff000 PBRIDGE_PCI pbridge-pci IGP IBUS - 0x300000 PROM nv17-prom NV50:G200 IBUS + 0x300000 PROM nv17-prom G80:G200 IBUS 0x300000 PROM g200-prom G200: IBUS - 0x400000 PGRAPH nv50-pgraph * IBUS - 0x601000 PRMIO nv50-prmio * IBUS - 0x610000 PDISPLAY nv50-pdisplay * IBUS + 0x400000 PGRAPH g80-pgraph * IBUS + 0x601000 PRMIO g80-prmio * IBUS + 0x610000 PDISPLAY g80-pdisplay * IBUS 0x700000 PMEM pmem * ROOT - 0x800000 PIO_USER[subc:8] nv50-pio-user * ROOT - 0xc00000 DMA_USER[chid:0x80] nv50-dma-user * ROOT + 0x800000 PIO_USER[subc:8] g80-pio-user * ROOT + 0xc00000 DMA_USER[chid:0x80] g80-dma-user * ROOT .. todo:: 10f000:112000 range on GT215- @@ -239,7 +239,7 @@ GF100+ MMIO map 0x089000 UNK089000 unk089000 GF100:GK104 HUB 0x08a000 PPCI_HDA ppci-hda * HUB 0x08b000 UNK08B000 unk08b000 GK104: HUB - 0x0a0000 PRMFB nv50-prmfb * ROOT + 0x0a0000 PRMFB g80-prmfb * ROOT 0x100700 PBFB_COMMON pbfb-common 0x100800 PFFB pffb * HUB 0x101000 PSTRAPS nv3-pstraps * HUB @@ -263,8 +263,8 @@ GF100+ MMIO map 0x200000 PMEDIA pmedia * HUB 0x300000 PROM g200-prom * HUB 0x400000 PGRAPH gf100-pgraph - 0x601000 PRMIO nv50-prmio * HUB - 0x610000 PDISPLAY nv50-pdisplay GF100:GF119 HUB + 0x601000 PRMIO g80-prmio * HUB + 0x610000 PDISPLAY g80-pdisplay GF100:GF119 HUB 0x610000 PDISPLAY gf119-pdisplay GF119: HUB 0x700000 PMEM pmem * ROOT 0x800000 PFIFO_CHAN gf100-pfifo-chan GK104: ROOT diff --git a/docs/hw/pciid.rst b/docs/hw/pciid.rst index e877581c..16f43e4c 100644 --- a/docs/hw/pciid.rst +++ b/docs/hw/pciid.rst @@ -703,8 +703,8 @@ device id product .. _pci-ids-g80: -G80 [NV50] ----------- +G80 +--- ========== ======================================================== device id product diff --git a/docs/hw/pcounter/index.rst b/docs/hw/pcounter/index.rst index 9abdfeef..cdf9103e 100644 --- a/docs/hw/pcounter/index.rst +++ b/docs/hw/pcounter/index.rst @@ -9,5 +9,5 @@ Contents: intro nv10 nv40 - nv50 + tesla fermi diff --git a/docs/hw/pcounter/intro.rst b/docs/hw/pcounter/intro.rst index 499bddbc..2c301c65 100644 --- a/docs/hw/pcounter/intro.rst +++ b/docs/hw/pcounter/intro.rst @@ -230,7 +230,7 @@ can be up to 256 signals per domain. The available signals and domains depend heavily on the GPU. The signals are packed tightly, so even a signal common to two GPUs may be at different position between them. The lists of known domains and signals may be found in :ref:`pcounter-signal-nv10`, -:ref:`pcounter-signal-nv40`, :ref:`pcounter-signal-nv50`, :ref:`pcounter-signal-gf100`. +:ref:`pcounter-signal-nv40`, :ref:`pcounter-signal-g80`, :ref:`pcounter-signal-gf100`. .. _pcounter-signal-status: @@ -241,7 +241,7 @@ The STATUS registers The STATUS registers may be used to peek at the current value of each signal. MMIO 0x00a430 + i*0x100 + (j >> 2)*0x200 + (j&3)*4: STATUS[i][j] [NV10:G84] -MMIO 0x00a800 + i*0x20 + j*4: STATUS[i][j] [NV50:GF100] +MMIO 0x00a800 + i*0x20 + j*4: STATUS[i][j] [G80:GF100] MMIO domain_base+0x000 + j*4: STATUS[j] [GF100+] Reading register #j gives current value of signals j*32..j*32+31 as bits 0..31 of the read value. This register is per-domain [i is the domain id] diff --git a/docs/hw/pcounter/nv40.rst b/docs/hw/pcounter/nv40.rst index f31a0ee5..62a00f12 100644 --- a/docs/hw/pcounter/nv40.rst +++ b/docs/hw/pcounter/nv40.rst @@ -1,8 +1,8 @@ .. _pcounter-signal-nv40: -================= -NV40:NV50 signals -================= +================ +NV40:G80 signals +================ .. contents:: diff --git a/docs/hw/pcounter/nv50.rst b/docs/hw/pcounter/tesla.rst index 861d74d8..09969411 100644 --- a/docs/hw/pcounter/nv50.rst +++ b/docs/hw/pcounter/tesla.rst @@ -1,8 +1,8 @@ -.. _pcounter-signal-nv50: +.. _pcounter-signal-g80: -================== -NV50:GF100 signals -================== +================= +G80:GF100 signals +================= .. contents:: @@ -10,7 +10,7 @@ NV50:GF100 signals Introduction ============ -NV50 generation cards have the following counter domains: +G80 generation cards have the following counter domains: - G80: @@ -133,9 +133,9 @@ VCLIP.??? b8 ae ?? ae ae ae ae ?? b8 VCLIP.??? ba b0 ?? b0 b0 b0 b0 ?? ba bc ?? be be ?? VCLIP.CG_IFACE_DISABLE bb -- -- -- -- -- -- -- -- -- -- -- -- -- DISPATCH.??? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ca ?? ?? idle? -PGRAPH.IDLE c8 bd bd bd bd bd bd c9 ?? c9 cb cb cb ?? graph/nv50-pgraph.txt -PGRAPH.INTR ca bf bf bf bf bf bf cb ?? cb cd cd cd ??a graph/nv50-pgraph.txt -CTXCTL.USER d2-d5 c7-ca c7-ca c7-ca c7-ca c7-ca c7-ca d3-d6 d1-d4 d3-d6 d5-d8 d5-d8 d5-d8 d5-d8 graph/nv50-ctxctl.txt +PGRAPH.IDLE c8 bd bd bd bd bd bd c9 ?? c9 cb cb cb ?? graph/g80-pgraph.txt +PGRAPH.INTR ca bf bf bf bf bf bf cb ?? cb cd cd cd ?? graph/g80-pgraph.txt +CTXCTL.USER d2-d5 c7-ca c7-ca c7-ca c7-ca c7-ca c7-ca d3-d6 d1-d4 d3-d6 d5-d8 d5-d8 d5-d8 d5-d8 graph/g80-ctxctl.txt TRAST.??? dc d2 d2 d2 d2 d2 d2 de ?? ?? e0 e0 e0 ?? setup_primitive_count TRAST.??? dd d3 d3 d3 d3 d3 d3 df ?? ?? e1 e1 e1 ?? setup_point_count[0] TRAST.??? de d4 d4 d4 d4 d4 d4 e0 ?? ?? e2 e2 e2 ?? setup_line_count[0] diff --git a/docs/hw/pm/clock.rst b/docs/hw/pm/clock.rst index 67ad6b75..378ae515 100644 --- a/docs/hw/pm/clock.rst +++ b/docs/hw/pm/clock.rst @@ -19,6 +19,6 @@ Contents: nv1-clock nv40-clock - nv50-clock + g80-clock gt215-clock gf100-clock diff --git a/docs/hw/pm/nv50-clock.rst b/docs/hw/pm/g80-clock.rst index 3345cf8d..518a1b43 100644 --- a/docs/hw/pm/nv50-clock.rst +++ b/docs/hw/pm/g80-clock.rst @@ -1,8 +1,8 @@ -.. _nv50-clock: +.. _g80-clock: -================= -NV50:GT215 clocks -================= +================ +G80:GT215 clocks +================ .. contents:: @@ -12,7 +12,7 @@ NV50:GT215 clocks Introduction ============ -NV50:GT215 cards have the following clocks: +G80:GT215 cards have the following clocks: - crystal clock: input from a quartz crystal, user as the base for other clocks @@ -21,11 +21,11 @@ NV50:GT215 cards have the following clocks: - root clocks [RPLL1, RPLL2]: used as the base for other clocks - host clock [HCLK]: clocks the host interface parts, like PFIFO - timer clock [TCLK]: clocks the PTIMER circuitry, only present on G84+ -- NVIO clock [IOCLK]: used for communication with the NVIO chip, NV50 and +- NVIO clock [IOCLK]: used for communication with the NVIO chip, G80 and G200 only - memory clock [MCLK]: used to clock the VRAM, not present on IGPs -- unknown clock 4010: present on NV50, G92, G200 only -- unknown clock 4018: present on NV50, G200 only +- unknown clock 4010: present on G80, G92, G200 only +- unknown clock 4018: present on G80, G200 only - unknown clock 4088: present on G200 only - core clock [NVCLK]: clocks most of the card's logic - shader clock [SCLK]: clocks the CUDA multiprocessor / shader units @@ -47,20 +47,20 @@ and the other clocks are set up in PCLOCK area. MMIO registers ============== -.. space:: 8 nv50-pclock 0x1000 PLL control +.. space:: 8 g80-pclock 0x1000 PLL control .. todo:: write me -.. space:: 8 nv50-pioclock 0x800 I/O PLL control +.. space:: 8 g80-pioclock 0x800 I/O PLL control .. todo:: write me -.. space:: 8 nv50-pcontrol 0x1000 misc clock control +.. space:: 8 g80-pcontrol 0x1000 misc clock control .. todo:: write me -.. _nv50-clock-hclk: +.. _g80-clock-hclk: HCLK: host clock ================ @@ -68,7 +68,7 @@ HCLK: host clock .. todo:: write me -.. _nv50-clock-nvclk: +.. _g80-clock-nvclk: NVCLK: core clock ================= diff --git a/docs/hw/pm/nv40-clock.rst b/docs/hw/pm/nv40-clock.rst index 7f575f89..d4697adb 100644 --- a/docs/hw/pm/nv40-clock.rst +++ b/docs/hw/pm/nv40-clock.rst @@ -1,8 +1,8 @@ .. _nv40-clock: -================ -NV40:NV50 clocks -================ +=============== +NV40:G80 clocks +=============== .. contents:: diff --git a/docs/hw/pm/nv43-therm.rst b/docs/hw/pm/nv43-therm.rst index 85824408..ee51ffd7 100644 --- a/docs/hw/pm/nv43-therm.rst +++ b/docs/hw/pm/nv43-therm.rst @@ -1,7 +1,7 @@ .. _nv43-therm: ============================ -NV43:NV50 thermal monitoring +NV43:G80 thermal monitoring ============================ .. contents:: @@ -10,17 +10,17 @@ NV43:NV50 thermal monitoring Introduction ============ -THERM is an area present in PBUS on NV43:NV50 GPUs. This area is reponsible +THERM is an area present in PBUS on NV43:G80 GPUs. This area is reponsible for temperature monitoring, probably on low-end and middle-range GPUs since high-end cards have been using LM89/ADT7473 for a long time. Beside some configuration knobs, THERM can generate IRQs to the HOST when the temperature goes over a configurable ALARM threshold or outside a configurable -temperature range. This range has been replaced by PTHERM on nv50+ GPUs. +temperature range. This range has been replaced by PTHERM on G80+ GPUs. THERM's MMIO range is 0x15b0:0x15c0. There are two major variants of this range: - NV43:NV47 -- NV47:NV50 +- NV47:G80 .. _nv43-therm-mmio: @@ -43,7 +43,7 @@ MMIO 0x15b0: CFG0 [NV43:NV47] - bit 24: DISABLE - bit 28: ALARM_INTR_EN -MMIO 0x15b0: CFG0 [NV47:NV50] +MMIO 0x15b0: CFG0 [NV47:G80] - bits 0-13: ALARM_HIGH - bits 16-29: SENSOR_OFFSET (signed integer) - bit 30: DISABLE @@ -56,7 +56,7 @@ MMIO 0x15b4: STATUS [NV43:NV47] .. todo:: figure out what divisors are available -MMIO 0x15b4: STATUS [NV47:NV50] +MMIO 0x15b4: STATUS [NV47:G80] - bits 0-13: SENSOR_RAW - bit 16: ALARM_HIGH - bits 26-31: ADC_CLOCK_DIV @@ -71,7 +71,7 @@ MMIO 0x15bc: TEMP_RANGE [NV43:NV47] - bits 0-7: LOW - bits 8-15: HIGH -MMIO 0x15bc: TEMP_RANGE [NV47:NV50] +MMIO 0x15bc: TEMP_RANGE [NV47:G80] - bits 0-13: LOW - bits 16-29: HIGH @@ -82,7 +82,7 @@ The ADC clock The source clock for THERM's ADC is: - NV43:NV47: the host clock -- NV47:NV50: constant (most likely hclck) +- NV47:G80: constant (most likely hclck) (most likely, since the rate doesn't change when I change the HOST clock) @@ -94,7 +94,7 @@ MMIO 0x15b4: STATUS [NV43:NV47] .. todo:: figure out what divisors are available -MMIO 0x15b4: STATUS [NV47:NV50] +MMIO 0x15b4: STATUS [NV47:G80] - bits 26-31: ADC_CLOCK_DIV The division is stored right-shifted 4. The possible division values range from 32 to 2016 with the possibility to completely bypass the divider. @@ -121,7 +121,7 @@ Temperature is read from: MMIO 0x15b4: STATUS [NV43:NV47] bits 0-7: SENSOR_RAW -MMIO 0x15b4: STATUS [NV47:NV50] +MMIO 0x15b4: STATUS [NV47:G80] bits 0-13: SENSOR_RAW SENSOR_RAW is the result of the (signed) addition of the actual value read by @@ -130,7 +130,7 @@ the ADC and SENSOR_OFFSET: MMIO 0x15b0: CFG0 [NV43:NV47] - bits 16-23: SENSOR_OFFSET signed -MMIO 0x15b0: CFG0 [NV47:NV50] +MMIO 0x15b0: CFG0 [NV47:G80] - bits 16-29: SENSOR_OFFSET signed Starting temperature readouts requires to flip a few switches that are @@ -139,7 +139,7 @@ GPU-dependent: MMIO 0x15b0: CFG0 [NV43:NV47] - bit 24: DISABLE -MMIO 0x15b0: CFG0 [NV47:NV50] +MMIO 0x15b0: CFG0 [NV47:G80] - bit 30: DISABLE - mutually exclusive with ENABLE - bit 31: ENABLE - mutually exclusive with DISABLE @@ -171,7 +171,7 @@ MMIO 0x15b0: CFG0 [NV43:NV47] - bits 0-7: ALARM_HIGH - bit 28: ALARM_INTR_EN -MMIO 0x15b0: CFG0 [NV47:NV50] +MMIO 0x15b0: CFG0 [NV47:G80] - bits 0-13: ALARM_HIGH When SENSOR_RAW > ALARM_HIGH, STATUS.ALARM_HIGH is set. @@ -179,7 +179,7 @@ When SENSOR_RAW > ALARM_HIGH, STATUS.ALARM_HIGH is set. MMIO 0x15b4: STATUS [NV43:NV47] - bit 8: ALARM_HIGH -MMIO 0x15b4: STATUS [NV47:NV50] +MMIO 0x15b4: STATUS [NV47:G80] - bit 16: ALARM_HIGH STATUS.ALARM_HIGH is unset as soon as SENSOR_RAW < ALARM_HIGH, without any @@ -199,7 +199,7 @@ MMIO 0x15bc: TEMP_RANGE [NV43:NV47] - bits 0-7: LOW - bits 8-15: HIGH -MMIO 0x15bc: TEMP_RANGE [NV47:NV50] +MMIO 0x15bc: TEMP_RANGE [NV47:G80] - bits 0-13: LOW - bits 16-29: HIGH diff --git a/docs/hw/pm/pdaemon/falcon.rst b/docs/hw/pm/pdaemon/falcon.rst index e7d17bd3..4480ad25 100644 --- a/docs/hw/pm/pdaemon/falcon.rst +++ b/docs/hw/pm/pdaemon/falcon.rst @@ -77,11 +77,11 @@ Core clock: :ref:`gt215-clock-dclk` v2-v4: :ref:`gf100-clock-dclk` -NV50 VM engine: +Tesla VM engine: 0xe -NV50 VM client: +Tesla VM client: 0x11 -NV50 context DMA: +Tesla context DMA: [none] Fermi VM engine: 0x17 diff --git a/docs/hw/pm/ptherm.rst b/docs/hw/pm/ptherm.rst index 7f047ac2..64d1e382 100644 --- a/docs/hw/pm/ptherm.rst +++ b/docs/hw/pm/ptherm.rst @@ -1,8 +1,8 @@ .. _ptherm: -================================================ -NV50+'s Thermal and power monitoring and capping -================================================ +=============================================== +G80+'s Thermal and power monitoring and capping +=============================================== .. contents:: @@ -55,10 +55,10 @@ temperature levels. The meaning of each temperature-level/GPIO should be read from the GPIO table in the VBIOS. Usually, only two temperature thresholds are exposed, ALARM and ALERT. The other one is reserved for a power-related issue. -NV50 ----- +G80 +--- -On NV50, temperature monitoring is very rudimentary and inspired from earlier +On G80, temperature monitoring is very rudimentary and inspired from earlier designs. The internal temperature exposed is the voltage at the pins of the internal diode. Conversion to a temperature in degrees Celsius should be done by the host driver. @@ -103,10 +103,10 @@ PTHERM's behaviour on different temperature scenarios. Temperature management ====================== -NV50 ----- +G80 +--- -On NV50, temperature management is again very rudimentary. It allows specifying +On G80, temperature management is again very rudimentary. It allows specifying 3 temperature thresholds. Critical, High and Low. An activation delay may be set on thresholds to prevent them from oscillating diff --git a/docs/hw/vdec/pvcomp.rst b/docs/hw/vdec/pvcomp.rst index da2f0df3..0d1454c2 100644 --- a/docs/hw/vdec/pvcomp.rst +++ b/docs/hw/vdec/pvcomp.rst @@ -50,11 +50,11 @@ IO addressing type: indexed Core clock: :ref:`gt215-clock-vdclk` -NV50 VM engine: +Tesla VM engine: 7 -NV50 VM client: +Tesla VM client: 0x14 -NV50 context DMA: +Tesla context DMA: 0xa Interrupts: ===== ===== ================== =============== diff --git a/docs/hw/vdec/vp3/pcrypt3.rst b/docs/hw/vdec/vp3/pcrypt3.rst index 7bc9e5c4..b9f42e37 100644 --- a/docs/hw/vdec/vp3/pcrypt3.rst +++ b/docs/hw/vdec/vp3/pcrypt3.rst @@ -43,12 +43,12 @@ Secretful: IO addressing type: indexed Core clock: - :ref:`nv50-clock-nvclk` -NV50 VM engine: + :ref:`g80-clock-nvclk` +Tesla VM engine: 0xa -NV50 VM client: +Tesla VM client: 0x0e -NV50 context DMA: +Tesla context DMA: 0xa Interrupts: ===== ===== ================== =============== diff --git a/docs/hw/vdec/vp3/pppp.rst b/docs/hw/vdec/vp3/pppp.rst index 9a12f2a7..7769719f 100644 --- a/docs/hw/vdec/vp3/pppp.rst +++ b/docs/hw/vdec/vp3/pppp.rst @@ -71,11 +71,11 @@ Core clock: :ref:`gt215-clock-vdclk` v2-v3: :ref:`gf100-clock-vdclk` -NV50 VM engine: +Tesla VM engine: 0x8 -NV50 VM client: +Tesla VM client: 0x06 -NV50 context DMA: +Tesla context DMA: 0x6 Fermi VM engine: 0x11 diff --git a/docs/hw/vdec/vp3/pvdec.rst b/docs/hw/vdec/vp3/pvdec.rst index daef1f46..a655cbd4 100644 --- a/docs/hw/vdec/vp3/pvdec.rst +++ b/docs/hw/vdec/vp3/pvdec.rst @@ -79,11 +79,11 @@ Core clock: :ref:`gt215-clock-vdclk` v2-v3: :ref:`gf100-clock-vdclk` -NV50 VM engine: +Tesla VM engine: 0x1 -NV50 VM client: +Tesla VM client: 0x0c -NV50 context DMA: +Tesla context DMA: 0x4 Fermi VM engine: 0x14 diff --git a/docs/hw/vdec/vp3/pvld.rst b/docs/hw/vdec/vp3/pvld.rst index c5ec1a36..acacb445 100644 --- a/docs/hw/vdec/vp3/pvld.rst +++ b/docs/hw/vdec/vp3/pvld.rst @@ -86,11 +86,11 @@ Core clock: :ref:`gt215-clock-vdclk` v3-v4: :ref:`gf100-clock-vdclk` -NV50 VM engine: +Tesla VM engine: 0x9 -NV50 VM client: +Tesla VM client: 0x0d -NV50 context DMA: +Tesla context DMA: 0x8 Fermi VM engine: 0x10 |