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2015-11-25nvif: modify nvif_unvers/nvif_unpack macros to be more obviousHEADmasterBen Skeggs46-173/+188
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvif: split out client interface definitionsBen Skeggs4-13/+14
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvif: split out device interface definitionsBen Skeggs6-49/+50
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvif: split out ctxdma interface definitionsBen Skeggs12-75/+79
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvif: split out perfmon interface definitionsBen Skeggs5-77/+77
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvif: split out device control interface definitionsBen Skeggs4-49/+49
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvif: split out fifo interface definitionsBen Skeggs23-78/+132
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvif: split out display interface definitionsBen Skeggs30-222/+261
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvif: split out nvsw interface definitonsBen Skeggs7-22/+30
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvif: split out fermi interface definitionsBen Skeggs3-54/+53
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvif: move internal class identifiers to class.hBen Skeggs12-33/+30
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25gr/gm107-: make use of gpc_addr() macro for tpc ramchain setupBen Skeggs2-170/+167
Should be no functional change here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25instmem/gk20a: use DMA API CPU mappingAlexandre Courbot2-92/+62
Commit 69c4938249fb ("drm/nouveau/instmem/gk20a: use direct CPU access") tried to be smart while using the DMA-API by managing the CPU mappings of buffers allocated with the DMA-API by itself. In doing so, it relied on dma_to_phys() which is an architecture-private function not available everywhere. This broke the build on several architectures. Since there is no reliable and portable way to obtain the physical address of a DMA-API buffer, stop trying to be smart and just use the CPU mapping that the DMA-API can provide. This means that buffers will be CPU-mapped for all their life as opposed to when we need them, but anyway using the DMA-API here is a fallback for when no IOMMU is available so we should not expect optimal behavior. This makes the IOMMU and DMA-API implementations of instmem diverge enough that we should maybe put them into separate files... Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25instmem/gk20a: fix race conditionsAlexandre Courbot1-29/+37
The LRU list used for recycling CPU mappings was handling concurrency very poorly. For instance, if an instobj was acquired twice before being released once, it would end up into the LRU list even though there is still a client accessing it. This patch fixes this by properly counting how many clients are currently using a given instobj. While at it, we also raise errors when inconsistencies are detected, and factorize some code. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25gk20a: Add MODULE_FIRMWARE for gk20aNicolas Chauvet1-0/+11
This patch is needed by initramfs tools to detect the required firmware files for the module. This patch tests for either TEGRA_124_SOC or TEGRA_132_SOC for the firmwares related to the Tegra K1 generation. v2: move the MODULE_FIRMWARE to the nvidia_platform.c file. This will avoid to test for NOUVEAU_PLATFORM_DRIVER Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25fifo/gk104: fix engine status register offsetVince Hsu1-1/+1
The offset should be 8 on Kepler and later. Signed-off-by: Vince Hsu <vinceh@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25WIPce/gk104: attempt at better handling of LAUNCHERRBen Skeggs1-4/+50
Very rough, no idea how correct it is at this point, but it prevents getteximage-depth from piglit from hanging the GPU. v2: updated with NV_PCE_FE_LAUNCHERR_REPORT values provided by NVIDIA Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25fifo/gf100: fix race condition when updating engine runlistsBen Skeggs3-7/+26
Similar in spirit to the gk104 fix with a similar title. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25fifo/gk104: fix race condition when updating engine runlistsBen Skeggs3-7/+26
The CPU-side tracking of engine runlists was not protected by a lock, leading to list corruption, eventually causing runlist_update() to overrun the GPU-side runlist, triggering an OOPS. Fixes some of the issues noticed during parallel piglit runs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25nvkm: add/remove 0's to make 7 (or 9)-nibble constants use 8 nibblesIlia Mirkin3-6/+6
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25kms: no need to check for empty edid before drm_detect_hdmi_monitorIlia Mirkin1-1/+0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25core: fix return in error path of device probeAlexandre Courbot1-1/+2
We want to unlock nv_devices_mutex in this error path as well. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25kms: allow 225/297MHz pixel clocks for HDMI on Fermi/KeplerIlia Mirkin1-3/+21
Some Fermi's apparently alow allow 297MHz clocks, so create a parameter which allows end-users to set it themselves until we have a reliable way to determine the board's maximum pixel clocks. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25disp: activate dual link TMDS links only when possibleHauke Mehrtens3-6/+13
Without this patch a pixel clock rate above 165 MHz on a TMDS link is assumed to be dual link. This is true for DVI, but not for HDMI. HDMI supports no dual link, but it supports pixel clock rates above 165 MHz. Only activate Dual Link mode when it is actually possible and requested. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> [imirkin: check for hdmi monitor for computing proto, use sor ctrl to enable extra config bit] Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25volt/pwm/gk104: fix an off-by-one resulting in the voltage not being setlinux-4.4Martin Peres1-1/+1
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-25nvif: allow userspace access to its own client objectBen Skeggs2-2/+7
Regression from "abi16: implement limited interoperability with usif/nvif". Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25gr/gf100-: fix oops when calling zbc methodsBen Skeggs1-2/+2
Somehow missed these two when removing dodgy void casts during the rework. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25gr/gf117-: assume no PPC if NV_PGRAPH_GPC_GPM_PD_PES_TPC_ID_MASK is zeroBen Skeggs3-0/+5
fdo#92761 Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25gr/gf117-: read NV_PGRAPH_GPC_GPM_PD_PES_TPC_ID_MASK from correct GPCBen Skeggs6-897/+897
Each GPCCS unit was reading the mask from GPC0, which causes problems on boards where some GPCs are missing PPCs. Part of the fix for fdo#92761. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25gr/gf100-: split out per-gpc address calculation macroBen Skeggs2-47/+49
There's a few places where we need to access a GPC register from ucode, but outside of the falcon's io address space. To do this we need to calculate the offset based on which GPC we're executing on. This used to be done manually, but we've since found a "base" offset that can be added by the hardware. To use this, an extra bit needs to be set in the register address, which is what this macro achieves. There should be no functional change from this commit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25bios: return actual size of the buffer retrieved via _ROMBen Skeggs1-0/+1
Fixes detection of a failed attempt at fetching the entire ROM image in one-shot (a violation of the spec, that works a lot of the time). Tested on a HP Zbook 15 G2. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25instmem: protect instobj list with a spinlockBen Skeggs2-0/+6
No locking is required for the traversal of this list, as it only happens during suspend/resume where nothing else can be executing. Fixes some of the issues noticed during parallel piglit runs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25pci: enable c800 magic for some unknown Samsung laptopBen Skeggs1-1/+7
fdo#70354 - comment #88. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25pci: enable c800 magic for Clevo P157SMKarol Herbst1-1/+7
this is needed for my gpu Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm: bump patchlevel to indicate availability of abi16/nvif interopBen Skeggs1-1/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03abi16: implement limited interoperability with usif/nvifBen Skeggs3-2/+53
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03abi16: introduce locked variant of nouveau_abi16_get()Ben Skeggs1-5/+13
USIF already takes the client mutex, but will need access to ABI16 data in order to provide some limited interoperability. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03abi16: remove unused argument from nouveau_abi16_get()Ben Skeggs3-9/+8
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03pci: enable c800 magic for Medion Erazer X7827Ilia Mirkin1-0/+1
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91557 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03pci: enable c800 magic for Lenovo Y510PIlia Mirkin1-1/+7
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70354#c75 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03pll/gk104: fix PLL instability due to bad configuration with gddr5Karol Herbst1-23/+77
This patch uses an approach closer to the nvidia driver to configure both PLLs for high gddr5 memory clocks (usually above 2400MHz) Previously nouveau used the one PLL as it was used for the lower clocks and just adjusted the second PLL to get as close as possible to the requested clock. This means for my card, that I got a 4050 MHz clock although 4008 MHz was requested. Now the driver iterates over a list of PLL configuration also used by the nvidia driver and then adjust the second PLL to get near the requested clock. Also it hold to some restriction I found while analyzing the PLL configurations This won't fix all gddr5 high clock issues itself, but it should be fine on hybrid gpu systems as found on many laptops these days. Also switching while normal desktop usage should be a lot more stable than before. v2: move the pll code into ramgk104 Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03clk/g84: Enable reclocking for GDDR3 G94-G200Roy Spliet1-1/+1
Your milage may vary, as it's only been tested on a single G94 and one G96. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03bus/hwsq: Implement VBLANK waiting heuristicRoy Spliet5-2/+41
Avoids waiting for VBLANKS that never arrive on headless or otherwise unconventional set-ups. Strategy taken from MEMX. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03fb/ramnv50: Script changes for G94 and upRoy Spliet1-6/+30
10053c is not even read on some cards, and I have no idea exactly what the criteria are. Likely NVIDIA pre-scans the VBIOS and in their driver disables all features that are never used. The practical effect should be the same as this implementation though. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03fb/ramnv50: Deal with cards without timing entriesRoy Spliet3-7/+50
Like Pierre's G94. We might want to structure Kepler similarly in a follow-up. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03fb/ramnv50: Voltage GPIOsRoy Spliet2-0/+42
Does not seem to be necessary for NVA0, hence untested by me. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03fb/ramgt215: Restructure r111100 calculation for DDR2Roy Spliet1-30/+34
Seems to be mostly equal to DDR3 on < GT218, should improve stability for DDR2 reclocks. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03fb/ramgt215: Change FBVDD/Q when BIOS asks for itRoy Spliet3-0/+20
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03fb/ramgt215: Transform GPIO ramfuc method from FBVREF-specific to genericRoy Spliet2-24/+19
In preparation of changing FBVDDQ, as observed on at least one GDDR3 card. While at it, adhere to func.log[1] properly for consistency. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03bios/rammap: Identify DLLoff for >= GF100Roy Spliet5-12/+39
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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