diff options
| author | Vince Hsu <vinceh@nvidia.com> | 2015-11-16 15:38:30 +0800 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2015-11-25 15:38:13 +1000 |
| commit | 1363dfeae883c1becc527ed5ded46afa8b3264af (patch) | |
| tree | 2b17551f519227f76c67af5a9891a14d5c0101b3 | |
| parent | 492b355843902b2ac23f07e501ace640c176ac30 (diff) | |
fifo/gk104: fix engine status register offset
The offset should be 8 on Kepler and later.
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| -rw-r--r-- | drm/nouveau/nvkm/engine/fifo/gk104.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drm/nouveau/nvkm/engine/fifo/gk104.c b/drm/nouveau/nvkm/engine/fifo/gk104.c index 8d5db6d5..4fcd147d 100644 --- a/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -196,7 +196,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) spin_lock_irqsave(&fifo->base.lock, flags); for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) { - u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); + u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); u32 busy = (stat & 0x80000000); u32 next = (stat & 0x07ff0000) >> 16; u32 chsw = (stat & 0x00008000); |