~currojerez/mesa - Unnamed repository; edit this file to name it for gitweb.

Age	Commit message (Expand)	Author	Files	Lines
2019-09-03	intel/fs/gen12: Use TCS 8_PATCH mode.jenkins	Kenneth Graunke	2	-6/+8
2019-09-03	intel/fs/gen12: Implement gl_FrontFacing on gen12+.	Jason Ekstrand	2	-2/+25
2019-09-03	intel/fs/gen12: Fix barrier codegen.	Francisco Jerez	3	-3/+9
2019-09-03	WIP: intel/ir/gen12: Update assert in brw_stage_has_packed_dispatch().	Francisco Jerez	1	-1/+1
2019-09-03	intel/eu/validate/gen12: Add TGL to eu_validate tests.	Jordan Justen	1	-0/+5
2019-09-03	intel/eu/validate/gen12: Don't blow up on indirect src0.	Jason Ekstrand	1	-1/+2
2019-09-03	intel/eu/validate/gen12: Validation fixes for SEND instruction.	Francisco Jerez	1	-22/+28
2019-09-03	intel/eu/validate/gen12: Fix validation of SYNC instruction.	Francisco Jerez	1	-1/+1
2019-09-03	intel/eu/validate/gen12: Implement integer multiply restrictions in EU valida...	Francisco Jerez	1	-0/+33
2019-09-03	intel/ir: Lower fpow on Gen12.	Jordan Justen	1	-0/+1
2019-09-03	intel/fs/gen12: Don't support source mods for 32x16 integer multiply.	Francisco Jerez	1	-0/+18
2019-09-03	intel/disasm: Disassemble register file of split SEND sources.	Francisco Jerez	1	-1/+4
2019-09-03	intel/disasm: Don't disassemble saturate control on SEND instructions.	Francisco Jerez	1	-2/+4
2019-09-03	intel/disasm/gen12: Disassemble Gen12 SEND instructions.	Francisco Jerez	1	-4/+18
2019-09-03	intel/disasm/gen12: Disassemble Gen12 SYNC instruction.	Francisco Jerez	1	-0/+14
2019-09-03	intel/disasm/gen12: Disassemble three-source instruction source and destinati...	Francisco Jerez	1	-13/+32
2019-09-03	intel/disasm/gen12: Fix disassembly of some common instruction controls.	Francisco Jerez	1	-4/+9
2019-09-03	intel/disasm/gen12: Disassemble software scoreboard information.	Francisco Jerez	1	-0/+16
2019-09-03	intel/fs/gen12: Demodernize software scoreboard lowering pass.	Francisco Jerez	1	-82/+158
2019-09-03	intel/fs/gen12: Introduce software scoreboard lowering pass.	Francisco Jerez	5	-0/+918
2019-09-03	intel/fs/gen12: Add scheduling information to the IR.	Francisco Jerez	2	-0/+3
2019-09-03	intel/eu/gen12: Set SWSB annotations in hand-crafted assembly.	Francisco Jerez	2	-1/+83
2019-09-03	intel/eu/gen12: Add tracking of default SWSB state to the current brw_codegen...	Francisco Jerez	3	-0/+18
2019-09-03	intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.	Francisco Jerez	1	-0/+137
2019-09-03	intel/fs/gen12: Add SYNC IR instruction.	Francisco Jerez	4	-0/+7
2019-09-03	intel/eu/gen12: Add codegen helpers for the SYNC instruction.	Francisco Jerez	3	-3/+15
2019-09-03	intel/eu/gen12: Don't set thread control, it's gone.	Francisco Jerez	1	-2/+4
2019-09-03	intel/eu/gen12: Don't set DD control, it's gone.	Francisco Jerez	2	-6/+12
2019-09-03	intel/eu/gen12: Use SEND instruction for split sends.	Francisco Jerez	1	-1/+1
2019-09-03	intel/eu/gen12: Codegen SEND descriptor regions correctly.	Francisco Jerez	2	-6/+14
2019-09-03	intel/eu/gen12: Codegen pathological SEND source and destination regions.	Francisco Jerez	1	-7/+39
2019-09-03	intel/eu/gen12: Codegen control flow instructions correctly.	Francisco Jerez	1	-6/+9
2019-09-03	intel/eu/gen12: Codegen three-source instruction source and destination regions.	Francisco Jerez	2	-24/+42
2019-09-03	intel/eu/gen12: Fix codegen of immediate source regions.	Francisco Jerez	1	-1/+1
2019-09-03	intel/eu/gen12: Add Gen12 opcode descriptions to the table.	Francisco Jerez	1	-28/+51
2019-09-03	intel/eu/gen12: Implement datatype binary encoding.	Francisco Jerez	1	-7/+55
2019-09-03	intel/eu/gen12: Implement immediate 64 bit constant encoding.	Sagar Ghuge	1	-2/+13
2019-09-03	intel/eu/gen12: Implement compact instruction binary encoding.	Francisco Jerez	1	-39/+49
2019-09-03	intel/eu/gen12: Implement indirect region binary encoding.	Francisco Jerez	1	-8/+15
2019-09-03	intel/eu/gen12: Implement SEND instruction binary encoding.	Francisco Jerez	1	-71/+140
2019-09-03	intel/eu/gen12: Implement control flow instruction binary encoding.	Francisco Jerez	1	-0/+6
2019-09-03	intel/eu/gen12: Implement three-source instruction binary encoding.	Francisco Jerez	1	-67/+85
2019-09-03	intel/eu/gen12: Implement basic instruction binary encoding.	Francisco Jerez	1	-47/+51
2019-09-03	intel/eu/gen12: Add sanity-check asserts to brw_inst_bits() and brw_inst_set_...	Francisco Jerez	1	-0/+2
2019-09-03	intel/eu/gen12: Extend brw_inst.h macros for Gen12 support.	Francisco Jerez	1	-202/+344
2019-09-03	intel/ir: Represent physical edge of unconditional CONTINUE instruction.	Francisco Jerez	1	-0/+2
2019-09-03	intel/ir: Represent physical edge of ELSE instruction.	Francisco Jerez	1	-0/+1
2019-09-03	intel/ir: Represent logical edge of BREAK instruction.	Francisco Jerez	1	-0/+1
2019-09-03	intel/ir: Represent physical and logical subsets of the CFG.	Francisco Jerez	3	-40/+81
2019-09-03	intel/ir: Drop hard-coded correspondence between IR and HW opcodes.	Francisco Jerez	2	-95/+85