diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2019-05-03 16:39:18 -0700 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2019-09-03 12:19:08 -0700 |
| commit | 41d0ff2bec95678bb0adfa11c4be8860734b3beb (patch) | |
| tree | f9c1de549f30c5b40e41c51956d4af848dcb5a37 | |
| parent | 35cbc2c5b232ec02c9816c28ad578a55249dd47b (diff) | |
intel/fs/gen12: Use TCS 8_PATCH mode.jenkins
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
| -rw-r--r-- | src/intel/compiler/brw_compiler.c | 3 | ||||
| -rw-r--r-- | src/intel/compiler/brw_vec4_tcs.cpp | 11 |
2 files changed, 8 insertions, 6 deletions
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index ac2529fc4da..0d3320a609d 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -100,7 +100,8 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false); compiler->use_tcs_8_patch = - devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH); + devinfo->gen >= 12 || + (devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH)); if (devinfo->gen >= 10) { /* We don't support vec4 mode on Cannonlake. */ diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 9d6c4f326a4..3ce5e268e27 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -360,12 +360,13 @@ brw_compile_tcs(const struct brw_compiler *compiler, nir->info.system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID); if (compiler->use_tcs_8_patch && - nir->info.tess.tcs_vertices_out <= 16 && + nir->info.tess.tcs_vertices_out <= (devinfo->gen >= 12 ? 32 : 16) && 2 + has_primitive_id + key->input_vertices <= 31) { - /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, - * the "Instance" field limits the number of output vertices to [1, 16]. - * Secondly, the "Dispatch GRF Start Register for URB Data" field is - * limited to [0, 31] - which imposes a limit on the input vertices. + /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the + * "Instance" field limits the number of output vertices to [1, 16] on + * gen11 and below, or [1, 32] on gen12 and above. Secondly, the + * "Dispatch GRF Start Register for URB Data" field is limited to [0, + * 31] - which imposes a limit on the input vertices. */ vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH; prog_data->instances = nir->info.tess.tcs_vertices_out; |