diff options
| author | Matthew Garrett <mjg59@srcf.ucam.org> | 2007-09-12 17:48:24 +0100 |
|---|---|---|
| committer | Matthew Garrett <mjg59@srcf.ucam.org> | 2007-09-12 17:48:24 +0100 |
| commit | 3f1c9384866c59104f3225dcb44b6e158de30364 (patch) | |
| tree | 8f8ac3e68d621ff115046c475cd5648239eea84f | |
| parent | b554116046a2bb9dfb673ddd3c1a6c88e97a3ad4 (diff) | |
Replace AVIVO_VGA_MYSTERY registers with real names and values
| -rw-r--r-- | include/radeon_reg.h | 16 | ||||
| -rw-r--r-- | xorg/avivo_crtc.c | 8 | ||||
| -rw-r--r-- | xorg/avivo_state.c | 8 |
3 files changed, 24 insertions, 8 deletions
diff --git a/include/radeon_reg.h b/include/radeon_reg.h index ac92ef7..a375295 100644 --- a/include/radeon_reg.h +++ b/include/radeon_reg.h @@ -3181,8 +3181,20 @@ */ #define AVIVO_VGA_MEMORY_BASE 0x0134 #define AVIVO_VGA_FB_START 0x0310 -#define AVIVO_VGA_MYSTERY0 0x0330 -#define AVIVO_VGA_MYSTERY1 0x0338 +#define AVIVO_VGA1_CONTROL 0x0330 + #define AVIVO_VGA1_CONTROL_MODE_ENABLE (1<<0) + #define AVIVO_VGA1_CONTROL_TIMING_SELECT (1<<8) + #define AVIVO_VGA1_CONTROL_SYNC_POLARITY_SELECT (1<<9) + #define AVIVO_VGA1_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) + #define AVIVO_VGA1_CONTROL_OVERSCAN_COLOR_EN (1<<16) + #define AVIVO_VGA1_CONTROL_ROTATE (1<<24) +#define AVIVO_VGA2_CONTROL 0x0338 + #define AVIVO_VGA2_CONTROL_MODE_ENABLE (1<<0) + #define AVIVO_VGA2_CONTROL_TIMING_SELECT (1<<8) + #define AVIVO_VGA2_CONTROL_SYNC_POLARITY_SELECT (1<<9) + #define AVIVO_VGA2_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) + #define AVIVO_VGA2_CONTROL_OVERSCAN_COLOR_EN (1<<16) + #define AVIVO_VGA2_CONTROL_ROTATE (1<<24) /* * We believe reference clock is 108Mhz, we likely can change that using diff --git a/xorg/avivo_crtc.c b/xorg/avivo_crtc.c index c8e358e..0371987 100644 --- a/xorg/avivo_crtc.c +++ b/xorg/avivo_crtc.c @@ -186,6 +186,7 @@ avivo_crtc_mode_set(xf86CrtcPtr crtc, struct avivo_crtc_private *avivo_crtc = crtc->driver_private; struct avivo_info *avivo = avivo_get_info(crtc->scrn); unsigned long fb_location = avivo_crtc->fb_offset + avivo->fb_addr; + int regval; /* compute mode value * TODO: hsync & vsync pol likely not handled properly @@ -240,8 +241,11 @@ avivo_crtc_mode_set(xf86CrtcPtr crtc, /* TODO: find out what this regs truely are for. * last guess: Switch from text to graphics mode. */ - OUTREG(AVIVO_VGA_MYSTERY0, 0x00010600); - OUTREG(AVIVO_VGA_MYSTERY1, 0x00000400); + + regval = (AVIVO_VGA1_CONTROL_SYNC_POLARITY_SELECT | AVIVO_VGA1_CONTROL_OVERSCAN_TIMING_SELECT | AVIVO_VGA1_CONTROL_OVERSCAN_COLOR_EN); + OUTREG(AVIVO_VGA1_CONTROL, regval); + regval = (AVIVO_VGA2_CONTROL_OVERSCAN_TIMING_SELECT); + OUTREG(AVIVO_VGA2_CONTROL, regval); /* setup fb format and location */ diff --git a/xorg/avivo_state.c b/xorg/avivo_state.c index 9e874c2..c0e8565 100644 --- a/xorg/avivo_state.c +++ b/xorg/avivo_state.c @@ -76,8 +76,8 @@ avivo_restore_state(ScrnInfoPtr screen_info) avivo_set_mc(screen_info, AVIVO_MC_MEMORY_MAP, state->mc_memory_map); OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base); OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start); - OUTREG(AVIVO_VGA_MYSTERY0, state->vga_mystery0); - OUTREG(AVIVO_VGA_MYSTERY1, state->vga_mystery1); + OUTREG(AVIVO_VGA1_CONTROL, state->vga_mystery0); + OUTREG(AVIVO_VGA2_CONTROL, state->vga_mystery1); OUTREG(AVIVO_PLL1_POST_DIV_CNTL, state->pll1_post_div_cntl); OUTREG(AVIVO_PLL1_POST_DIV, state->pll1_post_div); @@ -202,8 +202,8 @@ avivo_save_state(ScrnInfoPtr screen_info) state->mc_memory_map = avivo_get_mc(screen_info, AVIVO_MC_MEMORY_MAP); state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); state->vga_fb_start = INREG(AVIVO_VGA_FB_START); - state->vga_mystery0 = INREG(AVIVO_VGA_MYSTERY0); - state->vga_mystery1 = INREG(AVIVO_VGA_MYSTERY1); + state->vga_mystery0 = INREG(AVIVO_VGA1_CONTROL); + state->vga_mystery1 = INREG(AVIVO_VGA2_CONTROL); state->pll1_post_div_cntl = INREG(AVIVO_PLL1_POST_DIV_CNTL); state->pll1_post_div = INREG(AVIVO_PLL1_POST_DIV); |