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| author | Tom St Denis <tom.stdenis@amd.com> | 2019-03-05 11:56:52 -0500 |
|---|---|---|
| committer | Tom St Denis <tom.stdenis@amd.com> | 2019-03-05 11:56:52 -0500 |
| commit | 20fec01d710258a7cf6a72c54689fdeab641e483 (patch) | |
| tree | d6fe519a79c6c4a31a01aadc7231eff4857af45f | |
| parent | efeb1491d58f8b38be63065f9e26d15baa97caf5 (diff) | |
Add ENGINE_CNTL for vcn10
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
| -rw-r--r-- | src/lib/ip/vcn10_bits.i | 4 | ||||
| -rw-r--r-- | src/lib/ip/vcn10_regs.i | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/lib/ip/vcn10_bits.i b/src/lib/ip/vcn10_bits.i index a873402..7e8569d 100644 --- a/src/lib/ip/vcn10_bits.i +++ b/src/lib/ip/vcn10_bits.i @@ -207,6 +207,10 @@ static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA0[] = { static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA1[] = { { "DATA1", 0, 31, &umr_bitfield_default }, }; +static struct umr_bitfield mmUVD_ENGINE_CNTL[] = { + { "ENGINE_START", 0, 0, &umr_bitfield_default }, + { "ENGINE_START_MODE", 1, 1, &umr_bitfield_default }, +}; static struct umr_bitfield mmUVD_UDEC_DBW_UV_ADDR_CONFIG[] = { { "NUM_PIPES", 0, 2, &umr_bitfield_default }, { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, diff --git a/src/lib/ip/vcn10_regs.i b/src/lib/ip/vcn10_regs.i index 88b8786..382ffa0 100644 --- a/src/lib/ip/vcn10_regs.i +++ b/src/lib/ip/vcn10_regs.i @@ -52,6 +52,7 @@ { "mmUVD_GPCOM_VCPU_CMD", REG_MMIO, 0x03c3, 1, &mmUVD_GPCOM_VCPU_CMD[0], sizeof(mmUVD_GPCOM_VCPU_CMD)/sizeof(mmUVD_GPCOM_VCPU_CMD[0]), 0, 0 }, { "mmUVD_GPCOM_VCPU_DATA0", REG_MMIO, 0x03c4, 1, &mmUVD_GPCOM_VCPU_DATA0[0], sizeof(mmUVD_GPCOM_VCPU_DATA0)/sizeof(mmUVD_GPCOM_VCPU_DATA0[0]), 0, 0 }, { "mmUVD_GPCOM_VCPU_DATA1", REG_MMIO, 0x03c5, 1, &mmUVD_GPCOM_VCPU_DATA1[0], sizeof(mmUVD_GPCOM_VCPU_DATA1)/sizeof(mmUVD_GPCOM_VCPU_DATA1[0]), 0, 0 }, + { "mmUVD_ENGINE_CNTL", REG_MMIO, 0x03c6, 1, &mmUVD_ENGINE_CNTL[0], sizeof(mmUVD_ENGINE_CNTL)/sizeof(mmUVD_ENGINE_CNTL[0]), 0, 0 }, { "mmUVD_UDEC_DBW_UV_ADDR_CONFIG", REG_MMIO, 0x03d2, 1, &mmUVD_UDEC_DBW_UV_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DBW_UV_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DBW_UV_ADDR_CONFIG[0]), 0, 0 }, { "mmUVD_UDEC_ADDR_CONFIG", REG_MMIO, 0x03d3, 1, &mmUVD_UDEC_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_ADDR_CONFIG)/sizeof(mmUVD_UDEC_ADDR_CONFIG[0]), 0, 0 }, { "mmUVD_UDEC_DB_ADDR_CONFIG", REG_MMIO, 0x03d4, 1, &mmUVD_UDEC_DB_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DB_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DB_ADDR_CONFIG[0]), 0, 0 }, |