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{ "mmUVD_PGFSM_CONFIG", REG_MMIO, 0x00c0, 1, &mmUVD_PGFSM_CONFIG[0], sizeof(mmUVD_PGFSM_CONFIG)/sizeof(mmUVD_PGFSM_CONFIG[0]), 0, 0 },
{ "mmUVD_PGFSM_STATUS", REG_MMIO, 0x00c1, 1, &mmUVD_PGFSM_STATUS[0], sizeof(mmUVD_PGFSM_STATUS)/sizeof(mmUVD_PGFSM_STATUS[0]), 0, 0 },
{ "mmUVD_POWER_STATUS", REG_MMIO, 0x00c4, 1, &mmUVD_POWER_STATUS[0], sizeof(mmUVD_POWER_STATUS)/sizeof(mmUVD_POWER_STATUS[0]), 0, 0 },
{ "mmCC_UVD_HARVESTING", REG_MMIO, 0x00c7, 1, &mmCC_UVD_HARVESTING[0], sizeof(mmCC_UVD_HARVESTING)/sizeof(mmCC_UVD_HARVESTING[0]), 0, 0 },
{ "mmUVD_DPG_LMA_CTL", REG_MMIO, 0x00d1, 1, &mmUVD_DPG_LMA_CTL[0], sizeof(mmUVD_DPG_LMA_CTL)/sizeof(mmUVD_DPG_LMA_CTL[0]), 0, 0 },
{ "mmUVD_DPG_LMA_DATA", REG_MMIO, 0x00d2, 1, NULL, 0, 0, 0 },
{ "mmUVD_DPG_LMA_MASK", REG_MMIO, 0x00d3, 1, NULL, 0, 0, 0 },
{ "mmUVD_DPG_PAUSE", REG_MMIO, 0x00d4, 1, &mmUVD_DPG_PAUSE[0], sizeof(mmUVD_DPG_PAUSE)/sizeof(mmUVD_DPG_PAUSE[0]), 0, 0 },
{ "mmUVD_SCRATCH1", REG_MMIO, 0x00d5, 1, &mmUVD_SCRATCH1[0], sizeof(mmUVD_SCRATCH1)/sizeof(mmUVD_SCRATCH1[0]), 0, 0 },
{ "mmUVD_SCRATCH2", REG_MMIO, 0x00d6, 1, &mmUVD_SCRATCH2[0], sizeof(mmUVD_SCRATCH2)/sizeof(mmUVD_SCRATCH2[0]), 0, 0 },
{ "mmUVD_SCRATCH3", REG_MMIO, 0x00d7, 1, &mmUVD_SCRATCH3[0], sizeof(mmUVD_SCRATCH3)/sizeof(mmUVD_SCRATCH3[0]), 0, 0 },
{ "mmUVD_SCRATCH4", REG_MMIO, 0x00d8, 1, &mmUVD_SCRATCH4[0], sizeof(mmUVD_SCRATCH4)/sizeof(mmUVD_SCRATCH4[0]), 0, 0 },
{ "mmUVD_SCRATCH5", REG_MMIO, 0x00d9, 1, &mmUVD_SCRATCH5[0], sizeof(mmUVD_SCRATCH5)/sizeof(mmUVD_SCRATCH5[0]), 0, 0 },
{ "mmUVD_SCRATCH6", REG_MMIO, 0x00da, 1, &mmUVD_SCRATCH6[0], sizeof(mmUVD_SCRATCH6)/sizeof(mmUVD_SCRATCH6[0]), 0, 0 },
{ "mmUVD_SCRATCH7", REG_MMIO, 0x00db, 1, &mmUVD_SCRATCH7[0], sizeof(mmUVD_SCRATCH7)/sizeof(mmUVD_SCRATCH7[0]), 0, 0 },
{ "mmUVD_SCRATCH8", REG_MMIO, 0x00dc, 1, &mmUVD_SCRATCH8[0], sizeof(mmUVD_SCRATCH8)/sizeof(mmUVD_SCRATCH8[0]), 0, 0 },
{ "mmUVD_SCRATCH9", REG_MMIO, 0x00dd, 1, &mmUVD_SCRATCH9[0], sizeof(mmUVD_SCRATCH9)/sizeof(mmUVD_SCRATCH9[0]), 0, 0 },
{ "mmUVD_SCRATCH10", REG_MMIO, 0x00de, 1, &mmUVD_SCRATCH10[0], sizeof(mmUVD_SCRATCH10)/sizeof(mmUVD_SCRATCH10[0]), 0, 0 },
{ "mmUVD_SCRATCH11", REG_MMIO, 0x00df, 1, &mmUVD_SCRATCH11[0], sizeof(mmUVD_SCRATCH11)/sizeof(mmUVD_SCRATCH11[0]), 0, 0 },
{ "mmUVD_SCRATCH12", REG_MMIO, 0x00e0, 1, &mmUVD_SCRATCH12[0], sizeof(mmUVD_SCRATCH12)/sizeof(mmUVD_SCRATCH12[0]), 0, 0 },
{ "mmUVD_SCRATCH13", REG_MMIO, 0x00e1, 1, &mmUVD_SCRATCH13[0], sizeof(mmUVD_SCRATCH13)/sizeof(mmUVD_SCRATCH13[0]), 0, 0 },
{ "mmUVD_SCRATCH14", REG_MMIO, 0x00e2, 1, &mmUVD_SCRATCH14[0], sizeof(mmUVD_SCRATCH14)/sizeof(mmUVD_SCRATCH14[0]), 0, 0 },
{ "mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW", REG_MMIO, 0x00e5, 1, &mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW[0], sizeof(mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW)/sizeof(mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW[0]), 0, 0 },
{ "mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH", REG_MMIO, 0x00e6, 1, &mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0], sizeof(mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH)/sizeof(mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0]), 0, 0 },
{ "mmUVD_DPG_VCPU_CACHE_OFFSET0", REG_MMIO, 0x00e7, 1, &mmUVD_DPG_VCPU_CACHE_OFFSET0[0], sizeof(mmUVD_DPG_VCPU_CACHE_OFFSET0)/sizeof(mmUVD_DPG_VCPU_CACHE_OFFSET0[0]), 0, 0 },
{ "mmUVD_LCM_CGC_CNTRL", REG_MMIO, 0x0123, 1, &mmUVD_LCM_CGC_CNTRL[0], sizeof(mmUVD_LCM_CGC_CNTRL)/sizeof(mmUVD_LCM_CGC_CNTRL[0]), 0, 0 },
{ "mmUVD_MIF_CURR_UV_ADDR_CONFIG", REG_MMIO, 0x0184, 1, NULL, 0, 0, 0 },
{ "mmUVD_MIF_REF_UV_ADDR_CONFIG", REG_MMIO, 0x0185, 1, NULL, 0, 0, 0 },
{ "mmUVD_MIF_RECON1_UV_ADDR_CONFIG", REG_MMIO, 0x0186, 1, NULL, 0, 0, 0 },
{ "mmUVD_MIF_CURR_ADDR_CONFIG", REG_MMIO, 0x0192, 1, NULL, 0, 0, 0 },
{ "mmUVD_MIF_REF_ADDR_CONFIG", REG_MMIO, 0x0193, 1, NULL, 0, 0, 0 },
{ "mmUVD_MIF_RECON1_ADDR_CONFIG", REG_MMIO, 0x01c5, 1, NULL, 0, 0, 0 },
{ "mmUVD_JPEG_CNTL", REG_MMIO, 0x0200, 1, &mmUVD_JPEG_CNTL[0], sizeof(mmUVD_JPEG_CNTL)/sizeof(mmUVD_JPEG_CNTL[0]), 0, 0 },
{ "mmUVD_JPEG_RB_BASE", REG_MMIO, 0x0201, 1, &mmUVD_JPEG_RB_BASE[0], sizeof(mmUVD_JPEG_RB_BASE)/sizeof(mmUVD_JPEG_RB_BASE[0]), 0, 0 },
{ "mmUVD_JPEG_RB_WPTR", REG_MMIO, 0x0202, 1, &mmUVD_JPEG_RB_WPTR[0], sizeof(mmUVD_JPEG_RB_WPTR)/sizeof(mmUVD_JPEG_RB_WPTR[0]), 0, 0 },
{ "mmUVD_JPEG_RB_RPTR", REG_MMIO, 0x0203, 1, &mmUVD_JPEG_RB_RPTR[0], sizeof(mmUVD_JPEG_RB_RPTR)/sizeof(mmUVD_JPEG_RB_RPTR[0]), 0, 0 },
{ "mmUVD_JPEG_RB_SIZE", REG_MMIO, 0x0204, 1, &mmUVD_JPEG_RB_SIZE[0], sizeof(mmUVD_JPEG_RB_SIZE)/sizeof(mmUVD_JPEG_RB_SIZE[0]), 0, 0 },
{ "mmUVD_JPEG_ADDR_CONFIG", REG_MMIO, 0x021f, 1, &mmUVD_JPEG_ADDR_CONFIG[0], sizeof(mmUVD_JPEG_ADDR_CONFIG)/sizeof(mmUVD_JPEG_ADDR_CONFIG[0]), 0, 0 },
{ "mmUVD_JPEG_PITCH", REG_MMIO, 0x0222, 1, NULL, 0, 0, 0 },
{ "mmUVD_JPEG_GPCOM_CMD", REG_MMIO, 0x022c, 1, &mmUVD_JPEG_GPCOM_CMD[0], sizeof(mmUVD_JPEG_GPCOM_CMD)/sizeof(mmUVD_JPEG_GPCOM_CMD[0]), 0, 0 },
{ "mmUVD_JPEG_GPCOM_DATA0", REG_MMIO, 0x022d, 1, &mmUVD_JPEG_GPCOM_DATA0[0], sizeof(mmUVD_JPEG_GPCOM_DATA0)/sizeof(mmUVD_JPEG_GPCOM_DATA0[0]), 0, 0 },
{ "mmUVD_JPEG_GPCOM_DATA1", REG_MMIO, 0x022e, 1, &mmUVD_JPEG_GPCOM_DATA1[0], sizeof(mmUVD_JPEG_GPCOM_DATA1)/sizeof(mmUVD_JPEG_GPCOM_DATA1[0]), 0, 0 },
{ "mmUVD_JPEG_JRB_BASE_LO", REG_MMIO, 0x022f, 1, &mmUVD_JPEG_JRB_BASE_LO[0], sizeof(mmUVD_JPEG_JRB_BASE_LO)/sizeof(mmUVD_JPEG_JRB_BASE_LO[0]), 0, 0 },
{ "mmUVD_JPEG_JRB_BASE_HI", REG_MMIO, 0x0230, 1, &mmUVD_JPEG_JRB_BASE_HI[0], sizeof(mmUVD_JPEG_JRB_BASE_HI)/sizeof(mmUVD_JPEG_JRB_BASE_HI[0]), 0, 0 },
{ "mmUVD_JPEG_JRB_SIZE", REG_MMIO, 0x0232, 1, &mmUVD_JPEG_JRB_SIZE[0], sizeof(mmUVD_JPEG_JRB_SIZE)/sizeof(mmUVD_JPEG_JRB_SIZE[0]), 0, 0 },
{ "mmUVD_JPEG_JRB_RPTR", REG_MMIO, 0x0233, 1, &mmUVD_JPEG_JRB_RPTR[0], sizeof(mmUVD_JPEG_JRB_RPTR)/sizeof(mmUVD_JPEG_JRB_RPTR[0]), 0, 0 },
{ "mmUVD_JPEG_JRB_WPTR", REG_MMIO, 0x0234, 1, &mmUVD_JPEG_JRB_WPTR[0], sizeof(mmUVD_JPEG_JRB_WPTR)/sizeof(mmUVD_JPEG_JRB_WPTR[0]), 0, 0 },
{ "mmUVD_JPEG_UV_ADDR_CONFIG", REG_MMIO, 0x0238, 1, &mmUVD_JPEG_UV_ADDR_CONFIG[0], sizeof(mmUVD_JPEG_UV_ADDR_CONFIG)/sizeof(mmUVD_JPEG_UV_ADDR_CONFIG[0]), 0, 0 },
{ "mmUVD_SEMA_ADDR_LOW", REG_MMIO, 0x03c0, 1, &mmUVD_SEMA_ADDR_LOW[0], sizeof(mmUVD_SEMA_ADDR_LOW)/sizeof(mmUVD_SEMA_ADDR_LOW[0]), 0, 0 },
{ "mmUVD_SEMA_ADDR_HIGH", REG_MMIO, 0x03c1, 1, &mmUVD_SEMA_ADDR_HIGH[0], sizeof(mmUVD_SEMA_ADDR_HIGH)/sizeof(mmUVD_SEMA_ADDR_HIGH[0]), 0, 0 },
{ "mmUVD_SEMA_CMD", REG_MMIO, 0x03c2, 1, &mmUVD_SEMA_CMD[0], sizeof(mmUVD_SEMA_CMD)/sizeof(mmUVD_SEMA_CMD[0]), 0, 0 },
{ "mmUVD_GPCOM_VCPU_CMD", REG_MMIO, 0x03c3, 1, &mmUVD_GPCOM_VCPU_CMD[0], sizeof(mmUVD_GPCOM_VCPU_CMD)/sizeof(mmUVD_GPCOM_VCPU_CMD[0]), 0, 0 },
{ "mmUVD_GPCOM_VCPU_DATA0", REG_MMIO, 0x03c4, 1, &mmUVD_GPCOM_VCPU_DATA0[0], sizeof(mmUVD_GPCOM_VCPU_DATA0)/sizeof(mmUVD_GPCOM_VCPU_DATA0[0]), 0, 0 },
{ "mmUVD_GPCOM_VCPU_DATA1", REG_MMIO, 0x03c5, 1, &mmUVD_GPCOM_VCPU_DATA1[0], sizeof(mmUVD_GPCOM_VCPU_DATA1)/sizeof(mmUVD_GPCOM_VCPU_DATA1[0]), 0, 0 },
{ "mmUVD_UDEC_DBW_UV_ADDR_CONFIG", REG_MMIO, 0x03d2, 1, &mmUVD_UDEC_DBW_UV_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DBW_UV_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DBW_UV_ADDR_CONFIG[0]), 0, 0 },
{ "mmUVD_UDEC_ADDR_CONFIG", REG_MMIO, 0x03d3, 1, &mmUVD_UDEC_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_ADDR_CONFIG)/sizeof(mmUVD_UDEC_ADDR_CONFIG[0]), 0, 0 },
{ "mmUVD_UDEC_DB_ADDR_CONFIG", REG_MMIO, 0x03d4, 1, &mmUVD_UDEC_DB_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DB_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DB_ADDR_CONFIG[0]), 0, 0 },
{ "mmUVD_UDEC_DBW_ADDR_CONFIG", REG_MMIO, 0x03d5, 1, &mmUVD_UDEC_DBW_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG[0]), 0, 0 },
{ "mmUVD_SUVD_CGC_GATE", REG_MMIO, 0x03e4, 1, &mmUVD_SUVD_CGC_GATE[0], sizeof(mmUVD_SUVD_CGC_GATE)/sizeof(mmUVD_SUVD_CGC_GATE[0]), 0, 0 },
{ "mmUVD_SUVD_CGC_STATUS", REG_MMIO, 0x03e5, 1, &mmUVD_SUVD_CGC_STATUS[0], sizeof(mmUVD_SUVD_CGC_STATUS)/sizeof(mmUVD_SUVD_CGC_STATUS[0]), 0, 0 },
{ "mmUVD_SUVD_CGC_CTRL", REG_MMIO, 0x03e6, 1, &mmUVD_SUVD_CGC_CTRL[0], sizeof(mmUVD_SUVD_CGC_CTRL)/sizeof(mmUVD_SUVD_CGC_CTRL[0]), 0, 0 },
{ "mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW", REG_MMIO, 0x03ec, 1, &mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW[0]), 0, 0 },
{ "mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH", REG_MMIO, 0x03ed, 1, &mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH[0]), 0, 0 },
{ "mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW", REG_MMIO, 0x03f0, 1, &mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW[0]), 0, 0 },
{ "mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH", REG_MMIO, 0x03f1, 1, &mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH[0]), 0, 0 },
{ "mmUVD_NO_OP", REG_MMIO, 0x03ff, 1, &mmUVD_NO_OP[0], sizeof(mmUVD_NO_OP)/sizeof(mmUVD_NO_OP[0]), 0, 0 },
{ "mmUVD_JPEG_CNTL2", REG_MMIO, 0x0404, 1, NULL, 0, 0, 0 },
{ "mmUVD_VERSION", REG_MMIO, 0x0409, 1, &mmUVD_VERSION[0], sizeof(mmUVD_VERSION)/sizeof(mmUVD_VERSION[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH8", REG_MMIO, 0x040a, 1, &mmUVD_GP_SCRATCH8[0], sizeof(mmUVD_GP_SCRATCH8)/sizeof(mmUVD_GP_SCRATCH8[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH9", REG_MMIO, 0x040b, 1, &mmUVD_GP_SCRATCH9[0], sizeof(mmUVD_GP_SCRATCH9)/sizeof(mmUVD_GP_SCRATCH9[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH10", REG_MMIO, 0x040c, 1, &mmUVD_GP_SCRATCH10[0], sizeof(mmUVD_GP_SCRATCH10)/sizeof(mmUVD_GP_SCRATCH10[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH11", REG_MMIO, 0x040d, 1, &mmUVD_GP_SCRATCH11[0], sizeof(mmUVD_GP_SCRATCH11)/sizeof(mmUVD_GP_SCRATCH11[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH12", REG_MMIO, 0x040e, 1, &mmUVD_GP_SCRATCH12[0], sizeof(mmUVD_GP_SCRATCH12)/sizeof(mmUVD_GP_SCRATCH12[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH13", REG_MMIO, 0x040f, 1, &mmUVD_GP_SCRATCH13[0], sizeof(mmUVD_GP_SCRATCH13)/sizeof(mmUVD_GP_SCRATCH13[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH14", REG_MMIO, 0x0410, 1, &mmUVD_GP_SCRATCH14[0], sizeof(mmUVD_GP_SCRATCH14)/sizeof(mmUVD_GP_SCRATCH14[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH15", REG_MMIO, 0x0411, 1, &mmUVD_GP_SCRATCH15[0], sizeof(mmUVD_GP_SCRATCH15)/sizeof(mmUVD_GP_SCRATCH15[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH16", REG_MMIO, 0x0412, 1, &mmUVD_GP_SCRATCH16[0], sizeof(mmUVD_GP_SCRATCH16)/sizeof(mmUVD_GP_SCRATCH16[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH17", REG_MMIO, 0x0413, 1, &mmUVD_GP_SCRATCH17[0], sizeof(mmUVD_GP_SCRATCH17)/sizeof(mmUVD_GP_SCRATCH17[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH18", REG_MMIO, 0x0414, 1, &mmUVD_GP_SCRATCH18[0], sizeof(mmUVD_GP_SCRATCH18)/sizeof(mmUVD_GP_SCRATCH18[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH19", REG_MMIO, 0x0415, 1, &mmUVD_GP_SCRATCH19[0], sizeof(mmUVD_GP_SCRATCH19)/sizeof(mmUVD_GP_SCRATCH19[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH20", REG_MMIO, 0x0416, 1, &mmUVD_GP_SCRATCH20[0], sizeof(mmUVD_GP_SCRATCH20)/sizeof(mmUVD_GP_SCRATCH20[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH21", REG_MMIO, 0x0417, 1, &mmUVD_GP_SCRATCH21[0], sizeof(mmUVD_GP_SCRATCH21)/sizeof(mmUVD_GP_SCRATCH21[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH22", REG_MMIO, 0x0418, 1, &mmUVD_GP_SCRATCH22[0], sizeof(mmUVD_GP_SCRATCH22)/sizeof(mmUVD_GP_SCRATCH22[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH23", REG_MMIO, 0x0419, 1, &mmUVD_GP_SCRATCH23[0], sizeof(mmUVD_GP_SCRATCH23)/sizeof(mmUVD_GP_SCRATCH23[0]), 0, 0 },
{ "mmUVD_RB_BASE_LO2", REG_MMIO, 0x0421, 1, &mmUVD_RB_BASE_LO2[0], sizeof(mmUVD_RB_BASE_LO2)/sizeof(mmUVD_RB_BASE_LO2[0]), 0, 0 },
{ "mmUVD_RB_BASE_HI2", REG_MMIO, 0x0422, 1, &mmUVD_RB_BASE_HI2[0], sizeof(mmUVD_RB_BASE_HI2)/sizeof(mmUVD_RB_BASE_HI2[0]), 0, 0 },
{ "mmUVD_RB_SIZE2", REG_MMIO, 0x0423, 1, &mmUVD_RB_SIZE2[0], sizeof(mmUVD_RB_SIZE2)/sizeof(mmUVD_RB_SIZE2[0]), 0, 0 },
{ "mmUVD_RB_RPTR2", REG_MMIO, 0x0424, 1, &mmUVD_RB_RPTR2[0], sizeof(mmUVD_RB_RPTR2)/sizeof(mmUVD_RB_RPTR2[0]), 0, 0 },
{ "mmUVD_RB_WPTR2", REG_MMIO, 0x0425, 1, &mmUVD_RB_WPTR2[0], sizeof(mmUVD_RB_WPTR2)/sizeof(mmUVD_RB_WPTR2[0]), 0, 0 },
{ "mmUVD_RB_BASE_LO", REG_MMIO, 0x0426, 1, &mmUVD_RB_BASE_LO[0], sizeof(mmUVD_RB_BASE_LO)/sizeof(mmUVD_RB_BASE_LO[0]), 0, 0 },
{ "mmUVD_RB_BASE_HI", REG_MMIO, 0x0427, 1, &mmUVD_RB_BASE_HI[0], sizeof(mmUVD_RB_BASE_HI)/sizeof(mmUVD_RB_BASE_HI[0]), 0, 0 },
{ "mmUVD_RB_SIZE", REG_MMIO, 0x0428, 1, &mmUVD_RB_SIZE[0], sizeof(mmUVD_RB_SIZE)/sizeof(mmUVD_RB_SIZE[0]), 0, 0 },
{ "mmUVD_RB_RPTR", REG_MMIO, 0x0429, 1, &mmUVD_RB_RPTR[0], sizeof(mmUVD_RB_RPTR)/sizeof(mmUVD_RB_RPTR[0]), 0, 0 },
{ "mmUVD_RB_WPTR", REG_MMIO, 0x042a, 1, &mmUVD_RB_WPTR[0], sizeof(mmUVD_RB_WPTR)/sizeof(mmUVD_RB_WPTR[0]), 0, 0 },
{ "mmUVD_RB_WPTR4", REG_MMIO, 0x0456, 1, &mmUVD_RB_WPTR4[0], sizeof(mmUVD_RB_WPTR4)/sizeof(mmUVD_RB_WPTR4[0]), 0, 0 },
{ "mmUVD_JRBC_RB_RPTR", REG_MMIO, 0x0457, 1, &mmUVD_JRBC_RB_RPTR[0], sizeof(mmUVD_JRBC_RB_RPTR)/sizeof(mmUVD_JRBC_RB_RPTR[0]), 0, 0 },
{ "mmUVD_LMI_JPEG_VMID", REG_MMIO, 0x045d, 1, NULL, 0, 0, 0 },
{ "mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH", REG_MMIO, 0x045e, 1, &mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0]), 0, 0 },
{ "mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW", REG_MMIO, 0x045f, 1, &mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[0]), 0, 0 },
{ "mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH", REG_MMIO, 0x0466, 1, &mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[0]), 0, 0 },
{ "mmUVD_LMI_RBC_IB_64BIT_BAR_LOW", REG_MMIO, 0x0467, 1, &mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[0]), 0, 0 },
{ "mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH", REG_MMIO, 0x0468, 1, &mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[0]), 0, 0 },
{ "mmUVD_LMI_RBC_RB_64BIT_BAR_LOW", REG_MMIO, 0x0469, 1, &mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[0]), 0, 0 },
{ "mmUVD_SEMA_CNTL", REG_MMIO, 0x0500, 1, &mmUVD_SEMA_CNTL[0], sizeof(mmUVD_SEMA_CNTL)/sizeof(mmUVD_SEMA_CNTL[0]), 0, 0 },
{ "mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW", REG_MMIO, 0x0503, 1, &mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW[0]), 0, 0 },
{ "mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH", REG_MMIO, 0x0504, 1, &mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH[0]), 0, 0 },
{ "mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW", REG_MMIO, 0x0505, 1, &mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW[0]), 0, 0 },
{ "mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH", REG_MMIO, 0x0506, 1, &mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH[0]), 0, 0 },
{ "mmUVD_LMI_JRBC_IB_VMID", REG_MMIO, 0x0507, 1, &mmUVD_LMI_JRBC_IB_VMID[0], sizeof(mmUVD_LMI_JRBC_IB_VMID)/sizeof(mmUVD_LMI_JRBC_IB_VMID[0]), 0, 0 },
{ "mmUVD_LMI_JRBC_RB_VMID", REG_MMIO, 0x0508, 1, NULL, 0, 0, 0 },
{ "mmUVD_JRBC_RB_WPTR", REG_MMIO, 0x0509, 1, &mmUVD_JRBC_RB_WPTR[0], sizeof(mmUVD_JRBC_RB_WPTR)/sizeof(mmUVD_JRBC_RB_WPTR[0]), 0, 0 },
{ "mmUVD_JRBC_RB_CNTL", REG_MMIO, 0x050a, 1, &mmUVD_JRBC_RB_CNTL[0], sizeof(mmUVD_JRBC_RB_CNTL)/sizeof(mmUVD_JRBC_RB_CNTL[0]), 0, 0 },
{ "mmUVD_JRBC_IB_SIZE", REG_MMIO, 0x050b, 1, &mmUVD_JRBC_IB_SIZE[0], sizeof(mmUVD_JRBC_IB_SIZE)/sizeof(mmUVD_JRBC_IB_SIZE[0]), 0, 0 },
{ "mmUVD_JRBC_LMI_SWAP_CNTL", REG_MMIO, 0x050d, 1, &mmUVD_JRBC_LMI_SWAP_CNTL[0], sizeof(mmUVD_JRBC_LMI_SWAP_CNTL)/sizeof(mmUVD_JRBC_LMI_SWAP_CNTL[0]), 0, 0 },
{ "mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW", REG_MMIO, 0x050e, 1, NULL, 0, 0, 0 },
{ "mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH", REG_MMIO, 0x050f, 1, NULL, 0, 0, 0 },
{ "mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW", REG_MMIO, 0x0510, 1, NULL, 0, 0, 0 },
{ "mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH", REG_MMIO, 0x0511, 1, NULL, 0, 0, 0 },
{ "mmUVD_JRBC_RB_REF_DATA", REG_MMIO, 0x0512, 1, NULL, 0, 0, 0 },
{ "mmUVD_JRBC_RB_COND_RD_TIMER", REG_MMIO, 0x0513, 1, NULL, 0, 0, 0 },
{ "mmUVD_JRBC_EXTERNAL_REG_BASE", REG_MMIO, 0x0517, 1, NULL, 0, 0, 0 },
{ "mmUVD_JRBC_SOFT_RESET", REG_MMIO, 0x0519, 1, &mmUVD_JRBC_SOFT_RESET[0], sizeof(mmUVD_JRBC_SOFT_RESET)/sizeof(mmUVD_JRBC_SOFT_RESET[0]), 0, 0 },
{ "mmUVD_JRBC_STATUS", REG_MMIO, 0x051a, 1, &mmUVD_JRBC_STATUS[0], sizeof(mmUVD_JRBC_STATUS)/sizeof(mmUVD_JRBC_STATUS[0]), 0, 0 },
{ "mmUVD_RB_RPTR3", REG_MMIO, 0x051b, 1, &mmUVD_RB_RPTR3[0], sizeof(mmUVD_RB_RPTR3)/sizeof(mmUVD_RB_RPTR3[0]), 0, 0 },
{ "mmUVD_RB_WPTR3", REG_MMIO, 0x051c, 1, &mmUVD_RB_WPTR3[0], sizeof(mmUVD_RB_WPTR3)/sizeof(mmUVD_RB_WPTR3[0]), 0, 0 },
{ "mmUVD_RB_BASE_LO3", REG_MMIO, 0x051d, 1, &mmUVD_RB_BASE_LO3[0], sizeof(mmUVD_RB_BASE_LO3)/sizeof(mmUVD_RB_BASE_LO3[0]), 0, 0 },
{ "mmUVD_RB_BASE_HI3", REG_MMIO, 0x051e, 1, &mmUVD_RB_BASE_HI3[0], sizeof(mmUVD_RB_BASE_HI3)/sizeof(mmUVD_RB_BASE_HI3[0]), 0, 0 },
{ "mmUVD_RB_SIZE3", REG_MMIO, 0x051f, 1, &mmUVD_RB_SIZE3[0], sizeof(mmUVD_RB_SIZE3)/sizeof(mmUVD_RB_SIZE3[0]), 0, 0 },
{ "mmJPEG_CGC_GATE", REG_MMIO, 0x0526, 1, &mmJPEG_CGC_GATE[0], sizeof(mmJPEG_CGC_GATE)/sizeof(mmJPEG_CGC_GATE[0]), 0, 0 },
{ "mmUVD_CTX_INDEX", REG_MMIO, 0x0528, 1, &mmUVD_CTX_INDEX[0], sizeof(mmUVD_CTX_INDEX)/sizeof(mmUVD_CTX_INDEX[0]), 0, 0 },
{ "mmUVD_CTX_DATA", REG_MMIO, 0x0529, 1, &mmUVD_CTX_DATA[0], sizeof(mmUVD_CTX_DATA)/sizeof(mmUVD_CTX_DATA[0]), 0, 0 },
{ "mmUVD_CGC_GATE", REG_MMIO, 0x052a, 1, &mmUVD_CGC_GATE[0], sizeof(mmUVD_CGC_GATE)/sizeof(mmUVD_CGC_GATE[0]), 0, 0 },
{ "mmUVD_CGC_STATUS", REG_MMIO, 0x052b, 1, &mmUVD_CGC_STATUS[0], sizeof(mmUVD_CGC_STATUS)/sizeof(mmUVD_CGC_STATUS[0]), 0, 0 },
{ "mmUVD_CGC_CTRL", REG_MMIO, 0x052c, 1, &mmUVD_CGC_CTRL[0], sizeof(mmUVD_CGC_CTRL)/sizeof(mmUVD_CGC_CTRL[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH0", REG_MMIO, 0x0534, 1, &mmUVD_GP_SCRATCH0[0], sizeof(mmUVD_GP_SCRATCH0)/sizeof(mmUVD_GP_SCRATCH0[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH1", REG_MMIO, 0x0535, 1, &mmUVD_GP_SCRATCH1[0], sizeof(mmUVD_GP_SCRATCH1)/sizeof(mmUVD_GP_SCRATCH1[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH2", REG_MMIO, 0x0536, 1, &mmUVD_GP_SCRATCH2[0], sizeof(mmUVD_GP_SCRATCH2)/sizeof(mmUVD_GP_SCRATCH2[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH3", REG_MMIO, 0x0537, 1, &mmUVD_GP_SCRATCH3[0], sizeof(mmUVD_GP_SCRATCH3)/sizeof(mmUVD_GP_SCRATCH3[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH4", REG_MMIO, 0x0538, 1, &mmUVD_GP_SCRATCH4[0], sizeof(mmUVD_GP_SCRATCH4)/sizeof(mmUVD_GP_SCRATCH4[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH5", REG_MMIO, 0x0539, 1, &mmUVD_GP_SCRATCH5[0], sizeof(mmUVD_GP_SCRATCH5)/sizeof(mmUVD_GP_SCRATCH5[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH6", REG_MMIO, 0x053a, 1, &mmUVD_GP_SCRATCH6[0], sizeof(mmUVD_GP_SCRATCH6)/sizeof(mmUVD_GP_SCRATCH6[0]), 0, 0 },
{ "mmUVD_GP_SCRATCH7", REG_MMIO, 0x053b, 1, &mmUVD_GP_SCRATCH7[0], sizeof(mmUVD_GP_SCRATCH7)/sizeof(mmUVD_GP_SCRATCH7[0]), 0, 0 },
{ "mmUVD_LMI_VCPU_CACHE_VMID", REG_MMIO, 0x053c, 1, &mmUVD_LMI_VCPU_CACHE_VMID[0], sizeof(mmUVD_LMI_VCPU_CACHE_VMID)/sizeof(mmUVD_LMI_VCPU_CACHE_VMID[0]), 0, 0 },
{ "mmUVD_LMI_CTRL2", REG_MMIO, 0x053d, 1, &mmUVD_LMI_CTRL2[0], sizeof(mmUVD_LMI_CTRL2)/sizeof(mmUVD_LMI_CTRL2[0]), 0, 0 },
{ "mmUVD_MASTINT_EN", REG_MMIO, 0x0540, 1, &mmUVD_MASTINT_EN[0], sizeof(mmUVD_MASTINT_EN)/sizeof(mmUVD_MASTINT_EN[0]), 0, 0 },
{ "mmUVD_SYS_INT_EN", REG_MMIO, 0x0541, 1, &mmUVD_SYS_INT_EN[0], sizeof(mmUVD_SYS_INT_EN)/sizeof(mmUVD_SYS_INT_EN[0]), 0, 0 },
{ "mmJPEG_CGC_CTRL", REG_MMIO, 0x0565, 1, &mmJPEG_CGC_CTRL[0], sizeof(mmJPEG_CGC_CTRL)/sizeof(mmJPEG_CGC_CTRL[0]), 0, 0 },
{ "mmUVD_LMI_CTRL", REG_MMIO, 0x0566, 1, &mmUVD_LMI_CTRL[0], sizeof(mmUVD_LMI_CTRL)/sizeof(mmUVD_LMI_CTRL[0]), 0, 0 },
{ "mmUVD_LMI_STATUS", REG_MMIO, 0x0567, 1, &mmUVD_LMI_STATUS[0], sizeof(mmUVD_LMI_STATUS)/sizeof(mmUVD_LMI_STATUS[0]), 0, 0 },
{ "mmUVD_LMI_VM_CTRL", REG_MMIO, 0x0568, 1, NULL, 0, 0, 0 },
{ "mmUVD_LMI_SWAP_CNTL", REG_MMIO, 0x056d, 1, &mmUVD_LMI_SWAP_CNTL[0], sizeof(mmUVD_LMI_SWAP_CNTL)/sizeof(mmUVD_LMI_SWAP_CNTL[0]), 0, 0 },
{ "mmUVD_MPC_CNTL", REG_MMIO, 0x0577, 1, &mmUVD_MPC_CNTL[0], sizeof(mmUVD_MPC_CNTL)/sizeof(mmUVD_MPC_CNTL[0]), 0, 0 },
{ "mmUVD_MPC_SET_MUXA0", REG_MMIO, 0x0579, 1, &mmUVD_MPC_SET_MUXA0[0], sizeof(mmUVD_MPC_SET_MUXA0)/sizeof(mmUVD_MPC_SET_MUXA0[0]), 0, 0 },
{ "mmUVD_MPC_SET_MUXA1", REG_MMIO, 0x057a, 1, &mmUVD_MPC_SET_MUXA1[0], sizeof(mmUVD_MPC_SET_MUXA1)/sizeof(mmUVD_MPC_SET_MUXA1[0]), 0, 0 },
{ "mmUVD_MPC_SET_MUXB0", REG_MMIO, 0x057b, 1, &mmUVD_MPC_SET_MUXB0[0], sizeof(mmUVD_MPC_SET_MUXB0)/sizeof(mmUVD_MPC_SET_MUXB0[0]), 0, 0 },
{ "mmUVD_MPC_SET_MUXB1", REG_MMIO, 0x057c, 1, &mmUVD_MPC_SET_MUXB1[0], sizeof(mmUVD_MPC_SET_MUXB1)/sizeof(mmUVD_MPC_SET_MUXB1[0]), 0, 0 },
{ "mmUVD_MPC_SET_MUX", REG_MMIO, 0x057d, 1, &mmUVD_MPC_SET_MUX[0], sizeof(mmUVD_MPC_SET_MUX)/sizeof(mmUVD_MPC_SET_MUX[0]), 0, 0 },
{ "mmUVD_MPC_SET_ALU", REG_MMIO, 0x057e, 1, &mmUVD_MPC_SET_ALU[0], sizeof(mmUVD_MPC_SET_ALU)/sizeof(mmUVD_MPC_SET_ALU[0]), 0, 0 },
{ "mmUVD_GPCOM_SYS_CMD", REG_MMIO, 0x057f, 1, &mmUVD_GPCOM_SYS_CMD[0], sizeof(mmUVD_GPCOM_SYS_CMD)/sizeof(mmUVD_GPCOM_SYS_CMD[0]), 0, 0 },
{ "mmUVD_GPCOM_SYS_DATA0", REG_MMIO, 0x0580, 1, &mmUVD_GPCOM_SYS_DATA0[0], sizeof(mmUVD_GPCOM_SYS_DATA0)/sizeof(mmUVD_GPCOM_SYS_DATA0[0]), 0, 0 },
{ "mmUVD_GPCOM_SYS_DATA1", REG_MMIO, 0x0581, 1, &mmUVD_GPCOM_SYS_DATA1[0], sizeof(mmUVD_GPCOM_SYS_DATA1)/sizeof(mmUVD_GPCOM_SYS_DATA1[0]), 0, 0 },
{ "mmUVD_VCPU_CACHE_OFFSET0", REG_MMIO, 0x0582, 1, &mmUVD_VCPU_CACHE_OFFSET0[0], sizeof(mmUVD_VCPU_CACHE_OFFSET0)/sizeof(mmUVD_VCPU_CACHE_OFFSET0[0]), 0, 0 },
{ "mmUVD_VCPU_CACHE_SIZE0", REG_MMIO, 0x0583, 1, &mmUVD_VCPU_CACHE_SIZE0[0], sizeof(mmUVD_VCPU_CACHE_SIZE0)/sizeof(mmUVD_VCPU_CACHE_SIZE0[0]), 0, 0 },
{ "mmUVD_VCPU_CACHE_OFFSET1", REG_MMIO, 0x0584, 1, &mmUVD_VCPU_CACHE_OFFSET1[0], sizeof(mmUVD_VCPU_CACHE_OFFSET1)/sizeof(mmUVD_VCPU_CACHE_OFFSET1[0]), 0, 0 },
{ "mmUVD_VCPU_CACHE_SIZE1", REG_MMIO, 0x0585, 1, &mmUVD_VCPU_CACHE_SIZE1[0], sizeof(mmUVD_VCPU_CACHE_SIZE1)/sizeof(mmUVD_VCPU_CACHE_SIZE1[0]), 0, 0 },
{ "mmUVD_VCPU_CACHE_OFFSET2", REG_MMIO, 0x0586, 1, &mmUVD_VCPU_CACHE_OFFSET2[0], sizeof(mmUVD_VCPU_CACHE_OFFSET2)/sizeof(mmUVD_VCPU_CACHE_OFFSET2[0]), 0, 0 },
{ "mmUVD_VCPU_CACHE_SIZE2", REG_MMIO, 0x0587, 1, &mmUVD_VCPU_CACHE_SIZE2[0], sizeof(mmUVD_VCPU_CACHE_SIZE2)/sizeof(mmUVD_VCPU_CACHE_SIZE2[0]), 0, 0 },
{ "mmUVD_VCPU_CNTL", REG_MMIO, 0x0598, 1, &mmUVD_VCPU_CNTL[0], sizeof(mmUVD_VCPU_CNTL)/sizeof(mmUVD_VCPU_CNTL[0]), 0, 0 },
{ "mmUVD_SOFT_RESET", REG_MMIO, 0x05a0, 1, &mmUVD_SOFT_RESET[0], sizeof(mmUVD_SOFT_RESET)/sizeof(mmUVD_SOFT_RESET[0]), 0, 0 },
{ "mmUVD_LMI_RBC_IB_VMID", REG_MMIO, 0x05a1, 1, &mmUVD_LMI_RBC_IB_VMID[0], sizeof(mmUVD_LMI_RBC_IB_VMID)/sizeof(mmUVD_LMI_RBC_IB_VMID[0]), 0, 0 },
{ "mmUVD_RBC_IB_SIZE", REG_MMIO, 0x05a2, 1, &mmUVD_RBC_IB_SIZE[0], sizeof(mmUVD_RBC_IB_SIZE)/sizeof(mmUVD_RBC_IB_SIZE[0]), 0, 0 },
{ "mmUVD_RBC_RB_RPTR", REG_MMIO, 0x05a4, 1, &mmUVD_RBC_RB_RPTR[0], sizeof(mmUVD_RBC_RB_RPTR)/sizeof(mmUVD_RBC_RB_RPTR[0]), 0, 0 },
{ "mmUVD_RBC_RB_WPTR", REG_MMIO, 0x05a5, 1, &mmUVD_RBC_RB_WPTR[0], sizeof(mmUVD_RBC_RB_WPTR)/sizeof(mmUVD_RBC_RB_WPTR[0]), 0, 0 },
{ "mmUVD_RBC_RB_WPTR_CNTL", REG_MMIO, 0x05a6, 1, &mmUVD_RBC_RB_WPTR_CNTL[0], sizeof(mmUVD_RBC_RB_WPTR_CNTL)/sizeof(mmUVD_RBC_RB_WPTR_CNTL[0]), 0, 0 },
{ "mmUVD_RBC_RB_CNTL", REG_MMIO, 0x05a9, 1, &mmUVD_RBC_RB_CNTL[0], sizeof(mmUVD_RBC_RB_CNTL)/sizeof(mmUVD_RBC_RB_CNTL[0]), 0, 0 },
{ "mmUVD_RBC_RB_RPTR_ADDR", REG_MMIO, 0x05aa, 1, &mmUVD_RBC_RB_RPTR_ADDR[0], sizeof(mmUVD_RBC_RB_RPTR_ADDR)/sizeof(mmUVD_RBC_RB_RPTR_ADDR[0]), 0, 0 },
{ "mmUVD_STATUS", REG_MMIO, 0x05af, 1, &mmUVD_STATUS[0], sizeof(mmUVD_STATUS)/sizeof(mmUVD_STATUS[0]), 0, 0 },
{ "mmUVD_SEMA_TIMEOUT_STATUS", REG_MMIO, 0x05b0, 1, &mmUVD_SEMA_TIMEOUT_STATUS[0], sizeof(mmUVD_SEMA_TIMEOUT_STATUS)/sizeof(mmUVD_SEMA_TIMEOUT_STATUS[0]), 0, 0 },
{ "mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x05b1, 1, &mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 },
{ "mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL", REG_MMIO, 0x05b2, 1, &mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0]), 0, 0 },
{ "mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x05b3, 1, &mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 },
{ "mmUVD_CONTEXT_ID", REG_MMIO, 0x05bd, 1, &mmUVD_CONTEXT_ID[0], sizeof(mmUVD_CONTEXT_ID)/sizeof(mmUVD_CONTEXT_ID[0]), 0, 0 },
{ "mmUVD_CONTEXT_ID2", REG_MMIO, 0x05bf, 1, &mmUVD_CONTEXT_ID2[0], sizeof(mmUVD_CONTEXT_ID2)/sizeof(mmUVD_CONTEXT_ID2[0]), 0, 0 },
{ "mmUVD_RBC_WPTR_POLL_CNTL", REG_MMIO, 0x05d8, 1, &mmUVD_RBC_WPTR_POLL_CNTL[0], sizeof(mmUVD_RBC_WPTR_POLL_CNTL)/sizeof(mmUVD_RBC_WPTR_POLL_CNTL[0]), 0, 0 },
{ "mmUVD_RBC_WPTR_POLL_ADDR", REG_MMIO, 0x05d9, 1, &mmUVD_RBC_WPTR_POLL_ADDR[0], sizeof(mmUVD_RBC_WPTR_POLL_ADDR)/sizeof(mmUVD_RBC_WPTR_POLL_ADDR[0]), 0, 0 },
{ "mmUVD_RB_BASE_LO4", REG_MMIO, 0x05df, 1, &mmUVD_RB_BASE_LO4[0], sizeof(mmUVD_RB_BASE_LO4)/sizeof(mmUVD_RB_BASE_LO4[0]), 0, 0 },
{ "mmUVD_RB_BASE_HI4", REG_MMIO, 0x05e0, 1, &mmUVD_RB_BASE_HI4[0], sizeof(mmUVD_RB_BASE_HI4)/sizeof(mmUVD_RB_BASE_HI4[0]), 0, 0 },
{ "mmUVD_RB_SIZE4", REG_MMIO, 0x05e1, 1, &mmUVD_RB_SIZE4[0], sizeof(mmUVD_RB_SIZE4)/sizeof(mmUVD_RB_SIZE4[0]), 0, 0 },
{ "mmUVD_RB_RPTR4", REG_MMIO, 0x05e2, 1, &mmUVD_RB_RPTR4[0], sizeof(mmUVD_RB_RPTR4)/sizeof(mmUVD_RB_RPTR4[0]), 0, 0 },
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