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path: root/src/i965_render.c
AgeCommit message (Expand)AuthorFilesLines
2013-09-06Enable the Bay Trail platform.Zhao Halley1-1/+1
2013-06-21Update the supported render target format and pixel formatXiang, Haihao1-2/+2
2013-06-09Update max_wm_threads on HaswellXiang, Haihao1-6/+8
2013-06-09Fix Haswell GT3Xiang, Haihao1-0/+2
2013-04-03Merge branch 'master' into stagingXiang, Haihao1-0/+1
2013-03-15Check the object instance instead of the id for subpicture and imageXiang, Haihao1-20/+18
2013-03-15VPP: check the backing store bufferXiang, Haihao1-2/+6
2013-03-15Render: directly use the backing store bufferXiang, Haihao1-70/+61
2013-03-15Fix the initilization path and the termination path in reverseXiang, Haihao1-5/+3
2013-01-08render: fix rotation vertices for Ironlake.Gwenole Beauchesne1-14/+14
2012-12-28Render: Update the maximum number of WM threadsXiang, Haihao1-6/+23
2012-12-28Render: Update the maximum number of WM threadsXiang, Haihao1-6/+23
2012-12-14Render: Add four subpicture supportLi,Xiaowei1-7/+13
2012-12-14Render: Add global alpha support for subpictureLi,Xiaowei1-0/+29
2012-12-14Render: Add four subpicture supportLi,Xiaowei1-7/+13
2012-12-14Render: Add global alpha support for subpictureLi,Xiaowei1-0/+29
2012-11-01Warning fixesXiang, Haihao1-5/+0
2012-10-31VPP: haswell: fix video post-processing setup.Gwenole Beauchesne1-1/+1
2012-10-23haswell: fix render kernels.Gwenole Beauchesne1-1/+36
2012-10-23haswell: set "Shader Channel Select" fields in surface state.Gwenole Beauchesne1-0/+14
2012-10-23haswell: fix 3DSTATE_PS to fill in number of samples.Gwenole Beauchesne1-1/+3
2012-10-23haswell: fix max PS threads shift value.Gwenole Beauchesne1-1/+6
2012-10-23haswell: use at least 64 URB entries for GT2+.Gwenole Beauchesne1-1/+5
2012-10-23haswell: fix video post-processing setup.Gwenole Beauchesne1-1/+1
2012-10-23haswell: fix render kernels.Gwenole Beauchesne1-1/+36
2012-10-23haswell: set "Shader Channel Select" fields in surface state.Gwenole Beauchesne1-0/+14
2012-10-23haswell: fix 3DSTATE_PS to fill in number of samples.Gwenole Beauchesne1-1/+3
2012-10-23haswell: fix max PS threads shift value.Gwenole Beauchesne1-1/+6
2012-10-23haswell: use at least 64 URB entries for GT2+.Gwenole Beauchesne1-1/+5
2012-10-08Fix build with VA-API 0.32.0.Gwenole Beauchesne1-2/+0
2012-10-04render: fix rotation vertices for Ironlake.Gwenole Beauchesne1-14/+14
2012-09-26Add raw DRM support.Dmitry Ermilov1-1/+1
2012-09-20render: add support for display rotation attribute.Gwenole Beauchesne1-63/+63
2012-09-20render: add support for display rotation attribute.Gwenole Beauchesne1-63/+63
2012-08-06Add raw DRM support.Dmitry Ermilov1-1/+1
2012-04-04render: fix rendering of interlaced surfaces.Gwenole Beauchesne1-39/+84
2012-03-14render: fix rendering of interlaced surfaces.Gwenole Beauchesne1-39/+84
2012-02-07Render YUV400 image on IvybridgeXiang, Haihao1-4/+10
2012-02-07Fix graphics memory allocation for VA surfaceXiang, Haihao1-36/+30
2012-02-07i965_drv_video: support JPEG decoding on IvybridgeXiang, Haihao1-11/+23
2012-01-19Render YUV400 image on IvybridgeXiang, Haihao1-4/+10
2012-01-18Fix graphics memory allocation for VA surfaceXiang, Haihao1-36/+30
2012-01-12Merge branch 'master' into vaapi-extXiang, Haihao1-1/+0
2012-01-10Avoid depending on va_backend.h for some filesXiang, Haihao1-1/+0
2011-12-21i965_drv_video: check the internal format of a surface before renderingXiang, Haihao1-10/+7
2011-09-19silence compiler warningXiang, Haihao1-5/+0
2011-09-08i965_drv_video: support JPEG decoding on IvybridgeXiang, Haihao1-11/+23
2011-08-25i965_drv_video: check the internal format of a surface before renderingXiang, Haihao1-10/+7
2011-08-25New project build rules and files.Gwenole Beauchesne1-1/+1
2011-08-22Moved files around.Gwenole Beauchesne1-0/+3037