diff options
| author | Chao Xie <chao.xie@marvell.com> | 2012-05-07 11:22:23 +0800 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2012-05-07 11:35:00 +0800 |
| commit | 87046f4f3194ac0a795a10f3368ac73c04c633e3 (patch) | |
| tree | 142681e56baadcb7d6d2269c051d7ee8dcc4311c /arch/arm/mach-mmp/include/mach | |
| parent | 5e5661a872600cb4b12d5292160608fb232efdcd (diff) | |
ARM: mmp: add PM support for mmp2
MMP2 can enter system sleep level during suspend.
It can be waken up by PMIC interrupt, RTC/ALARM.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/mach-mmp/include/mach')
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/pm-mmp2.h | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/include/mach/pm-mmp2.h b/arch/arm/mach-mmp/include/mach/pm-mmp2.h new file mode 100644 index 000000000000..98bd66ce8006 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pm-mmp2.h @@ -0,0 +1,61 @@ +/* + * MMP2 Power Management Routines + * + * This software program is licensed subject to the GNU General Public License + * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html + * + * (C) Copyright 2010 Marvell International Ltd. + * All Rights Reserved + */ + +#ifndef __MMP2_PM_H__ +#define __MMP2_PM_H__ + +#include <mach/addr-map.h> + +#define APMU_PJ_IDLE_CFG APMU_REG(0x018) +#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1) +#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5) +#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16) +#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19) +#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28) + +#define APMU_SRAM_PWR_DWN APMU_REG(0x08c) + +#define MPMU_SCCR MPMU_REG(0x038) +#define MPMU_PCR_PJ MPMU_REG(0x1000) +#define MPMU_PCR_PJ_AXISD (1 << 31) +#define MPMU_PCR_PJ_SLPEN (1 << 29) +#define MPMU_PCR_PJ_SPSD (1 << 28) +#define MPMU_PCR_PJ_DDRCORSD (1 << 27) +#define MPMU_PCR_PJ_APBSD (1 << 26) +#define MPMU_PCR_PJ_INTCLR (1 << 24) +#define MPMU_PCR_PJ_SLPWP0 (1 << 23) +#define MPMU_PCR_PJ_SLPWP1 (1 << 22) +#define MPMU_PCR_PJ_SLPWP2 (1 << 21) +#define MPMU_PCR_PJ_SLPWP3 (1 << 20) +#define MPMU_PCR_PJ_VCTCXOSD (1 << 19) +#define MPMU_PCR_PJ_SLPWP4 (1 << 18) +#define MPMU_PCR_PJ_SLPWP5 (1 << 17) +#define MPMU_PCR_PJ_SLPWP6 (1 << 16) +#define MPMU_PCR_PJ_SLPWP7 (1 << 15) + +#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414) +#define MPMU_CGR_PJ MPMU_REG(0x1024) +#define MPMU_WUCRM_PJ MPMU_REG(0x104c) +#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x)) +#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17) + +enum { + POWER_MODE_ACTIVE = 0, + POWER_MODE_CORE_INTIDLE, + POWER_MODE_CORE_EXTIDLE, + POWER_MODE_APPS_IDLE, + POWER_MODE_APPS_SLEEP, + POWER_MODE_CHIP_SLEEP, + POWER_MODE_SYS_SLEEP, +}; + +extern void mmp2_pm_enter_lowpower_mode(int state); +extern int mmp2_set_wake(struct irq_data *d, unsigned int on); +#endif |