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2012-05-28swizzle updatedglsltollvmVincent Lejeune1-5/+56
2012-05-28playing around with llvmVincent Lejeune3-1/+181
2012-05-28starting glsl-to-llvmVincent Lejeune3-1/+7
2012-05-25nv30: Fix generic passing to fragment program in NV34.Roy Spliet3-5/+9
2012-05-25nv30: handle user index buffersChristoph Bumiller4-17/+27
2012-05-25radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard4-34/+36
2012-05-25radeon/llvm: Use tablegen pattern to lower bitconvertTom Stellard4-294/+11
2012-05-25radeon/llvm: Use a custom inserter to lower FNEGTom Stellard5-22/+15
2012-05-25radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard9-84/+41
2012-05-25radeon/llvm: Use a custom inserter to lower FABSTom Stellard10-42/+41
2012-05-25r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswapKai Wasserbäch1-0/+2
2012-05-25draw: fix primitive restart bug by using the index buffer offsetBrian Paul1-3/+6
2012-05-25svga: remove the special zero-stride vertex array codeBrian Paul9-153/+12
2012-05-25gallium/docs: beef up the docs related to color clampingBrian Paul2-3/+18
2012-05-25util: add GALLIUM_LOG_FILE option for logging output to a fileBrian Paul2-6/+25
2012-05-25i965/msaa: Enable 4x MSAA on Gen7.Paul Berry2-9/+9
2012-05-25i965/msaa: Implement manual blending operation for Gen7.Paul Berry1-23/+67
2012-05-25i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.Paul Berry3-68/+151
2012-05-25i965/msaa: Validate Gen7 surface state constraints.Paul Berry3-3/+109
2012-05-25i965/msaa: Properly handle sliced layout for Gen7.Paul Berry10-58/+162
2012-05-25i965/msaa: Add defines for Gen7.Paul Berry1-0/+5
2012-05-25i965/blorp: Enable blorp blits on Gen7.Paul Berry2-2/+4
2012-05-25i965/blorp: Implement proper texel fetch messages for Gen7.Paul Berry2-2/+31
2012-05-25i965/blorp: Use 16 pixel dispatch on Gen7.Paul Berry1-1/+9
2012-05-25i965/blorp: Allocate space for push constants on Gen7.Paul Berry3-30/+28
2012-05-25i965/blorp: Set the dynamic state upper bound.Paul Berry1-1/+6
2012-05-25i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions.Paul Berry3-34/+49
2012-05-25i965/blorp: Use MSDISPMODE_PERSAMPLE rendering when necessaryPaul Berry4-27/+87
2012-05-25i965/blorp: Emit sample index in SAMPLE_LD message when necessaryPaul Berry2-21/+36
2012-05-25i965/blorp: Generalize sampling code in preparation for Gen7Paul Berry1-26/+61
2012-05-25i965/msaa: Expand odd-sized MSAA surfaces to account for interleaving pattern.Paul Berry1-5/+40
2012-05-25gallium/targets: pass ldflags parameter to MKLIBThomas Gstädtner1-1/+1
2012-05-25Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen"Vadim Girlin2-6/+56
2012-05-25radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructionsVadim Girlin1-0/+20
2012-05-25radeon/llvm: prepare to revert the round mode state to defaultVadim Girlin1-2/+9
2012-05-25radeon/llvm: fix sampler index in llvm_emit_texVadim Girlin1-2/+4
2012-05-25radeon/llvm: fix opcode for RECIP_UINT_r600Vadim Girlin1-1/+1
2012-05-25radeon/llvm/loader: convert hardcoded gpu name to optionVadim Girlin1-2/+3
2012-05-25r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operandsVadim Girlin1-0/+2
2012-05-24i915g: Check for geometry shader earlier in i915_set_constant_buffer.Vinson Lee1-4/+4
2012-05-24scons: Fix SCons build infrastructure for FreeBSD.Vinson Lee4-4/+4
2012-05-24radeon/llvm: Lower UDIV using the Selection DAGTom Stellard8-212/+126
2012-05-24radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard14-280/+28
2012-05-24radeon/llvm: Remove AMDIL instructions MULHI, SMULTom Stellard3-10/+5
2012-05-24radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard8-693/+6
2012-05-24radeon/llvm: Remove AMDIL FTOI and ITOF instructionsTom Stellard7-316/+7
2012-05-24radeon/llvm: Remove AMDIL EXP* instructionsTom Stellard5-15/+7
2012-05-24radeon/llvm: Remove AMDIL ADD instructionsTom Stellard6-179/+4
2012-05-24radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)Tom Stellard8-422/+8
2012-05-24radeon/llvm: Remove AMDILMachinePeephole passTom Stellard4-177/+0