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~vlj/mesa
arlfixes
cayman-fix
codesize
constbuf
constbuf2
export
export-vs
glsl-to-llvm
glsl-to-llvm-05nov
glsl-to-llvm-sync2
glsl-to-llvm-wip
glsl-to-llvm2
glsl-to-llvm3
glsltollvm
glsltollvmdump
glsltollvmold
interp
interpolation
interpolation2
interpolation3
intrinsics
llvm-simplification
master
modprop
native
r600-llvm
Mesa clone to host some work
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Author
Files
Lines
2012-05-28
swizzle updated
glsltollvm
Vincent Lejeune
1
-5
/
+56
2012-05-28
playing around with llvm
Vincent Lejeune
3
-1
/
+181
2012-05-28
starting glsl-to-llvm
Vincent Lejeune
3
-1
/
+7
2012-05-25
nv30: Fix generic passing to fragment program in NV34.
Roy Spliet
3
-5
/
+9
2012-05-25
nv30: handle user index buffers
Christoph Bumiller
4
-17
/
+27
2012-05-25
radeon/llvm: Use a custom inserter for MASK_WRITE
Tom Stellard
4
-34
/
+36
2012-05-25
radeon/llvm: Use tablegen pattern to lower bitconvert
Tom Stellard
4
-294
/
+11
2012-05-25
radeon/llvm: Use a custom inserter to lower FNEG
Tom Stellard
5
-22
/
+15
2012-05-25
radeon/llvm: Use a custom inserter to lower CLAMP
Tom Stellard
9
-84
/
+41
2012-05-25
radeon/llvm: Use a custom inserter to lower FABS
Tom Stellard
10
-42
/
+41
2012-05-25
r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswap
Kai Wasserbäch
1
-0
/
+2
2012-05-25
draw: fix primitive restart bug by using the index buffer offset
Brian Paul
1
-3
/
+6
2012-05-25
svga: remove the special zero-stride vertex array code
Brian Paul
9
-153
/
+12
2012-05-25
gallium/docs: beef up the docs related to color clamping
Brian Paul
2
-3
/
+18
2012-05-25
util: add GALLIUM_LOG_FILE option for logging output to a file
Brian Paul
2
-6
/
+25
2012-05-25
i965/msaa: Enable 4x MSAA on Gen7.
Paul Berry
2
-9
/
+9
2012-05-25
i965/msaa: Implement manual blending operation for Gen7.
Paul Berry
1
-23
/
+67
2012-05-25
i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.
Paul Berry
3
-68
/
+151
2012-05-25
i965/msaa: Validate Gen7 surface state constraints.
Paul Berry
3
-3
/
+109
2012-05-25
i965/msaa: Properly handle sliced layout for Gen7.
Paul Berry
10
-58
/
+162
2012-05-25
i965/msaa: Add defines for Gen7.
Paul Berry
1
-0
/
+5
2012-05-25
i965/blorp: Enable blorp blits on Gen7.
Paul Berry
2
-2
/
+4
2012-05-25
i965/blorp: Implement proper texel fetch messages for Gen7.
Paul Berry
2
-2
/
+31
2012-05-25
i965/blorp: Use 16 pixel dispatch on Gen7.
Paul Berry
1
-1
/
+9
2012-05-25
i965/blorp: Allocate space for push constants on Gen7.
Paul Berry
3
-30
/
+28
2012-05-25
i965/blorp: Set the dynamic state upper bound.
Paul Berry
1
-1
/
+6
2012-05-25
i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions.
Paul Berry
3
-34
/
+49
2012-05-25
i965/blorp: Use MSDISPMODE_PERSAMPLE rendering when necessary
Paul Berry
4
-27
/
+87
2012-05-25
i965/blorp: Emit sample index in SAMPLE_LD message when necessary
Paul Berry
2
-21
/
+36
2012-05-25
i965/blorp: Generalize sampling code in preparation for Gen7
Paul Berry
1
-26
/
+61
2012-05-25
i965/msaa: Expand odd-sized MSAA surfaces to account for interleaving pattern.
Paul Berry
1
-5
/
+40
2012-05-25
gallium/targets: pass ldflags parameter to MKLIB
Thomas Gstädtner
1
-1
/
+1
2012-05-25
Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen"
Vadim Girlin
2
-6
/
+56
2012-05-25
radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructions
Vadim Girlin
1
-0
/
+20
2012-05-25
radeon/llvm: prepare to revert the round mode state to default
Vadim Girlin
1
-2
/
+9
2012-05-25
radeon/llvm: fix sampler index in llvm_emit_tex
Vadim Girlin
1
-2
/
+4
2012-05-25
radeon/llvm: fix opcode for RECIP_UINT_r600
Vadim Girlin
1
-1
/
+1
2012-05-25
radeon/llvm/loader: convert hardcoded gpu name to option
Vadim Girlin
1
-2
/
+3
2012-05-25
r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operands
Vadim Girlin
1
-0
/
+2
2012-05-24
i915g: Check for geometry shader earlier in i915_set_constant_buffer.
Vinson Lee
1
-4
/
+4
2012-05-24
scons: Fix SCons build infrastructure for FreeBSD.
Vinson Lee
4
-4
/
+4
2012-05-24
radeon/llvm: Lower UDIV using the Selection DAG
Tom Stellard
8
-212
/
+126
2012-05-24
radeon/llvm: Remove auto-generated AMDIL->ISA conversion code
Tom Stellard
14
-280
/
+28
2012-05-24
radeon/llvm: Remove AMDIL instructions MULHI, SMUL
Tom Stellard
3
-10
/
+5
2012-05-24
radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)
Tom Stellard
8
-693
/
+6
2012-05-24
radeon/llvm: Remove AMDIL FTOI and ITOF instructions
Tom Stellard
7
-316
/
+7
2012-05-24
radeon/llvm: Remove AMDIL EXP* instructions
Tom Stellard
5
-15
/
+7
2012-05-24
radeon/llvm: Remove AMDIL ADD instructions
Tom Stellard
6
-179
/
+4
2012-05-24
radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)
Tom Stellard
8
-422
/
+8
2012-05-24
radeon/llvm: Remove AMDILMachinePeephole pass
Tom Stellard
4
-177
/
+0
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