diff options
| author | Vincent Lejeune <vljn@ovi.com> | 2012-07-20 01:33:50 +0200 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2012-07-20 01:33:50 +0200 |
| commit | 68ed0605c1eec9b93f2d6d85d70dd35543eeca04 (patch) | |
| tree | 7662052c93085bb07aaa9f1b00dc54ab4ffa779a | |
| parent | 2c373ad939d8371556d0e412f3e68ab41dd6fbb7 (diff) | |
fix missing regglsl-to-llvm-sync2
| -rw-r--r-- | src/gallium/drivers/radeon/R600ISelLowering.cpp | 15 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/R600Instructions.td | 6 |
2 files changed, 13 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index 153e1475fb..dcd1ea8595 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -97,21 +97,24 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( MI->getOperand(0).addTargetFlag(MO_FLAG_CLAMP); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV)) .addOperand(MI->getOperand(0)) - .addOperand(MI->getOperand(1)); + .addOperand(MI->getOperand(1)) + .addReg(0); break; case AMDGPU::FABS_R600: MI->getOperand(1).addTargetFlag(MO_FLAG_ABS); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV)) .addOperand(MI->getOperand(0)) - .addOperand(MI->getOperand(1)); + .addOperand(MI->getOperand(1)) + .addReg(0); break; case AMDGPU::FNEG_R600: MI->getOperand(1).addTargetFlag(MO_FLAG_NEG); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV)) .addOperand(MI->getOperand(0)) - .addOperand(MI->getOperand(1)); + .addOperand(MI->getOperand(1)) + .addReg(0); break; case AMDGPU::R600_LOAD_CONST: @@ -156,7 +159,8 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( // this way and it didn't produce the correct results. BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV), ShiftValue) .addReg(AMDGPU::ALU_LITERAL_X) - .addImm(2); + .addImm(2) + .addReg(0); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr) .addOperand(MI->getOperand(1)) .addReg(ShiftValue); @@ -278,7 +282,8 @@ void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBl BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::MOV), PtrReg) .addReg(AMDGPU::ALU_LITERAL_X) - .addImm(dword_offset * 4); + .addImm(dword_offset * 4) + .addReg(0); BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::VTX_READ_PARAM_i32_eg)) .addOperand(MI->getOperand(0)) diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index 2cdc949eb9..3c8a67f4dd 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -77,7 +77,7 @@ class R600_1OP <bits<32> inst, string opName, list<dag> pattern, InstrItinClass itin = AnyALU> : InstR600 <inst, (outs R600_Reg32:$dst), - (ins R600_Reg32:$src, R600_Pred:$p), + (ins R600_Reg32:$src, R600_Pred:$p, variable_ops), !strconcat(opName, " $dst, $src ($p)"), pattern, itin @@ -87,7 +87,7 @@ class R600_2OP <bits<32> inst, string opName, list<dag> pattern, InstrItinClass itin = AnyALU> : InstR600 <inst, (outs R600_Reg32:$dst), - (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops), + (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops), !strconcat(opName, " $dst, $src0, $src1"), pattern, itin @@ -97,7 +97,7 @@ class R600_3OP <bits<32> inst, string opName, list<dag> pattern, InstrItinClass itin = AnyALU> : InstR600 <inst, (outs R600_Reg32:$dst), - (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops), + (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops), !strconcat(opName, " $dst, $src0, $src1, $src2"), pattern, itin>{ |