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2012-10-11Merge master branchtstellar4-1/+60
2012-10-02Merge master branchtstellar2-1/+109
2012-10-02Merge master branchtstellar1-0/+36
2012-10-02Merge TOTtstellar2-0/+47
2012-09-24Emit dtors into proper section while compiling in vcpp-compatible mode.tstellar1-6/+17
2012-09-24Fix edge cases of ARM shift operands in arith instructions.tstellar2-0/+88
2012-09-24Fix the handling of edge cases in ARM shifted operands.tstellar2-0/+116
2012-09-19Add support for macro parameters/arguments delimited by spaces,pgurd2-8/+50
2012-09-19Support default parameters/arguments for assembler macros.pgurd1-2/+10
2012-09-19Enhance unmatched '.endr' directive error message in assembler.pgurd1-1/+1
2012-09-19llvm/test/MC/X86/x86_nop.s: Make sure -arch=x86 when -mcpu=geode.chapuni1-1/+1
2012-09-18Add test for r164132.rdivacky1-0/+7
2012-09-13Assembler: Darwin variables defined via .set are no-dead-strip.grosbach1-0/+158
2012-09-10Add newline.Chad Rosier1-1/+1
2012-09-10[ms-inline asm] Add support for .att_syntax directive.Chad Rosier1-2/+4
2012-09-07Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer1-0/+13
2012-09-07Initial relocations test for the Mips standalone assembler.Jack Carter1-0/+41
2012-09-07MC: Overhaul handling of .lcommBenjamin Kramer3-4/+30
2012-09-07PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for regi...Benjamin Kramer1-0/+18
2012-09-07The Mips standalone assembler aliased instruction support.Jack Carter2-0/+27
2012-09-07The Mips standalone assembler intial directive support.Jack Carter1-0/+10
2012-09-07The Mips standalone assembler fpu instruction support.Jack Carter2-0/+166
2012-09-06The Mips standalone assembler memory instruction support.Jack Carter1-0/+41
2012-09-06Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2-2/+6
2012-09-06Check for invalid alignment values when decoding VLDn/VSTn (single ln) instru...Tim Northover5-0/+93
2012-09-06Use correct part of complex operand to encode VST1 alignment.Tim Northover1-0/+77
2012-09-06Mips specific llvm assembler support for branch and jump instructions.Jack Carter1-0/+64
2012-09-05Mips specific llvm assembler support for ALU instructions. This includesJack Carter1-0/+81
2012-08-31The instruction DINS may be transformed into DINSU or DEXTM dependingJack Carter1-0/+29
2012-08-31X86: Fix encoding of 'movd %xmm0, %rax'Jim Grosbach1-0/+4
2012-08-28The instruction DEXT may be transformed into DEXTU or DEXTM dependingJack Carter1-0/+28
2012-08-28Some instructions are passed to the assembler to beJack Carter1-1/+4
2012-08-28Fix mips' long branch pass.Akira Hatanaka1-2/+5
2012-08-22Add option disable-mips-delay-filler. Turn on mips' delay slot filler byAkira Hatanaka3-4/+4
2012-08-22For mips64 switch statements in subroutines could generate Jack Carter1-0/+39
2012-08-21Fix macros arguments with an underscore, dot or dollar in them. This is basedRafael Espindola1-0/+21
2012-08-21Make the wording in of the "expected identifier" error in the .macro directiveRafael Espindola1-0/+9
2012-08-13ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.Jim Grosbach2-8/+10
2012-08-12Give this test an explicit triple.Nick Lewycky1-1/+1
2012-08-12When emitting the PC range in an FDE, use the same data encoding for both endsNick Lewycky1-0/+28
2012-08-09Another 32 to 64 bit sign extension bug.Jack Carter1-4/+9
2012-08-08llvm/test/MC/COFF/seh.s: Fixup corresponding to r161487.NAKAMURA Takumi1-1/+0
2012-08-08Add `.pushsection', `.popsection', and `.previous' directives to Darwin ASM.Bill Wendling2-0/+29
2012-08-07The define for 64 bit sign extension neglected to Jack Carter1-0/+15
2012-08-06The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64 Jack Carter1-0/+18
2012-08-06Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.Jack Carter1-0/+27
2012-08-02Support fpv4 for ARM Cortex-M4.Jiangning Liu1-0/+4
2012-08-02Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ...Jiangning Liu2-1/+23
2012-08-02Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu4-33/+235
2012-08-02Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu4-0/+18
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