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2012-11-29R600: Fold immediates into ALU instructions when possible v2Tom Stellard3-1/+116
2012-11-29AMDGPU: Remove or document commented out codeTom Stellard4-92/+13
2012-11-29AMDGPU: Fix 4-space indentationTom Stellard3-73/+73
2012-11-29AMDGPU: Remove unused macros v2Tom Stellard6-100/+19
2012-11-29AMDGPU: Coding style - put braces on same line as function headersTom Stellard27-458/+229
2012-11-29AMDGPU: Simplify SI control flow loweringChristian König1-41/+38
2012-11-29AMDGPU: Fix S_*_SAVEEXEC_B64 definesChristian König1-2/+8
2012-11-29R600: rename if/break operator to improve readabilityVincent Lejeune4-61/+29
2012-11-29R600: do not use magic number for resourceIdVincent Lejeune4-53/+60
2012-11-29R600: add fsqrt pattern for r600/r700Vincent Lejeune1-0/+3
2012-11-29R600: Valid pixel mode and EOP were inverted in exportVincent Lejeune1-2/+2
2012-11-29SI: Use IMAGE_SAMPLE_L for the SI.sample.lod intrinsic.Michel Dänzer1-2/+2
2012-11-16AMDGPU: Fix name of SI control flow lowering source file.Michel Dänzer1-1/+1
2012-11-16AMDGPU: Don't allow using SI SGPRs 102 and 103 directly.Michel Dänzer1-2/+2
2012-11-16AMDGPU: Fix string concatenation in AMDGPUInstPrinter::printRel().Michel Dänzer1-1/+1
2012-11-16R600: replaces fragment input with negative index with undef valuesVincent Lejeune1-3/+9
2012-11-16R600: Fix operand index table for OP3 instructionsTom Stellard1-1/+1
2012-11-16AMDGPU: Print integer and floating point values for literalsTom Stellard3-1/+13
2012-11-16R600: Add helper function for setting instruction modifiersTom Stellard3-9/+16
2012-11-13AMDGPU: Fix builds with -DNDEBUGtstellar1-0/+2
2012-11-13R600: Fix sampler->resource_id mappingtstellar1-2/+2
2012-11-13SI: s/flow control/control flow/g .tstellar4-15/+15
2012-11-13SI: fix SGPR liveness v4tstellar4-0/+191
2012-11-13SI: Add intrinsic for sampling with explicit LOD.tstellar2-1/+9
2012-11-13SI: Add intrinsic for sampling with bias.tstellar2-1/+9
2012-11-13SI: Update flow control comments to match current code.tstellar1-4/+5
2012-11-13SI: Only allow SGPR for the first operand of VOP3 instructions.tstellar2-4/+4
2012-10-31SI: Enable control flow pass againtstellar1-2/+1
2012-10-31SI: Handle kilp intrinsictstellar1-0/+5
2012-10-31SI: Use SReg_1 class for SI_IF_(N)Z condition code operandtstellar1-3/+3
2012-10-31SI: Prevent instructions modifying the EXEC register from being movedtstellar2-0/+6
2012-10-31SI: Handle more cases in copyPhysReg callbacktstellar1-3/+15
2012-10-31SI: Alternative handling of EXEC register for control flowtstellar2-26/+36
2012-10-31SI: Use SReg_64RegClass for i64 register clasststellar1-1/+1
2012-10-31R600: use specialised R600.store.pixel.* for fragment shadertstellar8-2/+185
2012-10-26R600: Add a v4f32 to v4i32 BitConvert patterntstellar1-0/+1
2012-10-26R600: Set isBarrier bit for JUMP instructiontstellar1-2/+2
2012-10-25SI: Add intrinsic for reading the FRONT_FACE VGPR.tstellar2-0/+6
2012-10-25SI: Use 64-bit encoding for V_CMP instructionststellar6-51/+155
2012-10-22R600: Cayman uses vector instruction for SIN/COS/RECIP_CLAMPED_RECIPSQRT_IEEEtstellar1-10/+20
2012-10-22R600: turn select into select_cctstellar2-0/+17
2012-10-22R600: add support for vector setCCtstellar1-4/+2
2012-10-22R600: Remove input.face and input.position intrinsicststellar3-40/+0
2012-10-22R600: Add super reg to reserved reg listtstellar1-0/+3
2012-10-22R600: interp instructions emits native outputststellar3-38/+27
2012-10-22AMDGPU: Fix build after mergetstellar1-1/+1
2012-10-19R600: Remove deprecated code from R600MCCodeEmitterHEADmastertstellar1-129/+9
2012-10-19R600: Use native operands for KILLGT instructiontstellar4-38/+29
2012-10-19R600: Use native operands for CUBE*, DOT4* instructionststellar3-68/+46
2012-10-19R600: Organize pseudo instruction in R600Instructions.tdtstellar1-27/+10
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