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-rw-r--r--lib/Target/AMDGPU/AMDGPUISelLowering.cpp3
-rw-r--r--lib/Target/AMDGPU/AMDILIntrinsics.td1
2 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index f44e3d3605..14477547af 100644
--- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -36,6 +36,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::FEXP2, MVT::f32, Legal);
setOperationAction(ISD::FPOW, MVT::f32, Legal);
setOperationAction(ISD::FLOG2, MVT::f32, Legal);
+ setOperationAction(ISD::FABS, MVT::f32, Legal);
setOperationAction(ISD::FRINT, MVT::f32, Legal);
setOperationAction(ISD::UDIV, MVT::i32, Expand);
@@ -110,8 +111,6 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return LowerIntrinsicIABS(Op, DAG);
case AMDGPUIntrinsic::AMDIL_exp:
return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
- case AMDGPUIntrinsic::AMDIL_fabs:
- return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
case AMDGPUIntrinsic::AMDGPU_lrp:
return LowerIntrinsicLRP(Op, DAG);
case AMDGPUIntrinsic::AMDIL_fraction:
diff --git a/lib/Target/AMDGPU/AMDILIntrinsics.td b/lib/Target/AMDGPU/AMDILIntrinsics.td
index 4de5767427..213c8bbfbb 100644
--- a/lib/Target/AMDGPU/AMDILIntrinsics.td
+++ b/lib/Target/AMDGPU/AMDILIntrinsics.td
@@ -66,7 +66,6 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
}
let TargetPrefix = "AMDIL", isTarget = 1 in {
- def int_AMDIL_fabs : GCCBuiltin<"__amdil_fabs">, UnaryIntFloat;
def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt;
def int_AMDIL_bit_extract_i32 : GCCBuiltin<"__amdil_ibit_extract">,