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-rw-r--r--lib/Target/AMDGPU/R600InstrInfo.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/R600InstrInfo.h b/lib/Target/AMDGPU/R600InstrInfo.h
index cec1c3bd38..81e1828e9b 100644
--- a/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/lib/Target/AMDGPU/R600InstrInfo.h
@@ -50,6 +50,9 @@ namespace llvm {
bool isReductionOp(unsigned opcode) const;
bool isCubeOp(unsigned opcode) const;
+ /// isALUInstr - Returns true if this Opcode represents an ALU instruction.
+ bool isALUInstr(unsigned Opcode) const;
+
/// isVector - Vector instructions are instructions that must fill all
/// instruction slots within an instruction group.
bool isVector(const MachineInstr &MI) const;
@@ -130,6 +133,10 @@ namespace llvm {
/// if the Instruction does not contain the specified Op.
int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
+ /// getOperandIdx - Get the index of Op for the given Opcode. Returns -1
+ /// if the Instruction does not contain the specified Op.
+ int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
+
/// setImmOperand - Helper function for setting instruction flag values.
void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;