diff options
| author | Christian König <deathsimple@vodafone.de> | 2012-12-11 18:43:08 +0100 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-12-14 14:25:59 +0000 |
| commit | 120513d82e70a95ab38086216199e6cd32819355 (patch) | |
| tree | 4e05cb71f58dbff65d61445d65a25c0bc84fe954 | |
| parent | a881158b24beec4e3b7a6883e54d34e6aea9085e (diff) | |
R600: Remove unecessary VREG alignment.
Unlike SGPRs VGPRs doesn't need to be aligned.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
| -rw-r--r-- | lib/Target/AMDGPU/SIRegisterInfo.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/AMDGPU/SIRegisterInfo.td b/lib/Target/AMDGPU/SIRegisterInfo.td index e52311ab8a..c3f136191a 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/lib/Target/AMDGPU/SIRegisterInfo.td @@ -105,15 +105,15 @@ def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32, // VGPR 64-bit registers def VGPR_64 : RegisterTuples<[low, high], - [(add (decimate VGPR_32, 2)), - (add (decimate (rotl VGPR_32, 1), 2))]>; + [(add VGPR_32), + (add (rotl VGPR_32, 1))]>; // VGPR 128-bit registers def VGPR_128 : RegisterTuples<[sel_x, sel_y, sel_z, sel_w], - [(add (decimate VGPR_32, 4)), - (add (decimate (rotl VGPR_32, 1), 4)), - (add (decimate (rotl VGPR_32, 2), 4)), - (add (decimate (rotl VGPR_32, 3), 4))]>; + [(add VGPR_32), + (add (rotl VGPR_32, 1)), + (add (rotl VGPR_32, 2)), + (add (rotl VGPR_32, 3))]>; // Register class for all scalar registers (SGPRs + Special Registers) def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, |