From 120513d82e70a95ab38086216199e6cd32819355 Mon Sep 17 00:00:00 2001 From: Christian König Date: Tue, 11 Dec 2012 18:43:08 +0100 Subject: R600: Remove unecessary VREG alignment. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unlike SGPRs VGPRs doesn't need to be aligned. Reviewed-by: Tom Stellard Tested-by: Michel Dänzer Signed-off-by: Christian König --- lib/Target/AMDGPU/SIRegisterInfo.td | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/Target/AMDGPU/SIRegisterInfo.td b/lib/Target/AMDGPU/SIRegisterInfo.td index e52311ab8a..c3f136191a 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/lib/Target/AMDGPU/SIRegisterInfo.td @@ -105,15 +105,15 @@ def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32, // VGPR 64-bit registers def VGPR_64 : RegisterTuples<[low, high], - [(add (decimate VGPR_32, 2)), - (add (decimate (rotl VGPR_32, 1), 2))]>; + [(add VGPR_32), + (add (rotl VGPR_32, 1))]>; // VGPR 128-bit registers def VGPR_128 : RegisterTuples<[sel_x, sel_y, sel_z, sel_w], - [(add (decimate VGPR_32, 4)), - (add (decimate (rotl VGPR_32, 1), 4)), - (add (decimate (rotl VGPR_32, 2), 4)), - (add (decimate (rotl VGPR_32, 3), 4))]>; + [(add VGPR_32), + (add (rotl VGPR_32, 1)), + (add (rotl VGPR_32, 2)), + (add (rotl VGPR_32, 3))]>; // Register class for all scalar registers (SGPRs + Special Registers) def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, -- cgit v1.2.3