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2013-01-02Merge LLVM 3.2 branchTom Stellard4-51/+24
2012-11-13Merge master branchtstellar22-608/+558
Build with clang checkouts: SVN: r167547 Git Mirror: b578aee665aad5ed1a46a26217c730fdfbfc8c2e git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22Merge master branchtstellar4-16/+25
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16Merge master branchtstellar9-35/+103
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Merge master branchtstellar18-116/+114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge master branchtstellar2-3/+7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge master branchtstellar25-73/+1941
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge TOTtstellar2-11/+62
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165010 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]tstellar1-0/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Whitespace.tstellar1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164522 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Fix edge cases of ARM shift operands in arith instructions.tstellar1-38/+6
As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Fix the handling of edge cases in ARM shifted operands.tstellar4-8/+35
This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.tstellar1-0/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164503 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Add comment.tstellar1-1/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24[fast-isel] Fallback to SelectionDAG isel if we require strict alignment fortstellar1-0/+6
non-aligned i32 loads/stores. rdar://12304911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164491 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Cortex-A9 latency fixes (w/ -schedmodel only).atrick1-5/+5
Quick review against the manual revealed a few obvious mistakes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164361 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21[fast-isel] Fallback to SelectionDAG isel if we require strict alignment formcrosier1-0/+6
non-halfword-aligned i16 loads/stores. rdar://12304911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Tidy up. Whitespace.grosbach1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Tidy up. Formatting.grosbach1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164343 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21ARM: Use a dedicated intrinsic for vector bitwise select.grosbach1-2/+29
The expression based expansion too often results in IR level optimizations splitting the intermediate values into separate basic blocks, preventing the formation of the VBSL instruction as the code author intended. In particular, LICM would often hoist part of the computation out of a loop. rdar://11011471 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20Change enum type in a static table to uint8_t instead. Saves about 700 ↵ctopper1-6/+6
hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164285 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648evancheng1-2/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendrdivacky2-2/+2
store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18More domain conversion; convert VFP VMOVS to NEON instructions in more cases ↵jamesm1-13/+56
- when we may clobber the other S-lane by converting an S to a D instruction, make an effort to work out if the S lane is clobberable or not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵atrick1-1/+2
model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteevancheng2-5/+42
aligned address. Based on patch by David Peixotto. Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment hints. rdar://12090772, rdar://12238782 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Revert r164061-r164067. Most of the new subtarget emitter.atrick1-2/+1
I have to work out the Target/CodeGen header dependencies before putting this back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵atrick1-1/+2
model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Removed the VMLxForwarding feature for the Cortex-A15 target.sbaranga1-2/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.ctopper1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.atrick2-0/+34
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14Cortex-A9 instruction-level scheduling machine model.atrick1-3/+594
This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163921 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14Fix Doxygen issues:gribozavr1-1/+1
* wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph); * use \param instead of \arg to document parameters in order to be consistent with the rest of the codebase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13This patch introduces A15 as a target in LLVM.Silviu Baranga9-30/+41
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163803 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Rename the isMemory() function to isMem(). No functional change intended.Chad Rosier1-22/+22
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Remove redundant semicolons which are null statements.Dmitri Gribenko1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen1-2/+8
The ARM backend can eliminate cmp instructions by reusing flags from a nearby sub instruction with similar arguments. Don't do that if the sub is predicated - the flags are not written unconditionally. <rdar://problem/12263428> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163535 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵Craig Topper1-0/+1
FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07Custom DAGCombine for and/or/xor are for all ARMs.Jakob Stoklund Olesen1-6/+3
The 'select' transformations apply to all ARM architectures and don't require hasV6T2Ops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07MC: Overhaul handling of .lcommBenjamin Kramer1-1/+0
- Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover1-0/+4
Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover1-8/+38
instructions. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Use correct part of complex operand to encode VST1 alignment.Tim Northover1-2/+2
Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Fix a few old-GCC warnings. No functional change.Nadav Rotem1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Fix self-host; ensure signedness is consistent.James Molloy1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163306 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Improve codegen for BUILD_VECTORs on ARM.James Molloy1-10/+56
If we have a BUILD_VECTOR that is mostly a constant splat, it is often better to splat that constant then insertelement the non-constant lanes instead of insertelementing every lane from an undef base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate ↵James Molloy2-17/+66
to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Remove predicated pseudo-instructions.Jakob Stoklund Olesen2-100/+0
These pseudos are no longer needed now that it is possible to represent predicated instructions in SSA form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163275 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen1-56/+31
Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Stop casting away const qualifier needlessly.Roman Divacky1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
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