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2013-01-02Merge LLVM 3.2 branchTom Stellard4-51/+24
2012-11-13Merge master branchtstellar22-608/+558
2012-10-22Merge master branchtstellar4-16/+25
2012-10-16Merge master branchtstellar9-35/+103
2012-10-11Merge master branchtstellar18-116/+114
2012-10-02Merge master branchtstellar2-3/+7
2012-10-02Merge master branchtstellar25-73/+1941
2012-10-02Merge TOTtstellar2-11/+62
2012-09-24ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]tstellar1-0/+2
2012-09-24Whitespace.tstellar1-2/+2
2012-09-24Fix edge cases of ARM shift operands in arith instructions.tstellar1-38/+6
2012-09-24Fix the handling of edge cases in ARM shifted operands.tstellar4-8/+35
2012-09-24[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.tstellar1-0/+4
2012-09-24Add comment.tstellar1-1/+2
2012-09-24[fast-isel] Fallback to SelectionDAG isel if we require strict alignment fortstellar1-0/+6
2012-09-21Cortex-A9 latency fixes (w/ -schedmodel only).atrick1-5/+5
2012-09-21[fast-isel] Fallback to SelectionDAG isel if we require strict alignment formcrosier1-0/+6
2012-09-21Tidy up. Whitespace.grosbach1-2/+2
2012-09-21Tidy up. Formatting.grosbach1-1/+1
2012-09-21ARM: Use a dedicated intrinsic for vector bitwise select.grosbach1-2/+29
2012-09-20Change enum type in a static table to uint8_t instead. Saves about 700 hundre...ctopper1-6/+6
2012-09-18MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648evancheng1-2/+4
2012-09-18When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendrdivacky2-2/+2
2012-09-18More domain conversion; convert VFP VMOVS to NEON instructions in more cases ...jamesm1-13/+56
2012-09-18TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine m...atrick1-1/+2
2012-09-18Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteevancheng2-5/+42
2012-09-17Revert r164061-r164067. Most of the new subtarget emitter.atrick1-2/+1
2012-09-17TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine m...atrick1-1/+2
2012-09-17Removed the VMLxForwarding feature for the Cortex-A15 target.sbaranga1-2/+1
2012-09-15Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.ctopper1-2/+2
2012-09-14Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.atrick2-0/+34
2012-09-14Cortex-A9 instruction-level scheduling machine model.atrick1-3/+594
2012-09-14Fix Doxygen issues:gribozavr1-1/+1
2012-09-13This patch introduces A15 as a target in LLVM.Silviu Baranga9-30/+41
2012-09-11Rename the isMemory() function to isMem(). No functional change intended.Chad Rosier1-22/+22
2012-09-10Remove redundant semicolons which are null statements.Dmitri Gribenko1-1/+1
2012-09-10Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen1-2/+8
2012-09-08Set operation action for FFLOOR to Expand for all vector types for X86. Set F...Craig Topper1-0/+1
2012-09-07Custom DAGCombine for and/or/xor are for all ARMs.Jakob Stoklund Olesen1-6/+3
2012-09-07MC: Overhaul handling of .lcommBenjamin Kramer1-1/+0
2012-09-06Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover1-0/+4
2012-09-06Check for invalid alignment values when decoding VLDn/VSTn (single ln) instru...Tim Northover1-8/+38
2012-09-06Use correct part of complex operand to encode VST1 alignment.Tim Northover1-2/+2
2012-09-06Fix a few old-GCC warnings. No functional change.Nadav Rotem1-1/+1
2012-09-06Fix self-host; ensure signedness is consistent.James Molloy1-2/+2
2012-09-06Improve codegen for BUILD_VECTORs on ARM.James Molloy1-10/+56
2012-09-06Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate to...James Molloy2-17/+66
2012-09-05Remove predicated pseudo-instructions.Jakob Stoklund Olesen2-100/+0
2012-09-05Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen1-56/+31
2012-09-05Stop casting away const qualifier needlessly.Roman Divacky1-1/+1
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