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AgeCommit message (Expand)AuthorFilesLines
2012-12-21R600: Support for indirect addressingindirect-wip-5Tom Stellard26-62/+1236
2012-12-11R600: Add an intrinsic to handle stream outputs.Vincent Lejeune6-0/+102
2012-12-11R600: Add a field for Export node (compMask) and factorise code handling stor...Vincent Lejeune2-42/+58
2012-12-11R600: Split Word0 and Word1 in Export instructionVincent Lejeune3-49/+60
2012-12-11AMDGPU/SI: Only allow selecting VGPRs with V_CNDMASK_B32.Michel Dänzer1-4/+4
2012-12-11AMDGPU: Match fdiv for SI.Michel Dänzer1-0/+5
2012-12-11R600: Add support for i8 and i16 function argumentsTom Stellard5-15/+92
2012-12-11R600: Improve assembly output for VTX instructionsTom Stellard4-7/+13
2012-12-11AMDGPU: Promote floating-point load/store to integer load/storeTom Stellard4-60/+37
2012-12-11LegalizeDAG: Allow promotion of scalar loadsTom Stellard1-3/+2
2012-12-11LegalizeDAG: Allow type promotion for scalar storesTom Stellard1-3/+4
2012-12-11R600: Convert global store address to dword offset during iselTom Stellard7-14/+46
2012-12-05R600: Fix use iterator in custom select of ISD::ConstantTom Stellard1-2/+3
2012-12-05AMDGPU: add a pattern for min/maxTom Stellard6-8/+79
2012-12-05AMDGPU: replace int_AMDGPU_rcp by fdiv (1.0, x) in RECIP patternVincent Lejeune3-4/+4
2012-12-05AMDGPU: Match AMDGPU.cube intrinsic for SI.Michel Dänzer1-0/+21
2012-12-05AMDGPU: Doxygen fixesTom Stellard72-517/+572
2012-12-05AMDGPU: Various coding style fixesTom Stellard46-518/+452
2012-11-29R600: Fold immediates into ALU instructions when possible v2Tom Stellard9-6/+153
2012-11-29AMDGPU: Remove or document commented out codeTom Stellard4-92/+13
2012-11-29AMDGPU: Fix 4-space indentationTom Stellard3-73/+73
2012-11-29AMDGPU: Remove unused macros v2Tom Stellard6-100/+19
2012-11-29AMDGPU: Coding style - put braces on same line as function headersTom Stellard27-458/+229
2012-11-29AMDGPU: Simplify SI control flow loweringChristian König1-41/+38
2012-11-29AMDGPU: Fix S_*_SAVEEXEC_B64 definesChristian König1-2/+8
2012-11-29R600: rename if/break operator to improve readabilityVincent Lejeune4-61/+29
2012-11-29R600: do not use magic number for resourceIdVincent Lejeune4-53/+60
2012-11-29R600: add fsqrt pattern for r600/r700Vincent Lejeune1-0/+3
2012-11-29R600: Valid pixel mode and EOP were inverted in exportVincent Lejeune1-2/+2
2012-11-29SI: Use IMAGE_SAMPLE_L for the SI.sample.lod intrinsic.Michel Dänzer1-2/+2
2012-11-16AMDGPU: Fix name of SI control flow lowering source file.Michel Dänzer1-1/+1
2012-11-16AMDGPU: Don't allow using SI SGPRs 102 and 103 directly.Michel Dänzer1-2/+2
2012-11-16AMDGPU: Fix string concatenation in AMDGPUInstPrinter::printRel().Michel Dänzer1-1/+1
2012-11-16R600: replaces fragment input with negative index with undef valuesVincent Lejeune1-3/+9
2012-11-16R600: Fix operand index table for OP3 instructionsTom Stellard1-1/+1
2012-11-16AMDGPU: Print integer and floating point values for literalsTom Stellard3-1/+13
2012-11-16R600: Add helper function for setting instruction modifiersTom Stellard3-9/+16
2012-11-13AMDGPU: Fix builds with -DNDEBUGtstellar1-0/+2
2012-11-13R600: Fix sampler->resource_id mappingtstellar1-2/+2
2012-11-13SI: s/flow control/control flow/g .tstellar4-15/+15
2012-11-13SI: fix SGPR liveness v4tstellar4-0/+191
2012-11-13SI: Add intrinsic for sampling with explicit LOD.tstellar2-1/+9
2012-11-13SI: Add intrinsic for sampling with bias.tstellar2-1/+9
2012-11-13SI: Update flow control comments to match current code.tstellar1-4/+5
2012-11-13Merge master branchtstellar599-7650/+20056
2012-11-13SI: Only allow SGPR for the first operand of VOP3 instructions.tstellar2-4/+4
2012-10-31SI: Enable control flow pass againtstellar1-2/+1
2012-10-31SI: Handle kilp intrinsictstellar1-0/+5
2012-10-31SI: Use SReg_1 class for SI_IF_(N)Z condition code operandtstellar1-3/+3
2012-10-31SI: Prevent instructions modifying the EXEC register from being movedtstellar2-0/+6
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