XXX: More LDSlds

5 files changed, 47 insertions, 19 deletions

diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
index d20716000d3..638b5ac0153 100644
--- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -103,7 +103,8 @@ enum InstrTypes {
   INSTR_FC,
   INSTR_NATIVE,
   INSTR_VTX,
-  INSTR_EXPORT
+  INSTR_EXPORT,
+  INSTR_LDS
 };
 
 enum FCInstr {
@@ -198,7 +199,12 @@ void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
   const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
 
   // Emit instruction type
-  EmitByte(INSTR_ALU, OS);
+  if (MCDesc.TSFlags & R600_InstFlag::LDS_1A ||
+      MCDesc.TSFlags & R600_InstFlag::LDS_1A1D) {
+    EmitByte(INSTR_LDS, OS);
+  } else {
+    EmitByte(INSTR_ALU, OS);
+  }
 
   uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
 
@@ -211,8 +217,17 @@ void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
     InstWord01 |= ISAOpCode << 1;
   }
 
-  unsigned SrcNum = MCDesc.TSFlags & R600_InstFlag::OP3 ? 3 :
-      MCDesc.TSFlags & R600_InstFlag::OP2 ? 2 : 1;
+  unsigned SrcNum =
+      MCDesc.TSFlags & R600_InstFlag::OP3 ? 3 :
+      MCDesc.TSFlags & R600_InstFlag::OP2 ? 2 :
+      MCDesc.TSFlags & R600_InstFlag::OP1 ? 1 :
+      MCDesc.TSFlags & R600_InstFlag::LDS_1A ? 1 : 2;
+
+  unsigned TableIdx =
+      MCDesc.TSFlags & R600_InstFlag::OP1 ? 0 :
+      MCDesc.TSFlags & R600_InstFlag::OP2 ? 1 :
+      MCDesc.TSFlags & R600_InstFlag::OP3 ? 2 :
+      MCDesc.TSFlags & R600_InstFlag::LDS_1A ? 3 : 4;
 
   EmitByte(SrcNum, OS);
 
@@ -223,8 +238,8 @@ void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
   };
 
   for (unsigned SrcIdx = 0; SrcIdx < SrcNum; ++SrcIdx) {
-    unsigned RegOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][0]];
-    unsigned SelOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][1]];
+    unsigned RegOpIdx = R600Operands::ALUOpTable[TableIdx][SrcOps[SrcIdx][0]];
+    unsigned SelOpIdx = R600Operands::ALUOpTable[TableIdx][SrcOps[SrcIdx][1]];
     EmitSrcISA(MI, RegOpIdx, SelOpIdx, OS);
   }
 
diff --git a/lib/Target/R600/R600Defines.h b/lib/Target/R600/R600Defines.h
index 16cfcf59eb3..736fad46be8 100644
--- a/lib/Target/R600/R600Defines.h
+++ b/lib/Target/R600/R600Defines.h
@@ -39,7 +39,9 @@ namespace R600_InstFlag {
     //FlagOperand bits 7, 8
     NATIVE_OPERANDS = (1 << 9),
     OP1 = (1 << 10),
-    OP2 = (1 << 11)
+    OP2 = (1 << 11),
+    LDS_1A = (1 << 12),
+    LDS_1A1D = (1 << 13)
   };
 }
 
@@ -81,7 +83,7 @@ namespace R600Operands {
     COUNT
  };
 
-  const static int ALUOpTable[3][R600Operands::COUNT] = {
+  const static int ALUOpTable[5][R600Operands::COUNT] = {
 //            W        C     S  S  S  S     S  S  S  S     S  S  S
 //            R  O  D  L  S  R  R  R  R  S  R  R  R  R  S  R  R  R  L  P
 //   D  U     I  M  R  A  R  C  C  C  C  R  C  C  C  C  R  C  C  C  A  R  I
@@ -89,7 +91,9 @@ namespace R600Operands {
 //   T  M  P  E  D  L  P  0  N  R  A  S  1  N  R  A  S  2  N  R  S  T  D  M
     {0,-1,-1, 1, 2, 3, 4, 5, 6, 7, 8, 9,-1,-1,-1,-1,-1,-1,-1,-1,-1,10,11,12},
     {0, 1, 2, 3, 4 ,5 ,6 ,7, 8, 9,10,11,12,13,14,15,16,-1,-1,-1,-1,17,18,19},
-    {0,-1,-1,-1,-1, 1, 2, 3, 4, 5,-1, 6, 7, 8, 9,-1,10,11,12,13,14,15,16,17}
+    {0,-1,-1,-1,-1, 1, 2, 3, 4, 5,-1, 6, 7, 8, 9,-1,10,11,12,13,14,15,16,17},
+    {0,-1,-1,-1,-1,-1,-1, 1,-1, 2,-1, 3,-1,-1,-1,-1,-1,-1,-1,-1,-1, 4, 5, 6},
+   {-1,-1,-1,-1,-1,-1,-1, 0,-1, 1,-1, 2, 3,-1, 4,-1, 5,-1,-1,-1,-1, 6, 7, 8}
   };
 
 }
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index 54e0c38a19d..9557ff5165d 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -845,9 +845,9 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
 
   EVT ValueVT = Value.getValueType();
 
-  if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
+//  if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
     return SDValue();
-  }
+//  }
 
   // Lowering for indirect addressing
 
@@ -976,9 +976,9 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
     return DAG.getMergeValues(MergedValues, 2, DL);
   }
 
-  if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
+//  if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
     return SDValue();
-  }
+//}
 
   // Lowering for indirect addressing
   const MachineFunction &MF = DAG.getMachineFunction();
diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp
index 7e3f0057293..5a9eecebdcd 100644
--- a/lib/Target/R600/R600InstrInfo.cpp
+++ b/lib/Target/R600/R600InstrInfo.cpp
@@ -662,10 +662,12 @@ int R600InstrInfo::getOperandIdx(unsigned Opcode,
     OpTableIdx = 0;
   } else if (TargetFlags & R600_InstFlag::OP2) {
     OpTableIdx = 1;
-  } else {
-    assert((TargetFlags & R600_InstFlag::OP3) && "OP1, OP2, or OP3 not defined "
-                                                 "for this instruction");
+  } else if (TargetFlags & R600_InstFlag::OP3) {
     OpTableIdx = 2;
+  } else {
+    assert((TargetFlags & R600_InstFlag::LDS_1A) &&
+            "OP1, OP2, OP3, or LDS_1A not defined for this instruction");
+    OpTableIdx = 3;
   }
 
   return R600Operands::ALUOpTable[OpTableIdx][Op];
diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
index 440bf389e30..bd30c2cb4ca 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -24,6 +24,8 @@ class InstR600 <bits<11> inst, dag outs, dag ins, string asm, list<dag> pattern,
   bits<2> FlagOperandIdx = 0;
   bit Op1 = 0;
   bit Op2 = 0;
+  bit LDS_1A = 0;
+  bit LDS_1A1D = 0;
   bit HasNativeOperands = 0;
 
   bits<11> op_code = inst;
@@ -45,6 +47,8 @@ class InstR600 <bits<11> inst, dag outs, dag ins, string asm, list<dag> pattern,
   let TSFlags{9} = HasNativeOperands;
   let TSFlags{10} = Op1;
   let TSFlags{11} = Op2;
+  let TSFlags{12} = LDS_1A;
+  let TSFlags{13} = LDS_1A1D;
 }
 
 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
@@ -1568,7 +1572,7 @@ class R600_LDS  <bits<6> lds_op, dag outs, dag ins, string asm,
 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
   lds_op,
   (outs R600_Reg32:$dst),
-  (ins R600_Reg32:$src0, REL:$src0_rel,
+  (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
        LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
   !strconcat(name, " OQA, [$src0$src0_rel], $literal $pred_sel$last"),
   pattern
@@ -1581,14 +1585,15 @@ class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
 
   let Defs = [OQA];
   let usesCustomInserter = 1;
+  let LDS_1A = 1;
 }
 
 class R600_LDS_1A1D <bits<6> lds_op, string name, list<dag> pattern> :
     R600_LDS <
   lds_op,
   (outs),
-  (ins R600_Reg32:$src0, REL:$src0_rel,
-       R600_Reg32:$src1, REL:$src1_rel,
+  (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
+       R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
        LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
   !strconcat(name, " $src0$src0_rel, [$src1$src1_rel], $literal "
                    "$pred_sel$last"),
@@ -1597,6 +1602,7 @@ class R600_LDS_1A1D <bits<6> lds_op, string name, list<dag> pattern> :
 
   let src2 = 0;
   let src2_rel = 0;
+  let LDS_1A1D = 1;
 }
 
 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
@@ -1607,6 +1613,7 @@ def LDS_WRITE : R600_LDS_1A1D <0xD, "LDS_WRITE",
   [(private_store (i32 R600_Reg32:$src0), R600_Reg32:$src1)]
 >;
 
+} // End isR600toCayman
 //===----------------------------------------------------------------------===//
 // Regist loads and stores - for indirect addressing
 //===----------------------------------------------------------------------===//