XXX: Workingimage-support

3 files changed, 104 insertions, 32 deletions

diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index a2bc2c3a9fa..d7347e6b4c5 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -183,6 +183,16 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
     break;
   }
 
+  case AMDGPU::SET_CF_IDX:
+    assert(MRI.hasOneUse(MI->getOperand(0).getReg()));
+    MRI.replaceRegWith(MI->getOperand(0).getReg(), AMDGPU::CF_IDX0);
+    BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::SET_CF_IDX0))
+            .addOperand(MI->getOperand(1))
+            .addImm(1) // Last
+            .addImm(0) // Bank Swizzle
+            .addReg(AMDGPU::CF_IDX0, RegState::Define | RegState::Implicit);
+    break;
+
   case AMDGPU::TXD: {
     unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
     unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
index 9ff389701e6..cf259186a35 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -376,25 +376,6 @@ def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
 
 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
 
-multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
-def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
-          (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
-          (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
-          (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
-          (i32 imm:$DST_SEL_W),
-          (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
-          (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
-          (i32 imm:$COORD_TYPE_W)),
-          (inst R600_Reg128:$SRC_GPR,
-          imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
-          imm:$offsetx, imm:$offsety, imm:$offsetz,
-          imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
-          imm:$DST_SEL_W,
-          imm:$RESOURCE_ID, imm:$SAMPLER_ID,
-          imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
-          imm:$COORD_TYPE_W)>;
-}
-
 //===----------------------------------------------------------------------===//
 // Interpolation Instructions
 //===----------------------------------------------------------------------===//
@@ -827,11 +808,12 @@ class R600_TEX <bits<11> inst, string opName> :
           RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,
           i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
           CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,
-          CT:$COORD_TYPE_W),
+          CT:$COORD_TYPE_W, R600_CF_IDX:$RESOURCE_INDEX_MODE),
           !strconcat(opName,
           " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "
           "$SRC_GPR.$srcx$srcy$srcz$srcw "
           "RID:$RESOURCE_ID SID:$SAMPLER_ID "
+          "RIM: $RESOURCE_INDEX_MODE "
           "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),
           [],
           NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
@@ -847,7 +829,6 @@ class R600_TEX <bits<11> inst, string opName> :
   let FETCH_WHOLE_QUAD = 0;
   let ALT_CONST = 0;
   let SAMPLER_INDEX_MODE = 0;
-  let RESOURCE_INDEX_MODE = 0;
 
   let TEXInst = 1;
 }
@@ -871,17 +852,6 @@ def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;
 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;
 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;
 
-defm : TexPattern<0, TEX_SAMPLE>;
-defm : TexPattern<1, TEX_SAMPLE_C>;
-defm : TexPattern<2, TEX_SAMPLE_L>;
-defm : TexPattern<3, TEX_SAMPLE_C_L>;
-defm : TexPattern<4, TEX_SAMPLE_LB>;
-defm : TexPattern<5, TEX_SAMPLE_C_LB>;
-defm : TexPattern<6, TEX_LD, v4i32>;
-defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
-defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
-defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
-
 //===----------------------------------------------------------------------===//
 // Helper classes for common instructions
 //===----------------------------------------------------------------------===//
@@ -1522,6 +1492,41 @@ def GROUP_BARRIER : InstR600 <
   let ALUInst = 1;
 }
 
+let isPseudo = 1, usesCustomInserter = 1 in {
+def SET_CF_IDX : InstR600 <(outs R600_Reg32:$dst),
+                           (ins R600_Reg32:$idx), "", [], AnyALU>;
+} // End isPseudo = 1, usesCustomInserter = 1 in {
+
+def SET_CF_IDX0 : InstR600 <
+    (outs), (ins R600_Reg32:$src0, LAST:$last, BANK_SWIZZLE:$bank_swizzle),
+    "  SET_CF_IDX0 $last$src0 $bank_swizzle", [], AnyALU>,
+    R600ALU_Word0,
+    R600ALU_Word1_OP2 <0x58> {
+
+  let dst = 0;
+  let dst_rel = 0;
+  let src0_rel = 0;
+  let src0_neg = 0;
+  let src0_abs = 0;
+  let src1 = 0;
+  let src1_rel = 0;
+  let src1_neg = 0;
+  let src1_abs = 0;
+  let write = 0;
+  let omod = 0;
+  let clamp = 0;
+  let pred_sel = 0;
+  let update_exec_mask = 0;
+  let update_pred = 0;
+
+  let Inst{31-0}  = Word0;
+  let Inst{63-32} = Word1;
+
+  let ALUInst = 1;
+  let UseNamedOperandTable = 1;
+  let Defs = [CF_IDX0];
+}
+
 //===----------------------------------------------------------------------===//
 // LDS Instructions
 //===----------------------------------------------------------------------===//
@@ -2277,6 +2282,57 @@ def : Pat <
   (SETNE_DX10 $src0, $src1)
 >;
 
+// Texture patterns
+
+multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
+def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
+          (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
+          (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
+          (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
+          (i32 imm:$DST_SEL_W),
+          (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
+          (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
+          (i32 imm:$COORD_TYPE_W)),
+          (inst R600_Reg128:$SRC_GPR,
+          imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
+          imm:$offsetx, imm:$offsety, imm:$offsetz,
+          imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
+          imm:$DST_SEL_W,
+          imm:$RESOURCE_ID, imm:$SAMPLER_ID,
+          imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
+          imm:$COORD_TYPE_W,
+          CF_IDXNONE)>; //RESOURCE_INDEX_MODE
+def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
+          (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
+          (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
+          (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
+          (i32 imm:$DST_SEL_W),
+          i32:$RESOURCE_ID, (i32 imm:$SAMPLER_ID),
+          (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
+          (i32 imm:$COORD_TYPE_W)),
+          (inst R600_Reg128:$SRC_GPR,
+          imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
+          imm:$offsetx, imm:$offsety, imm:$offsetz,
+          imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
+          imm:$DST_SEL_W,
+          0, imm:$SAMPLER_ID,
+          imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
+          imm:$COORD_TYPE_W,
+          (SET_CF_IDX i32:$RESOURCE_ID))>; //RESOURCE_INDEX_MODE
+}
+
+defm : TexPattern<0, TEX_SAMPLE>;
+defm : TexPattern<0, TEX_SAMPLE, v4i32>;
+defm : TexPattern<1, TEX_SAMPLE_C>;
+defm : TexPattern<2, TEX_SAMPLE_L>;
+defm : TexPattern<3, TEX_SAMPLE_C_L>;
+defm : TexPattern<4, TEX_SAMPLE_LB>;
+defm : TexPattern<5, TEX_SAMPLE_C_LB>;
+defm : TexPattern<6, TEX_LD, v4i32>;
+defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
+defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
+defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
+
 def : Extract_Element <f32, v4f32, 0, sub0>;
 def : Extract_Element <f32, v4f32, 1, sub1>;
 def : Extract_Element <f32, v4f32, 2, sub2>;
diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td
index 1eabccbd59a..74b76be09fb 100644
--- a/lib/Target/R600/R600RegisterInfo.td
+++ b/lib/Target/R600/R600RegisterInfo.td
@@ -104,6 +104,10 @@ def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
 def AR_X : R600Reg<"AR.x", 0>;
 def OQAP : R600Reg<"OQAP", 221>;
 
+def CF_IDXNONE : R600Reg<"", 0>;
+def CF_IDX0 : R600Reg<"CF_IDX0", 1>;
+def CF_IDX1 : R600Reg<"CF_IDX1", 2>;
+
 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
                           (add (sequence "ArrayBase%u", 448, 480))>;
 // special registers for ALU src operands
@@ -117,6 +121,8 @@ let isAllocatable = 0 in {
 // XXX: Only use the X channel, until we support wider stack widths
 def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", 0, 127))>;
 
+def R600_CF_IDX : RegisterClass <"AMDGPU", [i32], 32, (add CF_IDXNONE, CF_IDX0, CF_IDX1)>;
+
 } // End isAllocatable = 0
 
 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,