diff options
author | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2014-10-03 10:42:23 +0300 |
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committer | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2014-10-03 10:42:23 +0300 |
commit | 2cc0a089a6bdd7b8eec51db83c1a288eb4781300 (patch) | |
tree | 214541fa01976078f848733ec34290b98656a3dc | |
parent | db1540dbd3e8cd266b6e5982765fae1cc4c6e006 (diff) |
Revert "i965/fs: Lower double precision scalars into vectors"df_scalar_test
This reverts commit c7cff16a7404d2b6eab1ef6d5714dba110d35a49.
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.h | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 44 |
2 files changed, 1 insertions, 45 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index a5686d6be2..9e4382c9a8 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -549,8 +549,6 @@ public: void visit_atomic_counter_intrinsic(ir_call *ir); - fs_reg lower_double_scalar(const fs_reg *reg); - const struct brw_wm_prog_key *const key; struct brw_wm_prog_data *prog_data; unsigned int sanity_param_count; diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index fb0cf087c9..cb7d58e138 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -150,44 +150,6 @@ fs_visitor::visit(ir_variable *ir) hash_table_insert(this->variable_ht, reg, ir); } -/** - * Lower double precision scalar into a vector. Hardware can operate only - * with scalars of single precision. - * - * Quotes from the docs: - * - * IVB PRM vol4 part 3, section 3.1 (about align1 mode): - * "A single precision float scalar is allowed." - * - * Section 3.3.9 (Register region restrictions): - * "If ExecSize = Width = 1, both VertStride and HorzStride must be 0. This - * defines a scalar." - * "If VertStride = HorzStride = 0, Width must be 1 regardless of the value of - * ExecSize." - * - * "In Align1 mode, all regioning parameters like stride, execution size, and - * width must use the syntax of a pair of packed floats. The offsets for - * these data types must be 64 - bit aligned. The execution size and - * regioning parameters are in terms of floats. - * - * Example: mov (8) r10.0<1>:df r11.0<8;8,1>:df - * The above instruction moves four double floats" - * - * Hence in case of "double scalar", one should set width = 2 violating the - * second constraint. - */ -fs_reg -fs_visitor::lower_double_scalar(const fs_reg *reg) -{ - fs_reg res = fs_reg(this, glsl_type::double_type); - fs_reg lo = retype(*reg, BRW_REGISTER_TYPE_UD); - fs_reg hi = offset(lo, 1); - - emit(FS_OPCODE_PACK_DOUBLE_2x32, res, lo, hi); - - return res; -} - void fs_visitor::visit(ir_dereference_variable *ir) { @@ -198,11 +160,7 @@ fs_visitor::visit(ir_dereference_variable *ir) this->result = fs_reg(reg_null_d); return; } - - if (reg->file == UNIFORM && reg->type == BRW_REGISTER_TYPE_DF) - this->result = lower_double_scalar(reg); - else - this->result = *reg; + this->result = *reg; } void |