i965/gen6: Represent w-tiled stencil surfaces with islb2b_with_surf_array

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

3 files changed, 50 insertions, 22 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index b69cb4fc7b..b43c09e42e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -171,8 +171,9 @@ blorp_surf_for_miptree(struct brw_context *brw,
       .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
    };
 
-   if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
-       mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
+   if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8) {
+      assert(mt->array_layout == GEN6_BACK_TO_BACK);
+
       /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
        * order to allow for layered rendering.  The hack makes each LOD of the
        * stencil or HiZ buffer a single tightly packed array surface at some
@@ -183,8 +184,14 @@ blorp_surf_for_miptree(struct brw_context *brw,
        *
        * See also gen6_depth_stencil_state.c
        */
-      uint32_t offset;
-      apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
+      uint32_t x_offset_sa, y_offset_sa;
+      gen6_back_to_back_offset(&mt->surf, *level, 0,
+                               &x_offset_sa, &y_offset_sa);
+      assert(x_offset_sa == 0);
+
+      /* Pitch represents two rows interleaved. */
+      const uint32_t offset = y_offset_sa * mt->surf.row_pitch / 2;
+
       surf->addr.offset += offset;
       *level = 0;
    }
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 0ff240753e..6871b20eab 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -188,27 +188,19 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
 
       /* Emit stencil buffer. */
       if (separate_stencil) {
-         uint32_t offset = 0;
-
-         if (stencil_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
-            assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
+         assert(mt->surf.size > 0);
 
-            /* Note: we can't compute the stencil offset using
-             * intel_region_get_aligned_offset(), because stencil_region
-             * claims that the region is untiled even though it's W tiled.
-             */
-            offset = stencil_mt->level[lod].level_y * stencil_mt->pitch +
-                     stencil_mt->level[lod].level_x * 64;
-         }
+         uint32_t x_offset_sa, y_offset_sa;
+         gen6_back_to_back_offset(&stencil_mt->surf, lod, 0,
+                                  &x_offset_sa, &y_offset_sa);
+         assert(x_offset_sa == 0);
+         
+         /* Pitch represents two rows interleaved. */
+         const uint32_t offset = y_offset_sa * stencil_mt->surf.row_pitch / 2;
 
 	 BEGIN_BATCH(3);
 	 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
-         /* The stencil buffer has quirky pitch requirements.  From Vol 2a,
-          * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
-          *    The pitch must be set to 2x the value computed based on width, as
-          *    the stencil buffer is stored with two rows interleaved.
-          */
-	 OUT_BATCH(2 * stencil_mt->pitch - 1);
+	 OUT_BATCH(stencil_mt->surf.row_pitch - 1);
 	 OUT_RELOC(stencil_mt->bo,
 		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		   offset);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index af8c3ef895..d59a280e3b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -609,6 +609,21 @@ intel_lower_compressed_format(struct brw_context *brw, mesa_format format)
    }
 }
 
+static void
+gen6_stencil_override(struct isl_surf *surf)
+{
+   const struct isl_extent3d image_align_sa =
+      isl_surf_get_image_alignment_sa(surf);
+   const uint32_t total_h = gen6_back_to_back_total_height(
+                                &surf->phys_level0_sa, &image_align_sa,
+                                surf->dim, surf->tiling, surf->levels);
+
+   surf->size = total_h * surf->row_pitch;
+
+   /* There is no such thing with back-to-back layout. */
+   surf->array_pitch_el_rows = 0;
+}
+
 static struct intel_mipmap_tree *
 make_surface(struct brw_context *brw, GLenum target, mesa_format format,
              unsigned first_level, unsigned last_level,
@@ -637,6 +652,8 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format,
        num_samples, width0, height0, depth0,
        first_level, last_level, mt);
 
+   const bool is_gen6_stencil = brw->gen == 6 &&
+                                format == MESA_FORMAT_S_UINT8;
 
    struct isl_surf_init_info init_info = {
       .dim = get_isl_surf_dim(target),
@@ -644,7 +661,7 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format,
       .width = width0,
       .height = height0,
       .depth = target == GL_TEXTURE_3D ? depth0 : 1,
-      .levels = last_level + 1,
+      .levels = is_gen6_stencil ? 1 : last_level + 1,
       .array_len = target == GL_TEXTURE_3D ? 1 : depth0,
       .samples = MAX2(num_samples, 1),
       .usage = isl_usage_flags, 
@@ -654,6 +671,11 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format,
    if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
       goto fail;
 
+   if (is_gen6_stencil) {
+      mt->array_layout = GEN6_BACK_TO_BACK;
+      gen6_stencil_override(&mt->surf);
+   }
+
    assert(mt->surf.size % mt->surf.row_pitch == 0);
 
    unsigned pitch = mt->surf.row_pitch;
@@ -694,6 +716,13 @@ miptree_create(struct brw_context *brw,
                GLuint num_samples,
                uint32_t layout_flags)
 {
+   if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8)
+      return make_surface(brw, target, format, first_level, last_level,
+                          width0, height0, depth0, num_samples, ISL_TILING_W,
+                          ISL_SURF_USAGE_STENCIL_BIT |
+                          ISL_SURF_USAGE_TEXTURE_BIT,
+                          BO_ALLOC_FOR_RENDER);
+
    struct intel_mipmap_tree *mt;
    mesa_format tex_format = format;
    mesa_format etc_format = MESA_FORMAT_NONE;