| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2012-11-29 | video: exynos_dp: Fix incorrect setting for INT_CTL | Ajay Kumar | 1 | -1/+2 |
| 2012-09-22 | video: exynos_dp: increase AUX channel voltage level | Jingoo Han | 1 | -1/+1 |
| 2012-09-22 | video: exynos_dp: add bit-masking for LINK_TRAINING_CTL register | Jingoo Han | 1 | -0/+1 |
| 2012-04-16 | video: exynos_dp: add analog and pll control setting | Jingoo Han | 1 | -0/+29 |
| 2012-02-13 | video: support DP controller driver | Jingoo Han | 1 | -0/+335 |
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