summaryrefslogtreecommitdiff
path: root/arch/arm/mm/cache-l2x0.c
AgeCommit message (Expand)AuthorFilesLines
2014-05-30ARM: l2c: trial at enabling some Cortex-A9 optimisationsRussell King1-3/+70
2014-05-30ARM: l2c: add warnings for stuff modifying aux_ctrl register valuesRussell King1-3/+22
2014-05-30ARM: l2c: print a warning with L2C-310 caches if the cache size is modifiedRussell King1-0/+2
2014-05-30ARM: l2c: remove old .set_debug methodRussell King1-19/+2
2014-05-30ARM: l2c: always enable non-secure access to lockdown registersRussell King1-2/+21
2014-05-30ARM: l2c: always enable low power modesRussell King1-0/+12
2014-05-30ARM: l2c: add automatic enable of early BRESPRussell King1-3/+22
2014-05-30ARM: l2c: move L2 cache register saving to a more sensible locationRussell King1-12/+22
2014-05-30ARM: l2c: check that DT files specify the required "cache-unified" propertyRussell King1-0/+4
2014-05-30ARM: l2c: fix register namingRussell King1-28/+29
2014-05-30ARM: l2c: implement L2C-310 erratum 752271 in core L2C codeRussell King1-1/+17
2014-05-30ARM: l2c: provide generic hook to intercept writes to secure registersRussell King1-12/+30
2014-05-30ARM: l2c: move way size calculation data into l2c_init_dataRussell King1-9/+20
2014-05-30ARM: l2c: add decode for L2C-220 cache waysRussell King1-0/+1
2014-05-30ARM: l2c: move type string into l2c_init_data structureRussell King1-7/+13
2014-05-30ARM: l2c: remove obsolete l2x0 ops for non-OF initRussell King1-206/+0
2014-05-30ARM: l2c: convert Broadcom L2C-310 to new codeRussell King1-16/+11
2014-05-30ARM: l2c: add L2C-220 specific handlersRussell King1-10/+157
2014-05-30ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementationsRussell King1-22/+36
2014-05-30ARM: l2c: implement L2C-310 erratum 588369 as a method overrideRussell King1-0/+69
2014-05-30ARM: l2c: implement L2C-310 erratum 727915 as a method overrideRussell King1-0/+20
2014-05-30ARM: l2c: add L2C-210 specific handlersRussell King1-1/+122
2014-05-30ARM: l2c: move pl310_set_debug() into l2c-310 codeRussell King1-8/+6
2014-05-30ARM: l2c: simplify l2x0 unlocking codeRussell King1-17/+8
2014-05-30ARM: l2c: clean up save/resume functionsRussell King1-57/+52
2014-05-30ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OFRussell King1-74/+77
2014-05-30ARM: l2c: clean up L2 cache initialisation messagesRussell King1-3/+4
2014-05-30ARM: l2c: implement fixups for L2 cache controller quirks/errataRussell King1-11/+101
2014-05-30ARM: l2c: move aurora broadcast setup to enable functionRussell King1-13/+15
2014-05-30ARM: l2c: only write the auxiliary control register if requiredRussell King1-1/+3
2014-05-30ARM: l2c: write auxctrl register before unlockingRussell King1-5/+5
2014-05-30ARM: l2c: provide enable methodRussell King1-18/+62
2014-05-30ARM: l2c: group implementation specific code togetherRussell King1-251/+251
2014-05-30ARM: l2c: move l2c save function to __l2c_init()Russell King1-3/+7
2014-05-30ARM: l2c: pass iomem address into data->save functionRussell King1-16/+16
2014-05-30ARM: l2c: clean up OF initialisation a bitRussell King1-26/+40
2014-05-30ARM: l2c: add and use L2C revision constantsRussell King1-5/+5
2014-05-30ARM: l2c: rename cache_wait_way()Russell King1-3/+3
2014-05-30ARM: l2c: provide generic helper for way-based operationsRussell King1-6/+9
2014-05-30ARM: l2c: split out cache unlock codeRussell King1-7/+16
2014-05-30ARM: l2c: provide generic function for calling set_debug methodRussell King1-1/+11
2014-05-30ARM: l2c: rename OF specific things, making l2x0_of_data available to allRussell King1-32/+32
2014-05-30ARM: l2c: tidy up l2x0_of_data declarationsRussell King1-16/+14
2014-05-30ARM: l2c: add helper for L2 cache controller DT IDsRussell King1-13/+10
2014-05-22ARM: l2c: remove outer_inv_all() methodRussell King1-5/+0
2013-12-29ARM: 7922/1: l2x0: add Marvell Tauros3 supportSebastian Hesselbarth1-8/+40
2013-09-05Merge branches 'debug-choice', 'devel-stable' and 'misc' into for-linusRussell King1-5/+7
2013-08-20ARM: 7821/1: DT: binding fixup to align with vendor-prefixes.txtChristian Daudt1-1/+3
2013-08-20ARM: 7820/1: mm: cache-l2x0: Print the cache size in kBFabio Estevam1-3/+3
2013-08-12ARM: l2x0: use -st dsb option for ordering writel_relaxed with unlockWill Deacon1-1/+1
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 12:40:26 +0000