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authorJernej Skrabec <jernej.skrabec@siol.net>2018-06-25 14:02:55 +0200
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-06-27 21:43:58 +0200
commit03c35dbf73e0726136bad921cb2649728ce909d5 (patch)
tree7513a3b0e9c423e31e341b01166a6b142387baea
parent0740845909b1e0089ff60ee62b55622759875e4f (diff)
dt-bindings: display: sun4i-drm: Add description of A64 HDMI PHY
A64 HDMI PHY is similar to H3 HDMI PHY except it has two possible PLL clock parents. It is compatible to other HDMI PHYs, like that found in R40. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-16-jernej.skrabec@siol.net
-rw-r--r--Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt4
1 files changed, 3 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index fe31b1510717..5a9319ad8861 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -101,6 +101,7 @@ DWC HDMI PHY
Required properties:
- compatible: value must be one of:
+ * allwinner,sun50i-a64-hdmi-phy
* allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy
- reg: base address and size of memory-mapped region
@@ -111,8 +112,9 @@ Required properties:
- resets: phandle to the reset controller driving the PHY
- reset-names: must be "phy"
-H3 HDMI PHY requires additional clock:
+H3 and A64 HDMI PHY require additional clocks:
- pll-0: parent of phy clock
+ - pll-1: second possible phy clock parent (A64 only)
TV Encoder
----------