diff options
| author | Xishi Qiu <qiuxishi@huawei.com> | 2013-08-30 17:39:28 +0800 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2013-10-14 15:50:53 +0200 |
| commit | bf038227a01263dc29fa7053e600ec5a939d0bbd (patch) | |
| tree | d909941745f8d773ad687dc13a64b90d80e6b1a5 /Documentation/DMA-attributes.txt | |
| parent | 0d7a0a8a7480a401b29c8e38c3b8f7c129b68db9 (diff) | |
doc: Documentation/DMA-attributes.txt fix typo
Fix some typos in Documentation/DMA-attributes.txt.
Signed-off-by: Xishi Qiu <qiuxishi@huawei.com>
Acked-by: Rob Landley <rob@landley.net>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'Documentation/DMA-attributes.txt')
| -rw-r--r-- | Documentation/DMA-attributes.txt | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt index e59480db9ee..cc2450d8031 100644 --- a/Documentation/DMA-attributes.txt +++ b/Documentation/DMA-attributes.txt @@ -13,7 +13,7 @@ all pending DMA writes to complete, and thus provides a mechanism to strictly order DMA from a device across all intervening busses and bridges. This barrier is not specific to a particular type of interconnect, it applies to the system as a whole, and so its -implementation must account for the idiosyncracies of the system all +implementation must account for the idiosyncrasies of the system all the way from the DMA device to memory. As an example of a situation where DMA_ATTR_WRITE_BARRIER would be @@ -60,7 +60,7 @@ such mapping is non-trivial task and consumes very limited resources Buffers allocated with this attribute can be only passed to user space by calling dma_mmap_attrs(). By using this API, you are guaranteeing that you won't dereference the pointer returned by dma_alloc_attr(). You -can threat it as a cookie that must be passed to dma_mmap_attrs() and +can treat it as a cookie that must be passed to dma_mmap_attrs() and dma_free_attrs(). Make sure that both of these also get this attribute set on each call. @@ -82,7 +82,7 @@ to 'device' domain, what synchronizes CPU caches for the given region (usually it means that the cache has been flushed or invalidated depending on the dma direction). However, next calls to dma_map_{single,page,sg}() for other devices will perform exactly the -same sychronization operation on the CPU cache. CPU cache sychronization +same synchronization operation on the CPU cache. CPU cache synchronization might be a time consuming operation, especially if the buffers are large, so it is highly recommended to avoid it if possible. DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of |