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authorEric Anholt <eric@anholt.net>2010-12-16 16:42:52 -0800
committerEric Anholt <eric@anholt.net>2010-12-16 16:48:29 -0800
commit253acc34af6fb9976a8d54991560dec5920af20b (patch)
tree9282da20d3e4ee30cec32c52611c1ca2976decd8
parent19b412b37cd3474200a2c6fe0cdb11af0c0f98cb (diff)
intel_disable_clock_gating: New tool for turning off clock gating on ILK.
This is something I sometimes want to do in testing, to see if a mystery bug (say, 29172) is due to broken clock gating. Sadly, in this case it isn't. Note that it isn't supported on non-ILK chipsets yet.
-rw-r--r--.gitignore1
-rw-r--r--lib/intel_reg.h7
-rw-r--r--tools/Makefile.am1
-rw-r--r--tools/intel_disable_clock_gating.c72
4 files changed, 81 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore
index c31b8650..cbb4f0db 100644
--- a/.gitignore
+++ b/.gitignore
@@ -47,6 +47,7 @@ tests/gem_bad_address
tests/gem_bad_batch
tests/gem_bad_blit
tests/gem_hang
+tools/intel_disable_clock_gating
tools/intel_error_decode
tools/intel_gpu_dump
tools/intel_gpu_time
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 44055fab..eb09a89f 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -1566,6 +1566,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
#define ADPA_HSYNC_ACTIVE_LOW 0
+#define PCH_DSPCLK_GATE_D 0x42020
+#define PCH_DSPRAMCLK_GATE_D 0x42024
+#define PCH_3DCGDIS0 0x46020
+#define PCH_3DCGDIS1 0x46024
+#define PCH_3DRAMCGDIS0 0x46028
+#define SOUTH_DSPCLK_GATE_D 0xc2020
+
#define CPU_eDP_A 0x64000
#define PCH_DP_B 0xe4100
#define PCH_DP_C 0xe4200
diff --git a/tools/Makefile.am b/tools/Makefile.am
index e7d23d23..09b4ec88 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -1,4 +1,5 @@
bin_PROGRAMS = \
+ intel_disable_clock_gating \
intel_audio_dump \
intel_bios_dumper \
intel_bios_reader \
diff --git a/tools/intel_disable_clock_gating.c b/tools/intel_disable_clock_gating.c
new file mode 100644
index 00000000..e702fa6e
--- /dev/null
+++ b/tools/intel_disable_clock_gating.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Zhenyu Wang <zhenyuw@linux.intel.com>
+ *
+ */
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <err.h>
+#include <string.h>
+#include "intel_gpu_tools.h"
+
+int main(int argc, char** argv)
+{
+ struct pci_device *pci_dev;
+ uint32_t temp;
+
+ pci_dev = intel_get_pci_device();
+ intel_get_mmio(pci_dev);
+
+ if (IS_IRONLAKE(pci_dev->device_id)) {
+ printf("Restore method:\n");
+
+ printf("intel_reg_write 0x%x 0x%08x\n",
+ PCH_3DCGDIS0, INREG(PCH_3DCGDIS0));
+ OUTREG(PCH_3DCGDIS0, 0xffffffff);
+
+ printf("intel_reg_write 0x%x 0x%08x\n",
+ PCH_3DCGDIS1, INREG(PCH_3DCGDIS1));
+ OUTREG(PCH_3DCGDIS1, 0xffffffff);
+
+ printf("intel_reg_write 0x%x 0x%08x\n",
+ PCH_3DRAMCGDIS0, INREG(PCH_3DRAMCGDIS0));
+ OUTREG(PCH_3DRAMCGDIS0, 0xffffffff);
+
+ printf("intel_reg_write 0x%x 0x%08x\n",
+ PCH_DSPCLK_GATE_D, INREG(PCH_DSPCLK_GATE_D));
+ OUTREG(PCH_DSPCLK_GATE_D, 0xffffffff);
+
+ printf("intel_reg_write 0x%x 0x%08x\n",
+ PCH_DSPRAMCLK_GATE_D, INREG(PCH_DSPRAMCLK_GATE_D));
+ OUTREG(PCH_DSPRAMCLK_GATE_D, 0xffffffff);
+ } else {
+ fprintf(stderr, "unsupported chipset\n");
+ }
+
+
+ return 0;
+}
+