Follow the HW spec to set the surface cache attribute for Gen9+

Currently it will use the unoptimized cache attribute for the surface on Gen9+.
This is to follow the HW spec to optimize the cache attribute of the surface
for gen9+.

Signed-off-by: Qu, Pengfei <pengfei.qu@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

3 files changed, 28 insertions, 0 deletions

diff --git a/src/gen8_post_processing.c b/src/gen8_post_processing.c
index fbf0e57..375bbe0 100644
--- a/src/gen8_post_processing.c
+++ b/src/gen8_post_processing.c
@@ -380,6 +380,7 @@ gen8_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_cont
                           int width, int height, int pitch, int format,
 			  int index, int is_target)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct gen8_surface_state *ss;
     dri_bo *ss_bo;
     unsigned int tiling;
@@ -393,6 +394,10 @@ gen8_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_cont
     assert(ss_bo->virtual);
     ss = (struct gen8_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
     memset(ss, 0, sizeof(*ss));
+
+    if (IS_GEN9(i965->intel.device_info))
+        ss->ss1.surface_mocs = GEN9_CACHE_PTE;
+
     ss->ss0.surface_type = I965_SURFACE_2D;
     ss->ss0.surface_format = format;
     ss->ss8.base_addr = surf_bo->offset + surf_bo_offset;
@@ -424,6 +429,7 @@ gen8_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_con
                            int format, int interleave_chroma,
                            int index)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct gen8_surface_state2 *ss2;
     dri_bo *ss2_bo;
     unsigned int tiling;
@@ -437,6 +443,10 @@ gen8_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_con
     assert(ss2_bo->virtual);
     ss2 = (struct gen8_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
     memset(ss2, 0, sizeof(*ss2));
+
+    if (IS_GEN9(i965->intel.device_info))
+        ss2->ss5.surface_object_mocs = GEN9_CACHE_PTE;
+
     ss2->ss6.base_addr = surf_bo->offset + surf_bo_offset;
     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
     ss2->ss1.width = width - 1;
diff --git a/src/i965_defines.h b/src/i965_defines.h
index e69f23f..f86ac8e 100755
--- a/src/i965_defines.h
+++ b/src/i965_defines.h
@@ -978,4 +978,6 @@
 #define MFC_BITSTREAM_BYTECOUNT_FRAME_REG       0x128A0
 #define MFC_IMAGE_STATUS_CTRL_REG               0x128B8
 
+#define GEN9_CACHE_PTE                  0x02
+
 #endif /* _I965_DEFINES_H_ */
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
index 91d1192..d911196 100644
--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -721,6 +721,7 @@ gen8_gpe_set_surface2_state(VADriverContextP ctx,
                             struct object_surface *obj_surface,
                             struct gen8_surface_state2 *ss)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     int w, h, w_pitch;
     unsigned int tiling, swizzle;
 
@@ -734,6 +735,9 @@ gen8_gpe_set_surface2_state(VADriverContextP ctx,
 
     memset(ss, 0, sizeof(*ss));
     /* ss0 */
+    if (IS_GEN9(i965->intel.device_info))
+        ss->ss5.surface_object_mocs = GEN9_CACHE_PTE;
+
     ss->ss6.base_addr = (uint32_t)obj_surface->bo->offset64;
     ss->ss7.base_addr_high = (uint32_t)(obj_surface->bo->offset64 >> 32);
     /* ss1 */
@@ -782,6 +786,7 @@ gen8_gpe_set_media_rw_surface_state(VADriverContextP ctx,
                                     struct object_surface *obj_surface,
                                     struct gen8_surface_state *ss)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     int w, h, w_pitch;
     unsigned int tiling, swizzle;
 
@@ -792,6 +797,9 @@ gen8_gpe_set_media_rw_surface_state(VADriverContextP ctx,
 
     memset(ss, 0, sizeof(*ss));
     /* ss0 */
+    if (IS_GEN9(i965->intel.device_info))
+        ss->ss1.surface_mocs = GEN9_CACHE_PTE;
+
     ss->ss0.surface_type = I965_SURFACE_2D;
     ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
     /* ss1 */
@@ -810,6 +818,7 @@ gen8_gpe_set_media_chroma_surface_state(VADriverContextP ctx,
                                     struct object_surface *obj_surface,
                                     struct gen8_surface_state *ss)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     int w, w_pitch;
     unsigned int tiling, swizzle;
     int cbcr_offset;
@@ -822,6 +831,9 @@ gen8_gpe_set_media_chroma_surface_state(VADriverContextP ctx,
     cbcr_offset = obj_surface->height * obj_surface->width;
     memset(ss, 0, sizeof(*ss));
     /* ss0 */
+    if (IS_GEN9(i965->intel.device_info))
+        ss->ss1.surface_mocs = GEN9_CACHE_PTE;
+
     ss->ss0.surface_type = I965_SURFACE_2D;
     ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
     /* ss1 */
@@ -897,6 +909,7 @@ gen8_gpe_set_buffer_surface_state(VADriverContextP ctx,
                                   struct i965_buffer_surface *buffer_surface,
                                   struct gen8_surface_state *ss)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     int num_entries;
 
     assert(buffer_surface->bo);
@@ -905,6 +918,9 @@ gen8_gpe_set_buffer_surface_state(VADriverContextP ctx,
     memset(ss, 0, sizeof(*ss));
     /* ss0 */
     ss->ss0.surface_type = I965_SURFACE_BUFFER;
+    if (IS_GEN9(i965->intel.device_info))
+        ss->ss1.surface_mocs = GEN9_CACHE_PTE;
+
     /* ss1 */
     ss->ss8.base_addr = (uint32_t)buffer_surface->bo->offset64;
     ss->ss9.base_addr_high = (uint32_t)(buffer_surface->bo->offset64 >> 32);