blob: 895506d93f4cf18b26347f1434d001d4fcb53b50 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
|
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-drc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A31 Dynamic Range Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
description: |
The DRC (Dynamic Range Controller) allows to dynamically adjust
pixel brightness/contrast based on histogram measurements for LCD
content adaptive backlight control.
properties:
compatible:
enum:
- allwinner,sun6i-a31-drc
- allwinner,sun6i-a31s-drc
- allwinner,sun8i-a23-drc
- allwinner,sun8i-a33-drc
- allwinner,sun9i-a80-drc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: The DRC interface clock
- description: The DRC module clock
- description: The DRC DRAM clock
clock-names:
items:
- const: ahb
- const: mod
- const: ram
resets:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: |
Input endpoints of the controller.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: |
Output endpoints of the controller.
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun6i-a31-ccu.h>
#include <dt-bindings/reset/sun6i-a31-ccu.h>
drc0: drc@1e70000 {
compatible = "allwinner,sun6i-a31-drc";
reg = <0x01e70000 0x10000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
<&ccu CLK_DRAM_DRC0>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_AHB1_DRC0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
drc0_in: port@0 {
reg = <0>;
drc0_in_be0: endpoint {
remote-endpoint = <&be0_out_drc0>;
};
};
drc0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
drc0_out_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_in_drc0>;
};
drc0_out_tcon1: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon1_in_drc0>;
};
};
};
};
...
|
