summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml
blob: 55dcad18b7c6d25d52aede343b3c0d8c6b773673 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX6 SoloX Clock Controller

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

properties:
  compatible:
    const: fsl,imx6sx-ccm

  reg:
    maxItems: 1

  interrupts:
    description: CCM provides 2 interrupt requests, request 1 is to generate
      interrupt for frequency or mux change, request 2 is to generate
      interrupt for oscillator read or PLL lock.
    items:
      - description: CCM interrupt request 1
      - description: CCM interrupt request 2

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: 32k osc
      - description: 24m osc
      - description: ipp_di0 clock input
      - description: ipp_di1 clock input
      - description: anaclk1 clock input
      - description: anaclk2 clock input

  clock-names:
    items:
      - const: ckil
      - const: osc
      - const: ipp_di0
      - const: ipp_di1
      - const: anaclk1
      - const: anaclk2

required:
  - compatible
  - reg
  - interrupts
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@20c4000 {
        compatible = "fsl,imx6sx-ccm";
        reg = <0x020c4000 0x4000>;
        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
        #clock-cells = <1>;
        clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
        clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
    };