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path: root/tools/testing/cxl/test/cxl.c
AgeCommit message (Expand)AuthorFilesLines
2023-12-04cxl: Add cxl_num_decoders_committed() usage to cxl_testDave Jiang1-2/+3
2023-10-27cxl/region: Fix x1 root-decoder granularity calculationsJim Harris1-1/+1
2023-07-20tools/testing/cxl: Remove unused SZ_512G macroXiao Yang1-4/+0
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-20/+10
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams1-3/+3
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-10/+10
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter1-10/+0
2023-02-14Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams1-2/+4
2023-02-14cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang1-1/+2
2023-02-14cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang1-1/+2
2023-02-10Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams1-10/+137
2023-02-10tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams1-10/+137
2023-01-26tools/testing/cxl: Remove cxl_test module math loading messageAlison Schofield1-3/+1
2023-01-05tools/testing/cxl: Prevent cxl_test from confusing production modulesDan Williams1-0/+8
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams1-2/+114
2022-12-05tools/testing/cxl: Add an RCH topologyDan Williams1-9/+141
2022-12-03tools/testing/cxl: Add XOR Math support to cxl_testAlison Schofield1-3/+115
2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter1-0/+10
2022-12-02tools/testing/cxl: Make mock CEDT parsing more robustDan Williams1-4/+6
2022-11-14tools/testing/cxl: Add bridge mocking supportDan Williams1-2/+8
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter1-8/+1
2022-11-04tools/testing/cxl: Add a single-port host-bridge regression configDan Williams1-19/+278
2022-11-04tools/testing/cxl: Fix some error exitsDan Williams1-2/+2
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams1-0/+46
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams1-3/+7
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams1-7/+16
2022-07-10tools/testing/cxl: Fix decoder default stateDan Williams1-1/+0
2022-07-10tools/testing/cxl: Add partition supportDan Williams1-39/+1
2022-07-10tools/testing/cxl: Expand CFMWS windowsDan Williams1-5/+5
2022-07-10tools/testing/cxl: Move cxl_test resources to the top of memoryDan Williams1-1/+2
2022-07-09cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams1-1/+1
2022-02-08tools/testing/cxl: Add a physical_node linkDan Williams1-2/+19
2022-02-08tools/testing/cxl: Enumerate mock decodersDan Williams1-20/+98
2022-02-08tools/testing/cxl: Mock one level of switchesDan Williams1-41/+97
2022-02-08tools/testing/cxl: Fix root port to host bridge assignmentDan Williams1-1/+1
2022-02-08cxl/memdev: Add numa_node attributeDan Williams1-0/+1
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams1-9/+5
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky1-2/+0
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams1-0/+29
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams1-21/+46
2021-11-15cxl/test: Mock acpi_table_parse_cedt()Dan Williams1-22/+46
2021-09-21tools/testing/cxl: Introduce a mock memory device + driverDan Williams1-1/+68
2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams1-0/+509
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