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2024-01-05drm/i915/display: use IS_DISPLAY_VER instead of IS_GRAPHICS_VERJani Nikula1-1/+1
Display code should not care about graphics version. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240104174350.823605-4-jani.nikula@intel.com
2024-01-05drm/i915/hdcp: use DISPLAY_VER instead of GRAPHICS_VERJani Nikula1-13/+15
Display code should not care about graphics version. While at it, abstract the version check to a separate macro. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240104174350.823605-3-jani.nikula@intel.com
2024-01-05drm/i915/dmc: use DISPLAY_VER instead of GRAPHICS_VERJani Nikula1-1/+1
Display code should not care about graphics version. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240104174350.823605-2-jani.nikula@intel.com
2024-01-05drm/i915/irq: use DISPLAY_VER instead of GRAPHICS_VERJani Nikula1-1/+1
Display code should not care about graphics version. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240104174350.823605-1-jani.nikula@intel.com
2024-01-04drm/i915/dp: Fix the PSR debugfs entries wrt. MST connectorsImre Deak1-5/+5
MST connectors don't have a static attached encoder, as their encoder can change depending on the pipe they use; so the encoder for an MST connector can't be retrieved using intel_dp_attached_encoder() (which may return NULL for MST). Most of the PSR debugfs entries depend on a static connector -> encoder mapping which is only true for eDP and SST DP connectors and not for MST. These debugfs entries were enabled for MST connectors as well recently to provide PR information for them, but handling MST connectors needs more changes. Fix this by not adding for now the PSR entries on MST connectors. To make things more uniform add the entries for SST connectors on all platforms, not just on platforms supporting DP2.0. v2: - Keep adding the entries for SST connectors. (Jouni) - Add a TODO: comment for MST support. Fixes: ef75c25e8fed ("drm/i915/panelreplay: Debugfs support for panel replay") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9850 Cc: Animesh Manna <animesh.manna@intel.com> Cc: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240103152609.2434100-1-imre.deak@intel.com
2024-01-04drm/i915/display: Skip C10 state verification in case of fastsetMika Kahola1-0/+3
PLL's are not programmed in case of fastset so the state verification compares bios programmed PLL values against sw PLL values. To overcome this limitation, we can skip the state verification for C10 in fastset case as the driver is not writing PLL values. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231219123246.832245-1-mika.kahola@intel.com
2024-01-04drm/i915/display: Cleanup mplla/mpllb selectionMika Kahola1-24/+15
The function intel_c20_use_mplla() is not really widely used and can be replaced with the more suitable pll->tx[0] & C20_PHY_USE_MPLLB expression. Let's remove the intel_c20_use_mplla() alltogether and replace mplla/mpllb selection by checking mpllb bit. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240102115741.118525-4-mika.kahola@intel.com
2024-01-04drm/i915/display: Store hw clock for C20Mika Kahola1-45/+52
We can calculate the hw port clock during the hw readout and store it as pll_state->clock for C20 state verification. In order to do that we need to move intel_c20pll_calc_port_clock() function. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240102115741.118525-3-mika.kahola@intel.com
2024-01-04drm/i915/display: Fix C20 pll selection for state verificationMika Kahola1-10/+15
Add pll selection check for C20 as well as clock state verification0. We have been relying on sw state to select A or B pll's. This is incorrect as the hw might see this selection differently. This patch fixes this shortcoming by reading pll selection for both sw and hw states and compares if these two selections match. Fixes: 59be90248b42 ("drm/i915/mtl: C20 state verification") v2: reword commit message and include fix to a original commit (Imre) Compare pll selection (Jani) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240102115741.118525-2-mika.kahola@intel.com
2024-01-03drm/i915/mtl: Add fake PCH for Meteor LakeHaridhar Kalvala9-29/+19
Correct the implementation trying to detect MTL PCH with the MTL fake PCH id. On MTL, both the North Display (NDE) and South Display (SDE) functionality reside on the same die (the SoC die in this case), unlike many past platforms where the SDE was on a separate PCH die. The code is (badly) structured today in a way that assumes the SDE is always on the PCH for modern platforms, so on platforms where we don't actually need to identify the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows us to avoid restructuring a bunch of the code.we've been assigning a "fake PCH" as a quick hack that allows us to avoid restructuring a bunch of the code. Removed unused macros of LNL amd MTL as well. v2: Reorder PCH_MTL conditional check (Matt Roper) Reverting to PCH_MTL for PICA interrupt(Matt Roper) Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231219185233.1469675-1-haridhar.kalvala@intel.com
2023-12-29drm/i915/bios: remove some unused leftover declarationsJani Nikula1-3/+0
Remove some unused declarations probably left behind after some refactoring. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231221105414.1518267-1-jani.nikula@intel.com
2023-12-22drm/i915/display: Take care of VSC select field in video dip ctl registerJouni Högander1-3/+5
We need to configure VSC Select field in video dip ctl if we want to have e.g. colorimetry date in our VSC SDP. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Shawn Lee <shawn.c.lee@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231220103609.1384523-8-jouni.hogander@intel.com
2023-12-22drm/i915/display: Read PSR configuration before VSC SDPJouni Högander1-2/+2
VSC SDP sending is taken care by PSR HW and it's not enabled in VIDEO_DIP_CTL when PSR is enabled. Readback of VSC SDP is depending on VSC_SDP being set in intel_crtc_state->infoframes.enabled. In case of PSR setting this flag is taken care by PSR code -> read back PSR configuration before reading VSC SDP otherwise we get pipeconfig mismatch error. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Shawn Lee <shawn.c.lee@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231220103609.1384523-7-jouni.hogander@intel.com
2023-12-22drm/i915/display: Ignore only psr specific part of vsc sdpJouni Högander2-7/+6
Pipe config check is currently ignoring vsc sdp changes completely if psr is enabled. We want to ignore only PSR part of it as there might be changes in colorimetry data. Also read back vsc_sdp when psr is used. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Shawn Lee <shawn.c.lee@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231220103609.1384523-6-jouni.hogander@intel.com
2023-12-22drm/i915/display: Fix vsc_sdp computationJouni Högander1-29/+19
Currently colorimetry data is not added for psr1 or non-psr case. Fix this by adding it as needed. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Shawn Lee <shawn.c.lee@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231220103609.1384523-5-jouni.hogander@intel.com
2023-12-22drm/i915/display: Unify VSC SPD preparationJouni Högander3-50/+6
There is no specific reason to prepare VSC SDP for PSR case somehow differently. Unify PSR and non-PSR preparation. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Shawn Lee <shawn.c.lee@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231220103609.1384523-4-jouni.hogander@intel.com
2023-12-22drm/i915/display: Move colorimetry_support from intel_psr to intel_dpJouni Högander3-8/+10
Colorimetry support is not really a PSR specific thing. Move it to intel_dp struct and use it also when preparing vsc sdp for non-PSR case. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Shawn Lee <shawn.c.lee@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231220103609.1384523-3-jouni.hogander@intel.com
2023-12-22drm/i915/display: Remove intel_crtc_state->psr_vscJouni Högander2-3/+2
There is no really need to have separate vsc for psr usage. Use intel_crtc_state->infoframes.vsc instead. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Shawn Lee <shawn.c.lee@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231220103609.1384523-2-jouni.hogander@intel.com
2023-12-22drm/i915/hdcp: Fail Repeater authentication if Type1 device not presentSuraj Kandpal1-0/+6
Fail repeater authentication step in case RX_INFO indicates HDCP1.x or HDCP2.0/2.1 device is present downstream in repeater topology and content type set by userspace is Type1. --v2 -Fix build error. --v3 -remove mst encoder check as branch device also act as repeater Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231215050915.2070119-1-suraj.kandpal@intel.com
2023-12-20drm/i915/cdclk: Remove divider field from tablesGustavo Sousa1-135/+134
The cdclk tables were introduced with commit 736da8112fee ("drm/i915: Use literal representation of cdclk tables"). It has been almost 4 years and the divider field was not really used yet. Let's remove it. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231124205522.57696-2-gustavo.sousa@intel.com
2023-12-19drm/i915/dp: Fix passing the correct DPCD_REV for drm_dp_set_phy_test_patternKhaled Almahallawy1-1/+1
Using link_status to get DPCD_REV fails when disabling/defaulting phy pattern. Use intel_dp->dpcd to access DPCD_REV correctly. Fixes: 8cdf72711928 ("drm/i915/dp: Program vswing, pre-emphasis, test-pattern") Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231213211542.3585105-3-khaled.almahallawy@intel.com
2023-12-19drm/i915/dp: Add TPS4 PHY test pattern supportKhaled Almahallawy2-1/+21
Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests. v2: rebase v3: - Enable TPS4 only for supported platforms (Jani) - Uppercase in macro names (Jani) - Fix indentation (Jani) - Use drm_warn instead of WARN v4: Disable TPS4 pattern on supported platforms only Bspec: 50482, 50484, 7557 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231213211542.3585105-2-khaled.almahallawy@intel.com
2023-12-19drm/i915/dp: Use LINK_QUAL_PATTERN_* Phy test pattern namesKhaled Almahallawy1-6/+6
Starting from DP2.0 specs, DPCD 248h is renamed LINK_QUAL_PATTERN_SELECT and it has the same values of registers DPCD 10Bh-10Eh. Use the PHY pattern names defined for DPCD 10Bh-10Eh in order to add CP2520 Pattern 3 (TPS4) phy pattern support in the next patch of this series and DP2.1 PHY patterns for future series. v2: rebase Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231213211542.3585105-1-khaled.almahallawy@intel.com
2023-12-19drm/i915: Ratelimit debug log in vm_fault_ttmNirmoy Das1-2/+3
Test like i915_gem_mman_live_selftests/igt_mmap_migrate can cause dmesg spamming. Use ratelimit api to reduce log rate. References: https://gitlab.freedesktop.org/drm/intel/-/issues/7038 Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231206210948.106238-3-andi.shyti@linux.intel.com
2023-12-19drm/i915/hdcp: fix intel_hdcp_get_repeater_ctl() error return valueJani Nikula1-2/+2
intel_hdcp_get_repeater_ctl() is supposed to return unsigned register contents. Returning negative error values is unexpected, and none of the callers check for that. Sort of fix the error cases by returning 0. I don't think we should hit these cases anyway, and using 0 for the registers is safer than 0xffffffea (-EINVAL). Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231219104746.1065431-2-jani.nikula@intel.com
2023-12-19drm/i915/hdcp: unify connector logging formatJani Nikula1-34/+34
It's customary to debug log connectors using [CONNECTOR:%d:%s] format. Make the HDCP code follow suit. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231219104746.1065431-1-jani.nikula@intel.com
2023-12-18drm/i915/display: Remove dead code around intel_atomic_helper->free_listJouni Högander4-35/+0
After switching to directly using dma_fence instead of i915_sw_fence we have left some dead code around intel_atomic_helper->free_list. Remove that dead code. v2: Remove intel_atomic_state->freed as well Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231114134141.2527694-1-jouni.hogander@intel.com
2023-12-18drm/i915/dmc: Print out the DMC mmio register list at fw load timeVille Syrjälä1-0/+18
To help with debugging print out the mmio list contained in the DMC firmware. Also highlight the event registers, and whether we're going to disable them or not. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231211213750.27109-5-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2023-12-18drm/i915/dmc: Also disable HRR event on TGL/ADLS main DMCVille Syrjälä2-0/+6
Unlike later platforms TGL/ADLS has the half refresh rate (HRR) event on the main DMC (as opposed to the pipe DMC). Since we're disabling that event on all later platforms already let's do the same on TGL/ADLS as well. There is supposedly a bit somewhere (DMC_CHICKEN on TGL) to make the handler not do anything, but we don't currently have code to frob it. Though that bit should be off by default, the ADL+ experience has shown us that trusting any of this isn't a good idea. So seems safer to just disable all event handlers we know that we don't need. Also the TGL/ADLS DMC firmware is apparently using the wrong event (undelayed vblank) here anyway. It should be using the delayed vblank event instead (like ADL+ firmware does), but they didn't release a firmware fix for this and instead just hacked around this in the Windows driver code :/ v2: Also disable the event on ADLS (Imre) Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231213150807.21331-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2023-12-18drm/i915/dmc: Also disable the flip queue event on TGL main DMCVille Syrjälä1-78/+5
Unlike later platforms TGL has its flip queue event (CLK_MSEC) on the main DMC (as opposed to the pipe DMC). Currently we're doing a second pass to disable that, but let's just follow the same approach as the later platforms and never even enable the event in the first place. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231211213750.27109-3-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2023-12-18drm/i915/dmc: Don't enable any pipe DMC eventsVille Syrjälä1-2/+41
The pipe DMC seems to be making a mess of things in ADL. Various weird symptoms have been observed such as missing vblank irqs, typicalle happening when using multiple displays. Keep all pipe DMC event handlers disabled until needed (which is never atm). This is also what Windows does on ADL+. We can also drop DG2 from disable_all_flip_queue_events() since on DG2 the pipe DMC is the one that handles the flip queue events. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8685 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231211213750.27109-2-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2023-12-15drm/i915/mtl: Fix HDMI/DP PLL clock selectionImre Deak1-1/+2
Select the HDMI specific PLL clock only for HDMI outputs. Fixes: 62618c7f117e ("drm/i915/mtl: C20 PLL programming") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231213220526.1828827-1-imre.deak@intel.com
2023-12-13drm/i915: Simplify intel_ddi_compute_min_voltage_level()Ville Syrjälä3-7/+7
Drop the redundant dev_priv parameters from intel_ddi_compute_min_voltage_level() to make life easier. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-9-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915/mtl: Calculate the correct voltage level from port_clockVille Syrjälä1-1/+3
On MTL we need to bump the voltage level to only 1 (not 2) when port clock exceeds 594MHz. Make it so. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-8-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915: Split intel_ddi_compute_min_voltage_level() into platform variantsVille Syrjälä1-7/+30
The mess inside intel_ddi_compute_min_voltage_level() is illegible. Clean it up a bit by splitting the internals into per-platform functions. TODO: make it a vfunc? Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-7-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915/mtl: Fix voltage_level for cdclk==480MHzVille Syrjälä1-1/+1
Allow MTL to use voltage level 1 for 480MHz cdclk, instead of the voltage level 2 that it's currently using. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-6-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tablesVille Syrjälä1-30/+57
The cdclk->voltage_level if ladders are hard to read, especially as they're written the other way around compared to how bspec lists the limits. Let's rewrite them to use simple arrays that gives us the max cdclk for each voltage level. v2: Bump the jsl/ehl max cdclk in the table to 652.8 MHz to accommodate JSL machines in CI that boot with high cdclk Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231211221759.29725-1-ville.syrjala@linux.intel.com
2023-12-13drm/i915/cdclk: Remove the assumption that cdclk divider==2 when using squashingVille Syrjälä1-7/+5
Currently we have a hardcoded assumption that the cdclk divider (2*cd2x divider) is always 2 when squashing is used. While that is true for all current platforms it might not hold in the future. So eliminate the assumption and calculate the correct divider from the other parameters. v2: s/cd2x divider/cdclk divider/ (Gustavo) s/clock/unsquashed_cdclk/ (Gustavo) Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231211221636.29658-1-ville.syrjala@linux.intel.com
2023-12-13drm/i915/cdclk: Give the squash waveform length a nameVille Syrjälä1-2/+4
Replace the slightly magic 'size = 16' with a bit more descriptive name. We'll have another user for this value later on. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-3-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915/cdclk: s/-1/~0/ when dealing with unsigned valuesVille Syrjälä1-2/+2
cdclk_pll_is_unknown() used ~0 when checking for the "VCO is unknown" value, but the assignment uses -1. They are the same in the end, but let's use the same ~0 form on both sides for consistency. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-2-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915: Reject async flips with bigjoinerVille Syrjälä1-0/+11
Currently async flips are busted when bigjoiner is in use. As a short term fix simply reject async flips in that case. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9769 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231211081134.2698-1-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2023-12-13drm/i915/display: Wait for PHY readiness not needed for disabling sequenceMika Kahola1-9/+16
When going through the disconnection flow we don't need to wait for PHY readiness and hence we can skip the wait part. For disabling the function returns false as an indicator that the power is not enabled. After all, we are not even using the return value when Type-C is disconnecting. v2: Cleanup for increased readibility (Imre) BSpec: 65380 For VLK-53734 Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231212115130.485911-1-mika.kahola@intel.com
2023-12-13drm/i915/display: Get bigjoiner config before dsc config during readoutAnkit Nautiyal1-1/+1
Currently we get bigjoiner config after the dsc get config, during HW readout. Since dsc_get_config now uses bigjoiner flags/pipes to compute DSC PPS parameter pic_width, this results in a state mismatch when Bigjoiner and DSC are used together. So call get bigjoiner config before calling dsc get config function. Fixes: 8b70b5691704 ("drm/i915/vdsc: Fill the intel_dsc_get_pps_config function") Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231122064627.905828-1-ankit.k.nautiyal@intel.com
2023-12-11drm/i915/display: do not use cursor size reduction on MTLAndrzej Hajda1-1/+1
Cursor size reduction is not supported since MTL. Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231124-cur_size_reduction-v1-1-30495dba475f@intel.com
2023-12-11drm/i915/edp: don't write to DP_LINK_BW_SET when using rate selectJani Nikula1-10/+21
The eDP 1.5 spec adds a clarification for eDP 1.4x: > For eDP v1.4x, if the Source device chooses the Main-Link rate by way > of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0]. We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the panel to ignore the rate set method. Moreover, 0 is a reserved value for DP_LINK_BW_SET, and should not be used. v2: Improve the comments (Ville) Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081 Tested-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231205180551.2476228-1-jani.nikula@intel.com
2023-12-09drm/i915: Drop irqsave/restore for flip_done_handler()Ville Syrjälä1-4/+2
Since flip_done_handler() is always called from the irq handler we can skip the irqsave/restore dance. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230928152450.30109-2-ville.syrjala@linux.intel.com Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
2023-12-09drm/i915: Stop accessing crtc->state from the flip done irqVille Syrjälä3-6/+15
Assuming crtc->state is pointing at the correct thing for the async flip commit is nonsense. If we had already queued up multiple commits this would point at the very lates crtc state even if the older commits hadn't even happened yet. Instead properly stage/arm the event like we do for async flips. Since we don't need to arm multiple of these at the same time we don't need a list like the normal vblank even processing uses. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230928152450.30109-1-ville.syrjala@linux.intel.com Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
2023-12-08drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_stateRadhakrishna Sripada2-22/+22
With the cleanup of the misleading clock value to avoid extra calculations to convert between link_bit_rate and clock, use one standard "clock" field for the c20 pll which works with crtc_state->port_clock field. Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207221025.2032207-4-radhakrishna.sripada@intel.com
2023-12-08drm/i915/mtl: Remove misleading "clock" field from C20 pll_stateRadhakrishna Sripada2-20/+1
The field link_bit_rate serves as the actual clock value for the C20 pll_state structure. Remove the misleading clock field. The subsequent patch would rename the link_bit_rate as the clock field. Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207221025.2032207-3-radhakrishna.sripada@intel.com
2023-12-08drm/i915/mtl: Use port clock compatible numbers for C20 phyRadhakrishna Sripada1-21/+22
In C20 pll_state link_bit_rate and clock fields are bit redundant. Since many of the helpers assume the clock values, which are different from link_bit_rate for dp2.0, convert the helpers to use the numbers that are compatible with link_bit_rate. Currently link_bit_rate is compatible with crtc_state->port_clock. The function intel_c20pll_calc_port_clock returns the number which is compatible with crtc_state->port_clock. In order to avoid extra conversions b/ween clock and link_bit_rate, remove "clock" field from the C20 pll_state and then rename "link_bit_rate" as "clock". While at it rely on crtc_state->port_clock during C20 Pll programming. Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207221025.2032207-2-radhakrishna.sripada@intel.com
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 09:31:25 +0000