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path: root/drivers
AgeCommit message (Expand)AuthorFilesLines
2024-01-05drm/i915/display: use IS_DISPLAY_VER instead of IS_GRAPHICS_VERJani Nikula1-1/+1
2024-01-05drm/i915/hdcp: use DISPLAY_VER instead of GRAPHICS_VERJani Nikula1-13/+15
2024-01-05drm/i915/dmc: use DISPLAY_VER instead of GRAPHICS_VERJani Nikula1-1/+1
2024-01-05drm/i915/irq: use DISPLAY_VER instead of GRAPHICS_VERJani Nikula1-1/+1
2024-01-04drm/i915/dp: Fix the PSR debugfs entries wrt. MST connectorsImre Deak1-5/+5
2024-01-04drm/i915/display: Skip C10 state verification in case of fastsetMika Kahola1-0/+3
2024-01-04drm/i915/display: Cleanup mplla/mpllb selectionMika Kahola1-24/+15
2024-01-04drm/i915/display: Store hw clock for C20Mika Kahola1-45/+52
2024-01-04drm/i915/display: Fix C20 pll selection for state verificationMika Kahola1-10/+15
2024-01-03drm/i915/mtl: Add fake PCH for Meteor LakeHaridhar Kalvala9-29/+19
2023-12-29drm/i915/bios: remove some unused leftover declarationsJani Nikula1-3/+0
2023-12-22drm/i915/display: Take care of VSC select field in video dip ctl registerJouni Högander1-3/+5
2023-12-22drm/i915/display: Read PSR configuration before VSC SDPJouni Högander1-2/+2
2023-12-22drm/i915/display: Ignore only psr specific part of vsc sdpJouni Högander2-7/+6
2023-12-22drm/i915/display: Fix vsc_sdp computationJouni Högander1-29/+19
2023-12-22drm/i915/display: Unify VSC SPD preparationJouni Högander3-50/+6
2023-12-22drm/i915/display: Move colorimetry_support from intel_psr to intel_dpJouni Högander3-8/+10
2023-12-22drm/i915/display: Remove intel_crtc_state->psr_vscJouni Högander2-3/+2
2023-12-22drm/i915/hdcp: Fail Repeater authentication if Type1 device not presentSuraj Kandpal1-0/+6
2023-12-20drm/i915/cdclk: Remove divider field from tablesGustavo Sousa1-135/+134
2023-12-19drm/i915/dp: Fix passing the correct DPCD_REV for drm_dp_set_phy_test_patternKhaled Almahallawy1-1/+1
2023-12-19drm/i915/dp: Add TPS4 PHY test pattern supportKhaled Almahallawy2-1/+21
2023-12-19drm/i915/dp: Use LINK_QUAL_PATTERN_* Phy test pattern namesKhaled Almahallawy1-6/+6
2023-12-19drm/i915: Ratelimit debug log in vm_fault_ttmNirmoy Das1-2/+3
2023-12-19drm/i915/hdcp: fix intel_hdcp_get_repeater_ctl() error return valueJani Nikula1-2/+2
2023-12-19drm/i915/hdcp: unify connector logging formatJani Nikula1-34/+34
2023-12-18drm/i915/display: Remove dead code around intel_atomic_helper->free_listJouni Högander4-35/+0
2023-12-18drm/i915/dmc: Print out the DMC mmio register list at fw load timeVille Syrjälä1-0/+18
2023-12-18drm/i915/dmc: Also disable HRR event on TGL/ADLS main DMCVille Syrjälä2-0/+6
2023-12-18drm/i915/dmc: Also disable the flip queue event on TGL main DMCVille Syrjälä1-78/+5
2023-12-18drm/i915/dmc: Don't enable any pipe DMC eventsVille Syrjälä1-2/+41
2023-12-15drm/i915/mtl: Fix HDMI/DP PLL clock selectionImre Deak1-1/+2
2023-12-13drm/i915: Simplify intel_ddi_compute_min_voltage_level()Ville Syrjälä3-7/+7
2023-12-13drm/i915/mtl: Calculate the correct voltage level from port_clockVille Syrjälä1-1/+3
2023-12-13drm/i915: Split intel_ddi_compute_min_voltage_level() into platform variantsVille Syrjälä1-7/+30
2023-12-13drm/i915/mtl: Fix voltage_level for cdclk==480MHzVille Syrjälä1-1/+1
2023-12-13drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tablesVille Syrjälä1-30/+57
2023-12-13drm/i915/cdclk: Remove the assumption that cdclk divider==2 when using squashingVille Syrjälä1-7/+5
2023-12-13drm/i915/cdclk: Give the squash waveform length a nameVille Syrjälä1-2/+4
2023-12-13drm/i915/cdclk: s/-1/~0/ when dealing with unsigned valuesVille Syrjälä1-2/+2
2023-12-13drm/i915: Reject async flips with bigjoinerVille Syrjälä1-0/+11
2023-12-13drm/i915/display: Wait for PHY readiness not needed for disabling sequenceMika Kahola1-9/+16
2023-12-13drm/i915/display: Get bigjoiner config before dsc config during readoutAnkit Nautiyal1-1/+1
2023-12-11drm/i915/display: do not use cursor size reduction on MTLAndrzej Hajda1-1/+1
2023-12-11drm/i915/edp: don't write to DP_LINK_BW_SET when using rate selectJani Nikula1-10/+21
2023-12-09drm/i915: Drop irqsave/restore for flip_done_handler()Ville Syrjälä1-4/+2
2023-12-09drm/i915: Stop accessing crtc->state from the flip done irqVille Syrjälä3-6/+15
2023-12-08drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_stateRadhakrishna Sripada2-22/+22
2023-12-08drm/i915/mtl: Remove misleading "clock" field from C20 pll_stateRadhakrishna Sripada2-20/+1
2023-12-08drm/i915/mtl: Use port clock compatible numbers for C20 phyRadhakrishna Sripada1-21/+22
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 04:20:01 +0000